Page 1 of 11

GENERAL TECHNICAL SPECIFICATIONS

Serial
No

Description of Requirements


Compliance

Specific Deviation if Any
1 The vendor must provide detailed product literature in the form of
catalogues / brochures along with the technical bid for the product
clearly mentioning the model number / part number / OEM details
etc.

2 Vendor must provide authorization certificate from OEM for all
quoted items

3 For each item and specification, the vendor must give a compliance
statement with actual values where required. Any deviation from
the required specification given in RFP should be mentioned in the
column provided for the same.

4 All power cables and adaptors must be of Indian standard.
5 Demonstration is needed for the working of all the components /
sub units at NPOL after the purchase before issuing acceptance.

6 For item NI myRIO EMBEDDED STUDENT DESIGN DEVICE AND
ACCESSERIES OR EQUIVALENT, LabView RF FPGA training for 5
scientists for 3 days at NPOL must be provided.

7 For AVNET VIRTEX-6 FPGA DSP KIT WITHAD/DA OR EQUIVALENT,
XILINX FPGA DSP tool training for 5 scientists for 5 days at NPOL
must be provided.

8 For item ETTUS REASEARCH USRP B210 BUS SERIES OR
EQUIVALENT , Python and GNURADIO training for 5 scientists for 5
days at NPOL must be provided.




Enclosure to T.E. No. NPOL/14SOT282/LP, Dated- 07th January 2014
ANNEXURE-II
Page 2 of 11

DETAILED TECHNICAL SPECIFICATIONS
Description ITEM NO. 1 NI myDAQ DEVICE AND ACCESSORIES OR EQUIVALENT COMPLIANCE WITH
GIVEN SPECIFICATION
SPECIFY DEVIATION IF ANY
Analog Input Number of channels 2 differential or 1 stereo audio input
ADC resolution 16 bits
Maximum sampling rate 200 kS/s
Timing accuracy 100 ppm of sample rate
Timing resolution 10 ns
Range of Analog input 10 V, 2 V, DC-coupled
Passband (3 dB) Analog input DC to 400 kHz
Connector type Analog input Screw terminals, 3.5 mm stereo jack
Input FIFO size 4,095 samples
Common-mode rejection ratio 70 dB
Input impedance Device on AI+ or AI to
AGND
Greater than 10 G || 100 pF
Analog Output Number of channels 2 differential or 1 stereo audio input
DAC resolution 16 bits
Maximum sampling rate 200 kS/s
Range of Analog output 10 V, 2 V, DC-coupled
Maximum output current 2 mA
Output impedance Analog output 1
Connector type of Analog output Screw terminals, 3.5 mm stereo jack
Timing accuracy 100 ppm of sample rate
Timing resolution 10 ns
Slew rate 4 V/s
Output FIFO size 8,191 samples
Digital IO Number of lines 8
Direction control Each line individually programmable input/
output

Update mode Software-timed
Pull-down resistor 75 k
Enclosure to T.E. No. NPOL/14SOT282/LP, Dated- 07th January 2014
ANNEXURE-II
Page 3 of 11

Logic level 5 V compatible LVTTL input;3.3 V LVTTL output
Number of counter/timers 1
Resolution 32 bits
Internal base clocks 100 MHz
Base clock accuracy 100 ppm
Maximum counting and pulse generation
update rate
1 MS/s
Data transfers Programmed I/O
Update mode Software-timed
Connectivity High Speed USB 2.0
Software
Development
LabView compatible having the following synthetic instruments : Oscilloscope, Dynamic
Signal Analyzer, Bode Analyzer, Function Generator, Arbitrary Waveform Generator,
Digital Multimeter, Digital Reader, Digital Writer

Power Supply USB Powered
Mechanical
Specifications
Less than 15 cm x 9 cm x 3 cm (without screw terminal connector)
Weight less than 180g










(DETAILED TECHNICAL SPECIFICATIONS Contd.) NI myDAQ DEVICE AND ACCESSORIES OR EQUIVALENT
Encl. to T.E. No. NPOL/14SOT282/LP, Dated- 07th January 2014
ANNEXURE-II
Page 4 of 11

DETAILED TECHNICAL SPECIFICATIONS
Description ITEM NO. 2 NI myRIO EMBEDDED STUDENT DESIGN DEVICE AND ACCESSERIES OR
EQUIVALENT
COMPLIANCE WITH
GIVEN SPECIFICATION
SPECIFY DEVIATION IF
ANY
Processor Processor type & FPGA 2 core Xilinx Z-7010
Processor speed 667 MHz
Nonvolatile memory 256 MB
DDR3 memory 512 MB
DDR3 clock frequency 533 MHz
DDR3 data bus width 16 bits
Wireless
Characteristics
Radio mode IEEE 802.11 b,g,n
Frequency band ISM 2.4 GHz
Channel width 20 MHz
TX power +10 dBm max (10 mW)
Analog Input Aggregate sample rate 500 kS/s
No of Channels 4
Resolution 12 bits
Overvoltage protection 16 V
MXP connector Configuration Four single-ended channels per connector
Input impedance Greater than 500 K acquiring at 500 Ks/s
Nominal range 0 V to +5 V
Bandwidth Greater than 300 kHz
Analog Output Aggregate maximum update rates 345 kS/s
No of Channels 2
Resolution 12 bits
Overvoltage protection 16 V
MXP connector Configuration Four single-ended channels per connector
Range 0 V to +5 V
Slew rate 0.3 V/s
Current drive 3 mA
Startup voltage 0 V after FPGA initialization
Digital IO No of Lines 16
Enclosure to T.E. No. NPOL/14SOT282/LP, Dated- 07th January 2014 ANNEXURE-II
Page 5 of 11

Number of lines MXP connectors 2 ports of 16 DIO lines, one UART.RX and one
UART.TX line per connector

Direction control Each DIO line individually programmable as
input or output

Logic level 5 V compatible LVTTL input; 3.3 V LVTTLoutput
Maximum frequencies for
secondary digital functions


UART lines


Accelerometer Number of axes 3
Range 8 g
Resolution 12 bits
Sample rate 800 S/s
Noise 3.9 mgrms typical at 25 C



10 Analog inputs, 6 Analog outputs, 40 digital I/O lines
Wi-Fi, LEDs, push button, accelerometer on-board
Xilinx FPGA and Dual-core ARM Cortex-A9 processor
Programmable with LabVIEW or C; adaptable for different programming levels

Connectivity High Speed USB 2.0
Software LabView compatible
Power Supply Power supply voltage range 6-16 VDC
Maximum power consumption 14 W
Typical idle power consumption 2.6 W
Mechanical Specs Dimensions : 14cm (H) x 9cm (W) x 2.5cm (D) Weight : less than 200g
Accessories
Required
Embedded Systems Kit, Expansion Port Protoboard, Mechatronics Kit, Panel Mount Kit,
Starter Kit, Power Supply


(DETAILED TECHNICAL SPECIFICATIONS Contd.) NI myRIO EMBEDDED STUDENT DESIGN DEVICE AND ACCESSERIES OR EQUIVALENT
Enclosure to T.E. No. NPOL/14SOT282/LP, Dated- 07th January 2014
ANNEXURE-II
Page 6 of 11

DETAILED TECHNICAL SPECIFICATIONS
Description

ITEM NO. 3 NI PXI 5690 RF PROGRAMMABLE AMPLIFIER / ATTENUATOR OR
EQUIVALENT
COMPLIANCE WITH
GIVEN SPECIFICATION
SPECIFY DEVIATION IF ANY
Frequency Coverage 100 kHz to 3.0 GHz
Channels 2-channel fixed or programmabl165 dBm/Hz extended noise floor
30 dB fixed gain on channel 0
-10 to +20 dB programmable gain on channel 1
Typical 5 dB noise figure on channel 0
Typical -1.5 dB loss on by pass gain with bypass


Connectivity PXI Platform Compliant
Software
Development
LabView compatible

Power Supply


Mechanical
Specifications
Physical Dimensions(L W H) 3U, One Slot, PXI/cPCI Module 21.6 2.0 13.0 cm
Weight : 263 g

Cables Required SMA male to SMA male, 50 coaxial cable 0.15 m (6 nos)
Enclosure to T.E. No. NPOL/14SOT282/LP, Dated- 07th January 2014
ANNEXURE-II
Page 7 of 11

DETAILED TECHNICAL SPECIFICATIONS
Description ITEM NO. 4 NI USRP 2930 AND ACCESSORIES OR EQUIVALENT COMPLIANCE WITH
GIVEN SPECIFICATION
SPECIFY DEVIATION
IF ANY
Transmitter Parameters Values
Frequency range 50 MHz to 2.2 GHz
Maximum
Instantaneous
Bandwidth
At 8 bit sample width - 35 MHz or Better (max 40 MHz)
At 16 bit sample width 15 Mhz or Better (max 20 MHz)
Frequency Step Better than 1KHz
Maximum Output
Power
50 MHz to 1.2 GHz - 50 mW to 100 mW (17 dBm to 20 dBm)
1.2GHz to 2.2 GHz - 30 mW to 70 mW (15 dBm to 18 dBm)
Gain Range 0 dB to 31 dB
Gain Step < 2 dB
Frequency Accuracy 2.5ppm
Max I/Q Sample Rate At 8 bit sample width 50 MS/s
At 16 bit sample width- 25 MS/s
DAC 2 channel 400 MS/s 16 bit with SFDR 80 dB
Receiver Frequency range 50 MHz to 2.2 GHz
Frequency Step Better than 1KHz
Gain Range 0 dB to 30 dB or higher (max 31.5 dB)
Gain Step < 1 dB (0.5 dB typical)
Noise Figure better than 10dB (typical 5 dB to 7 dB)
Max input power 0 dBm
Frequency Accuracy 2.5ppm
Maximum
Instantaneous
Bandwidth
At 8 bit sample width - 35 MHz or Better (max 40 MHz)
At 16 bit sample width 15 Mhz or Better (max 20 MHz)
Max I/Q Sample Rate

At 8 bit sample width 50 MS/s
At 16 bit sample width- 25 MS/s
ADC 2 channels, 100 MS/s, 14 bit with SFDR 88 dB
Enclosure to T.E. No. NPOL/14SOT282/LP, Dated- 07th January 2014 ANNEXURE-II
Page 8 of 11

GPS Signal Frequency 1574 MHz
PPS Accuracy 50 ns
Antenna Connector SMA Female
Connectivity Gigabit Ethernet (CAT5E 3m cables (02 nos) to be provided along with the unit)
Software
Development
Support for Modulation Toolkit, and Math Script RT Module for .m file script execution
in LabVIEW

Power
Consumption
Maximum 18W power Consumption
Mechanical
Specifications
Dimension less than 7 X 2.5 X 9 inches


Cables Required SMA Cable and 30dB Attenuator Loop Back comprising if 2 SMA-M to SMA-M
cables (60cm/2ft) and 2 SMA-F to SMA-M Attenuators (30dB, 50Ohm, DC-
6GHz). (02 nos)
MCX-M to SMA-F Bulkhead, 0.2M (04 nos)
SMA Female to BNC Male adapter. To be used with SMA-SMA cable when
connecting to a device with a female BNC. Frequency Range: 0-12 GHz
Nominal Impedance: 50 Ohms
Body and Contacts Finish: Gold plated (MIL-G-45204, Type II, Class 2) (04 nos)
SMA-M to SMA-F Bulkhead, 0.2M (04 nos)
Cable Assembly, SMA to SMA, 0.5M (4 nos)
Cable Assembly, USRP MIMO Data and Sync Cable, 0.5M (02 nos)

Antenna VERT400 144 MHz, 400 MHz, and 1200 MHz Tri-band omni-directional vertical
antenna.
Extended receive range: 118-160MHz, 250-290MHz,360-390MHz, 420-470MHz, 820-
960MHz, 1260-1300MHz
Gain & Wave:146MHz 0dBi 14 wave, 446MHz 0dBi 14 wave, 1200MHz 3.4dBi 58
wave
Max Power: 10 watts
Length: 17 cm (6.5 inches)Connector: SMA


(DETAILED TECHNICAL SPECIFICATIONS Contd.) NI USRP 2930 AND ACCESSORIES OR EQUIVALENT
ANNEXURE-II
Encl. to T.E. No. NPOL/14SOT282/LP, Dated-07th January 2014
Page 9 of 11

DETAILED TECHNICAL SPECIFICATIONS

Description ITEM NO. 5 AVNET VIRTEX-6 FPGA DSP KIT WITHAD/DA OR
EQUIVALENT
COMPLIANCE WITH GIVEN
SPECIFICATION
SPECIFY DEVIATION IF ANY
Xilinx ML605 Development Board

FPGA XC6VLX240T-1FFG1156
Configuration Onboard configuration circuitry (USB to JTAG)
16 MB Platform Flash XL
32 MB Parallel (BPI) Flash
System ACE CF with 2 GB Compact FLASH

Communications and
Networking
10/100/1000 Ethernet
SFP transceiver connector
GTX ports with four SMA connectors
USB To UART
USB Host / Peripheral Ports
PCI Express x8 Edge Connector

Memory DDR3 SO-DIMM (512 MB)
BPI Linear Flash (32 MB) (Also available for configuration)
IIC EEPROM (8 Kb)

Clocking 200 MHz Oscillator
66 MHz Socketed Oscillator
SMA Connectors for external clock
GTX Reference Clock port with 2 SMA connectors

Input / Output and
Expansion Ports
16x2 LCD character display
DVI Output
User Push buttons (5), DIP switches (3), LEDs (13)
User GPIO
Two FMC Expansion Ports

Power 12V wall adapter or ATX
Voltage and Current measurement capability of 2.5V , 1.5V, and 1.2
V, 1.0 V supplies

Enclosure to T.E. No. NPOL/14SOT282/LP, Dated- 07th January 2014
ANNEXURE-II
Page 10 of 11


4DSP FMC150 High-Speed ADC/DAC FMC Module

Texas Instruments ADS62P49 dual 14-bit, 250 MSPS Analog to Digital converter (ADC)
Texas Instruments DAC3283 dual 16-bit, 800 MSPS Digital to Analog converter (DAC)
Texas Instruments CDCE72010 clock synchronizer / jitter cleaner
External clock input option Analog IO
50 Ohm, transformer-coupled External trigger input

List of Deliverables Xilinx ML605 Virtex-6 LX240T board
12 V power supply
USB programming cable, Ethernet cable
DVI-VGA adapter
4DSP FMC150 High-Speed ADC/DAC FMC Module
2 MMCX RF coax cables
One license voucher for ISE Design Suite: System Edition license
(device-locked to Xilinx Virtex-6 LX240T FPGA)
MathWorks Simulink evaluation tools
DUC/DDC reference design tutorials
Kit documentation









(DETAILED TECHNICAL SPECIFICATIONS Contd.) AVNET VIRTEX-6 FPGA DSP KIT WITHAD/DA OR EQUIVALENT
Enclosure to T.E. No. NPOL/14SOT282/LP, Dated- 07th January 2014
ANNEXURE-II
Page 11 of 11

DETAILED TECHNICAL SPECIFICATIONS
Description ITEM NO. 6 ETTUS RESEARCH USRP B210 BUS SERIES OR EQUIVALENT COMPLIANCE WITH
GIVEN SPECIFICATION
SPECIFY
DEVIATION IF ANY
Frequency Coverage Fully integrated, two-channel device with continuous RF coverage from 70 MHz 6GHz
Channels Full duplex, MIMO (2x2) operation with up to 56 MHz of real-time bandwidth (61.44MS/s
quadrature)

Connectivity Super Speed USB 3.0 connectivity (USB cables (02 nos) to be provided along with the unit)
Synchronization 2 nos External GPS Disciplined Clock unit (GPS-DO) must be provided along with the unit.
FPGA Open and reconfigurable Spartan 6 XC6SLX150 FPGA
RF IC AD9361 RFIC from Analog Devices
Software Development GNU Radio, C, and Python Compatible. With SDR Environment and Loop back Kit

Front End
Specifications


Power Supply Includes DC 6V power supply
Mechanical
Specifications



Enclosure to T.E. No. NPOL/14SOT282/LP, Dated- 07th January 2014
ANNEUXRE-II