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Frequently Asked Microprocessors Interview Questions and Answers

1)What is microprocessor?
It is a program controlled semi conductor device I!)" which #etches" decodes and e$ecute
instructions%

&)What are the 'asic units o# microprocessor?
(he 'asic units or 'locks o# microprocessor are A)*" an array o# registers and control unit%

+)What is a 'us?
,us is a group o# conducting lines that carries data" address and controlsignals%

-)Why data 'us is 'i.directional?
(he microprocessor is to #etch read) the data #rom memory or input device #or processing
and a#ter processing it has to store write) the data to memory or output devices% /ence the
data 'us is 'i.directional%

0)Why is Address 'us unidirectional ?
(he address is an identi#ication num'er used 'y the microprocessor to identi#y or access a
memory location or input1output device% It is an output signal #rom the processor% /ence the
address 'us is unidirectional%

2)3e#ine machine cycle?
Machine cycle is de#ined as the time required to complete one operation o# accessing
memory input1output" or acknowledging an e$ternal request% (his cycle may consists o# three
to si$ (.states%

4)3e#ine (.state?
(.state is de#ined as one su'division o# operation per#ormed in one clock period% (hese
su'divisions are internal states synchroni5ed with the system clock" and each (.state is
precisely equal to one clock period%

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6)What is an instruction cycle?
(he sequence o# operations that a processor has to carry out while e$ecuting the instruction
is called instruction cycle% 7ach instruction cycle o# processor contains a num'er o# machine
cycles%


8) What is #etch and e$ecute cycle?
(he instruction cycle is divided in to #etch and e$ecute cycles% (he #etch cycle is e$ecuted to
#etch the opcode #rom memory% (he e$ecute cycle is e$ecuted to decode the instruction and
to per#orm the work instructed 'y the instruction%

19) )ist the #lags o# 6960?
(here are #ive #lags in 6960%(hey are sign #lag" 5ero #lag" au$iliary carry #lag" parity #lag and
carry #lag%

11)What does memory.mapping mean?
(he memory mapping is the process o# inter#acing memories to microprocessor and
allocating addresses to each memory locations%

1&)What is opcode #etch cycle?
(he opcode #etch cycle is a machine cycle e$ecuted to #etch the opcode o# an instruction
stored in memory% 7ach instruction starts with opcode #etch machine cycle%

1+) What are the instructions used to control the interrupts?
7I
3I
:IM
;IM

1-) What is polling?
In polling" the microprocessor<s so#tware simply checks each o# the I1= devices every so
o#ten% 3uring this check" the microprocessor tests to see i# any device needs servicing%

10)What are the di##erent types o# interrupts?
/ardware
;o#tware
/ardware interrupts. (he interrupts where the !>* pins are used to receive interrupt requests
" are called hardware interrupts%
;o#tware interrupts ? (his interrupt is caused 'y the e$ecution o# the instruction% (hese are
special instructions supported 'ythe microprocessor%

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12)What are the types o# hardware interrupts?
(:A>
:;( 4%0
:;( 2%0
:;( 0%0
I@(:

14)3i##erence 'etween memory mapped I1o and I1= mapped I1o?

Memory mapped I1= I1= mapped I1=
1% In this device address is 12. 'it% 1% In this device address is 6.'it%


&% M7M: and M7MW control signals
are used to control read and write I1=
operations%
&% I=: and I=W control signals are used
to control read and write I1= operations%

+% Instructions availa'le are
)3A";(A"M=A :"M " A33 M etc

+% Instructions availa'le are I@ and =*(%

-% 3ata trans#er is 'etween any register
and I1= device%

-% 3ata trans#er is 'etween accumulator
and I1= device%

0% 3ecoding 12.'it address may require
more hardware%

0% 3ecoding 6.'it address will require
less hardware%


16)3escri'e the #unction o# the #ollowing pins in 6960?
a) :7A3B ') A)7 c) I=1M d) /=)3 e);I3 and ;=3
:7A3B ? It is used 'y the microprocessor to sense whether a peripheral is ready or not #or
data trans#er% I# not" the processor waits% It is thus used to synchroni5e slower peripherals to
the microprocessor%
A)7 ? In 6960 " A3o to A34 lines are multiple$ed and lower hal# o# address Ao to A4)
is availa'le only during (1 o# the machine cycle% (he latching o# lower hal# address #rom
themultiple$ed address lines 'yusing A)7 signal%
I=1M . indicates whether I1= operation or memory operation is 'eing carried out% /=)3 ?
(his signal indicates that another master is requesting #or the use o# address 'us" data
'us and control 'us%
;I3;erial Input 3ata) ? (his input signal is used to accept serial data 'it 'y 'it #rom
the e$ternal device%

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;=3;erial =utput 3ata) ? (his is an output signal which ena'les the transmission o# serial
data 'it 'y'it to the e$ternal device%

18)!omparison 'etween #ull address decoding and partial address decoding?

Full Address 3ecoding >artial Address decoding
1% All higher address lines are decoded to
select the memory or I1= device%
1% Few higher address lines are decoded
to select the memory or I1= device%

&% More hardware is required to design
decoding logic%

&% /ardware required to design decoding
logic is less and sometimes it can 'e
eliminated%

+% /igher cost #or decoding circuit%

+% )ess cost #or decoding circuit%

-% @o Multiple addresses%

-% It has a advantage o# multiple
addresses%

0% *sed in large systems

0% *sed in small systems


&9)What is A)7?
(he A)7 Address latch ena'le) is a signal used to demultiple$ the address and data lines
using an e$ternal latch% It is used to ena'le the e$ternal latch%


&1)Where is the :7A3B signal used?
:7A3B is an input signal to the processor" used 'y the memory or input1output devices to
get e$tra time #or data trans#er or to introduce wait states in the 'us cycles%

&&)Cive some e$amples o# port devices used in 6960 microprocessor 'ased system?
(he various port devices used in 6960 are
6&1&"6100"6102"6&00"6+00"6400%

&+)What is the need #or timing diagram?
(he timing diagram provides in#ormation regarding the status o# various signals" when a
machine cycle is e$ecuted% (he knowledge o# timing diagram is essential #or system designer
to select matched peripheral devices like memories" latches" ports etc #rom a microprocessor
system%

&-)What operation is per#ormed during #irst (.state o# every machine cycle in 6960?
In 6960" during the #irst (.state o# every machine cycle the low 'yte address is latched into an
e$ternal latch using A)7 signal%

&0)What is interrupt acknowledge cycle?

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(he interrupt acknowledge cycle is a machine cycle e$ecuted 'y 6960 processor to get the
address o# the interrupt service routine in order to service the interrupt device%

&2)What is vectored and non.vectored interrupt?
When an interrupt is accepted" i# the processor control 'ranches to a speci#ic address de#ined
'y the manu#acturer then the interrupt is called vectored interrupt% In @on.vectored interrupt
there is no speci#ic address #or storing the interrupt service routine% /ence the interrupted
device should give the address o# the interrupt service routine%

&4))ist the so#tware and hardware interrupts o# 6960?
;o#tware interrupts D :;( 9":;( 1":;( &":;( +":;( -":;( 0":;( 2":;( 4
/ardware interrupts D (:A>":;( 4%0":;( 2%0":;( 0%0" I@(:%

&6) What is (:A>?
(he (:A> is a non.maska'le interrupt o# 6960% It is not disa'led 'y processor reset or a#ter
recognition o# interrupt%

&8)/ow clock signals are generated in 6960 and what is the #requency o# the internal clock?
(he 6960 has the clock generation circuit on the chip 'ut an e$ternal quart5 crystal or )!
circuit or :! circuit should 'e connected at the pins E1 andE&% (he ma$imum internal clock
#requency o# 6960 is +%9+M/5%

+9)3e#ine stack?
;tack is a sequence o# :AM memory locations de#ined 'y the programmer%


+1) What is program counter? /ow it is use#ul in program e$ecution?
(he program counter keeps track o# program e$ecution% (o e$ecute a program the starting
address o# the program is loaded in program counter% (he >! sends out an address to #etch a
'yte o# instruction #rom memory and increments its content automatically%

+&) 3e#ine opcode and operand?
=pcodeoperation code) is the part o# an instruction that identi#ies a speci#ic operation%
=perand is a part o# instruction that represents a value on which the instruction acts%

++)/ow the 6960 processor di##erentiates a memory access and I1= access?
(he memory access and I1= access is di##erentiated using I=1M signal% (he 6960 processor
asserts I=1M low #or memory operation and high #or I1= operations%

+-)When the 6960 processor checks #or an interrupt?
In the second (.state o# the last machine cycle o# every instruction" the 6960 processor
checks whether an interrupt request is made or not%

+0)Why inter#acing is needed #or I1= devices?

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Cenerally I1= devices are slow devices% (here#ore the speed o# I1= devices does not match
with the speed o# microprocessor% And so an inter#ace is provided 'etween system 'us and
I1= devices%

+2)What is interrupt I1=?
I# the I1= device initiate the data trans#er through interrupt then the I1= is called interrupt
driven I1=%

+4)What is a port?
(he port is a 'u##ered I1=" which is used to hold the data transmitted #rom the microprocessor
to I1= devices and vice versa%

+6)What is the need #or interrupt controller?
(he interrupt controller is employed to e$pand the interrupt inputs% It can handle the interrupt
request #rom various devices and allow one 'y one to the processor%

+8)What is synchronous data trans#er scheme?
For synchronous data trans#er scheme" the processor does not check the readiness o# the
device a#ter a command have 'een issued #or read1write operation% For this scheme the
processor will request the device to get ready and then read1write to the device immediately
a#ter the request%

-9)What is asynchronous data trans#er scheme?
In asynchronous data trans#er scheme" #irst the processor sends a request to the device #or
read1write operation% (hen the processor keeps on polling the status o# the device% =nce the
device is ready" the processor e$ecutes a data trans#er instruction to complete the process%

-1)What are the internal devices o# 6&00?
(he internal devices o# 6&00 are port.A" port.," port.!% (he ports can 'e programmed #or
either input or output #unction in di##erent operating modes%

-&)What is *;A:(?
(he device which can 'e programmed to per#orm ;ynchronous or Asynchronous serial
communication is called *;A:( *niversal ;ynchronous Asynchronous :eceiver
(ransmitter)% 7gD I@(7) 6&01

-+)What is scanning in key'oard and what is scan time?
(he process o# sending a 5ero to each row o# a key'oard matri$ and reading the columns #or
key actuation is called scanning% (he scan time is the time taken 'y the processor to scan all
the rows one 'y one starting #rom #irst row and coming 'ack to the #irst row again%

--)What is programma'le peripheral device?
I# the #unction per#ormed 'ythe peripheral device can 'e altered or changed 'ya program
instruction then the peripheral device is called programma'le device% It have control register%

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(he device can 'e programmed 'y sending control word in the prescri'ed #ormat to
the control register%

-0)What is 'aud rate?
(he 'aud rate is the rate at which the serial data are transmitted% ,aud rate is de#ined as (he
time #or a 'it cell)% In some systems one 'it cell has one data 'it" then the 'aud rate and
'its1sec are same%

-2)What are the tasks involved in key'oard inter#ace?
(he tasks involved in key'oard inter#acing are sensing a key actuation" 3e'ouncing the key
and generating key codes 3ecoding the key)% (hese tasks are per#ormed so#tware i# the
key'oard is inter#aced through ports and they are per#ormed 'y hardware i# the key'oard is
inter#aces through 6&48%

-4)/ow a key'oard matri$ is #ormed in key'oard inter#ace using 6&48?
(he return lines" :)9 to:)4 o# 6&48 are used to #orm the columns o# key'oard matri$% In
decoded scan lines ;)9 t9;)+ o# 6&48 are used to #orm the rows o# key'oard matri$% In
encoded scan mode" the output lines o# e$ternal decoder are used as rows o# key'oard matri$%

-6)What is C>I,?
C>I, is the Ceneral >urpose inter#ace ,us% It is used to inter#ace the test instruments to the
system controller%

-8)Advantages o# di##erential data trans#er?
!ommunication at high data rate in real world environment%
3i##erential data transmission o##ers superior per#ormance%
3i##erential signals can help induced noise signals%

09)What is di##erence 'etween Microprocessor and Microcontroller ?
Microprocessors generally require e$ternal components to
implement program memory" ram memory and Input1output%
IntelFs 6962" 6966" and 69+62 are e$amples o# microprocessors%

Micro controllers incorporate program memory" ram memory and
input1output resources internal to the chip% MicrochipFs pic
series and AtmelFs AA: series are e$amples o# micro controllers