Design Setup FPR CPF

UNICAD 24 / May 2008
CENTRAL R & D
Design Automation and Integrated Systems
CPF DESIGN SETUP
CPF DESIGN SETUP
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CPF Design SETUP
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page 1
TABLE OF CONTENTS
0.1 Design Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
0.1.1 seed.cpf reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
0.1.2 seed.tcl reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
0.1.3 seed.cpf example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
0.1.4 seed.tcl example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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0.1 Design Setup
Design setup needs to be performed by the user to specify the design and library information
required for the generation of setup files for all the tools used in the flow. For this purpose, two
files must be provided by the user in the SETUP directory:
A seed.cpf file in Cadence CPF format is used to define design name, power domains,
nominal conditions, power modes, operating corners and analysis-views, and power rules.
A seed.tcl file in Tcl format is used in addition to the seed.cpf format to define power
domain libraries and design global variables.
Examples of seed.cpf and seed.tcl are given at the end of this section.
0.1.1 seed.cpf reference
A seed.cpf file in Cadence CPF format is used for design setup. The purpose of this section is
to describe the CPF statements and extensions expected in the seed.cpf file, for design setup
(figure 1). Please refer to Cadence documentation for more information on CPF.
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Figure 1:CPF Terminology
0.1.1.1 Design Name
The CPF statement set_design is used to specify the current design name:
set_design <design>
Where:
<design> is the name of the current design name.
0.1.1.2 Power Domains
The CPF create_power_domain statement is used to specify the design power domains. At least
one default power domain must be defined.
create_power_domain [-default] -name <power domain>
Where:
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<power domain> is the name of the power domain to be specified.
-default specifies the default power domain. At least one default power
domain must be defined.
0.1.1.3 Nominal Conditions
The CPF create_nominal_condition statement is used to specify the nominal conditions at
which power domains can operate.
create_nominal_condition -name <condition> -voltage <float>
Where:
<condition> is the nominal condition to be specified.
<voltage> is the voltage of the nominal condition.
0.1.1.4 Power Modes
The CPF create_power_mode statement is used to specify the design modes. The concept of
design mode includes both power and timing modes. Additional properties can be attached to
design modes with the power_mode_properties Tcl variable.
create_power_mode -name <mode> -domain_conditions
{<domain1>@<condition1> ...}
set power_mode_properties(<mode>) {<name1> <value1> ...}
Where:
<mode> design mode to be specified.
<domain1>@<condition1> specifies that in mode <mode> the
condition for power domain <domain1> is <condition1>.
<name1> is the name of a property to be attached to the design
mode.
<value1> is the value of the property <name1>
0.1.1.5 Operating Corners
The CPF create_operating_corner statement is used to specify operating corners. Additional
properties can be attached to operating corners with the operating_corner_properties Tcl
variable.
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create_operating_corner -name <corner> -process <float> -voltage
<float> -temperature <int> -librarySet <library set>
set operating_corner_properties(corner) {rc <rccorner> [mode
<mode>] [voltage2(<library>) <voltage2>] ...}
Where:
<corner> is the operating corner to be specified.
-process, -voltage, -temperature are mandatory options to specify
operating corner process, voltage and temperature.
<library set> is the name of a library set. Actual library paths are computed
during script generation, according to design library definitions in seed.tcl
and library packaging/vc.bbview files. In consequence, library sets MUST
NOT be defined in the seed.cpf.
<rccorner> is a mandatory parasitics corner to be attached to the operating
corner. Allowed values are RCMIN, RCMAX, RCTYP.
<mode> is an optional mode to be attached to the operating corner. Allowed
values are modes defined with create_power_mode.
<library> name of a library with 2 voltages
<voltage2> value of the second voltage for library <library>
0.1.1.6 Analysis Views
The CPF create_analysis_view statement is used to specify analysis views. Analysis views are
used to generate different CAD tool execution runs, refered to as tasks.
create_analysis_view -name <view> -mode <mode>\
-domain_corners {<domain>@<corner>}
Where:
<view> is the name of the analysis view to be specified.
<mode> is the design mode corresponding to the analysis view.
<domain>@<corner> tells that in analysis view <name> the operating
corner to be used for power domain <domain> is <corner>
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The analysis_view_scenarios Tcl variable is used to specify the category of task to be
performed foreach analysis views.
set analysis_view_scenarios(<category>) {<view1> ... <viewn>}
Where:
<category> is the name of the category of tasks to be generated. Allowed
values task categories names are.
<view1>,... <viewn> are the analysis views used for the generation of tasks
in the category <category>.
The analysis_view_properties Tcl variable is used to specify mapping of analysis views
between different categories.
The following statement defines the analysis view <xtview> of category EXTRACTION, to be
used in the analysis view <dcview> of category DELAY_CALCULATION.
set analysis_view_properies(<dcview>) {parasitics <xtview>}
The following statement defines the analysis view <dcview> of category
DELAY_CALCULATION, to be used in the analysis view <taview> of category
TIMING_ANALYSIS.
set analysis_view_properies(<xtview>) {delays <dcview>}
Analysis View Categories
IMPLEMENTATION
EXTRACTION
DELAY_CALCULATION
TIMING_ANALYSIS
POWER_ANALYSIS
STATIC_IRDROP_ANALYSIS
DYNAMIC_IRDROP_ANALYSIS
RAMPUP_ANALYSIS
Table 1: Analysis View Category names
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0.1.2 seed.tcl reference
In addition to the seed.cpf, a seed.tcl in Tcl format is used to define power domain libraries and
design global variables.
The following tables describe the use of all the variables that can be found inside the seed.tcl
file:
Design Structure Description:
Variable name Value
G_DESIGNS Current design name.
G_DESIGN_TYPE Defines the type of the current design. top or
block.
G_TECHNO Technology name, in lower case
G_LIBRARIES List of library names used by the designs.
G_PHYSICAL_LIBRARIES List of additional libraries to be used for assem-
bly of the complete layout.
G_BUMP_LIBRARIES List of bump libraries, for flip-chip designs.
G_BLOCK_REFERENCE_LIBRA
RIES(<block>)
Obsolete
G_POWER_DOMAIN_LIBRARIE
S(<domain>)
List of libraries used in power domain <domain>.
G_BLOCKINSTANCE(<path>) This variable is used to describe the design hier-
archy. The hierarchy is described by an array
whose index contains the sub-block instance path
and whose value contains the sub-block master
name.
Table 2: Design structure related variables
Variable name Value
G_FLIP_CHIP Specifies a flip-chip design.
G_MULTISUPPLY Specifies a multisupply design.
Table 3: Design features related variables
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G_MULTISUPPLY_GROUP Non switchable group name. This group must be
specified in the power ATTX with a given area.
Variable name Value
G_OPCOND_LIBRARY Library name to be used as reference for operating
condition definitions.
G_OPCOND_NAME(<opcond>) Obsolete
G_LIBRARY_OPCOND_NAME(<
library>:<library set>)
This variable can be used when an operating condi-
tion is not available in library <library> How-
ever, it must not be used for final chip sign-off,
where all library operating conditions must be
available. The index <library set> is the name of
a library set. Allowed values are the operating
condition keys which can be found in library pack-
aging/vc.bbview files (typically <process>_<volt-
age>V_<temperature>)
G_PRIMETIME_USE_FULL_OP
COND_NAME
This variable is transparently set by the techno
kit. It is true when the operating condition
defined in the libraries is of the form
wc_1.10V_125C instead of Worst.
Table 4: Operating condition related variables
Variable name Value
G_MODES Obsolete
G_OPCOND_MODES(<opcond>
)
Obsolete
G_BLOCK_DESIGN_MODE_MAP
(<cell>)
Specifies the mapping between the top design mode
and the block design mode.
Table 5: Mode Related Variables
Variable name Value
Table 3: Design features related variables
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Implementation Flow Variables
Variable name Value
G_NBTI_EXTENSION Specify the NBTI extension to be used for librar-
ies and blocks. Allowed values are _10y, _1ey,
_2ey,... The default value is set by the technol-
ogy kit.
G_NBTI_MISSING_LIBRARIE
S
Specifies the libraries for which NBTI data is
not available for implementation (only for tech-
nologies that use NBTI).
G_NBTI_MISSING_LIBRARY_
OPCOND_NAMES(<library>)
This variable can be used when a NBTI operating
condition is not available in library <library>
However, it must not be used for final chip sign-
off, where all library NBTI operating conditions
must be available. Allowed values are the non
NBTI operating condition keys, corresponding to
the missing NBTI operating conditions, which can
be found in library packaging/vc.bbview files
(typically <process>_<voltage>V_<temperature>)
G_NBTI_MISSING_LIBRARY_
SETS
Lists the names of library sets for which no NBTI
views are expected.
G_BLOCK_NONBTI Specifies a list of block masters for which NBTI
data is not available.
Table 6: NBTI Related Variables
Variable name Value
G_IMPLEMENTATION_MODE Defines the mode in which the implementation is
going to be performed.
G_IMPLEMENTATION_NBTI Specifies whether the design should be imple-
mented using NBTI or not. For RtlKit, AvantiKit
and SignOffKit, this variable is automaticaly set
to the correct value depending on technology By
default this variable is set to the value of
G_NBTI.
Table 7: Global implementation variable
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G_IMPLEMENTATION_NBTI_M
ISSING_LIBRARIES
Specifies the libraries for which NBTI data is
not used for implementation (only for technolo-
gies that use NBTI). By default this variable is
set to the value of G_MISSING_LIBRARIES.
G_IMPLEMENTATION_OPCOND
_MODES(<opcond>)
List of modes to be performed for the operating
condition <opcond>, where <opcond> defined with
the G_OPCOND_NAME(<opcond>) variable. By default
this variable is set to the value of the
G_OPCOND_MODES(<opcond>) variable.
G_BLOCK_PR_MODE(<cell>) In top-down flow, blocks are located along with
design data. This variable should be set to
budget. In bottom-up flow, blocks are along
with libraries. This variable should be set to
library.
G_PSYN_HIGHSPEED_LIBRAR
IES
Specifies the high speed libraries for mix HS/LL
flow
Variable name Value
G_NETLISTOPT_DO_COMPILE Determines if incremental compile is done.
G_NETLISTOPT_TEST_READY Determines scan ready FFs are to be preserved.
G_NETLISTOPT_TEST_INSER
TION
Enables basic test insertion.
G_NETLISTOPT_XDBIST_INS
ERTION
Enables XdBist insertion in a gate 2 gate synthe-
sis flow.
G_PRECTS_FIX_HOLD Enables the synthesis flow to fix hold violations
before Clock Tree Synthesis.
G_CTEDIT_GTECH Enables the CTEdit flow (Clock Tree + High Fanout
Net management at GTECH level).
G_SYNTHESIS_USE_ACS Enables the parallel compilation with Automated
Chip Synthesis (Bottom-up synthesis), instead of
Top-Down synthesis.
G_SYNTHESIS_USE_SVF Enables the SVF flow (Design Compiler creates
information files that help Formality prove the
synthesis).
Table 8: Variable specific to SYNTHESIS tasks
Variable name Value
Table 7: Global implementation variable
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G_SYNTHESIS_DO_REFINE Determines if a refinement pass is to be done for
optimization
G_SYNTHESIS_TEST_READY Enables the use of flip-flops with dedicated scan
connected together (compile -scan).
G_SYNTHESIS_TEST_INSERT
ION
Enables basic test insertion.
G_SYNTHESIS_CLOCK_GATE Enables the automated clock gating insertion with
Power Compiler.
G_SYNTHESIS_USE_XG Enables the use of XG mode in Design Compiler.
Available in v.2003.12+.
G_SYNTHESIS_USE_LSF Enables the use of LSF for ACS compilation of par-
titions.
G_SYNTHESIS_LSF_COMMAND (optional) Specifies the default LSF command for
ACS (G_SYNTHESIS_USE_LSF must be set to true).
G_SYNTHESIS_LSF_COMMAND
_LARGE
(optional) Specifies the LSF command to use for
large partitions (G_SYNTHESIS_USE_LSF must be set
to true).
Variable name Value
G_DEFAULT_DRIVE_LIB library that contains the driving cells to make
the default budget. It is mandatory to use a
drive lib to enable the use of the xb template
latter on.
G_DEFAULT_DRIVE this is the default driving cell to use for all
outputs or inouts of the sub-blocks.
G_DEFAULT_MAX_LOAD this is the default expected maximum loading for
the drive cell specified with G_DEFAULT_DRIVE
G_DEFAULT_PORT_LOAD this is the default port load for all ports of the
sub-block.
G_DEFAULT_DRIVE_INPUT_T
RANSITION
this value is used by the .lib generator to
extract from the driving cell specified a table
that depends only on loading.
Table 9: Variable specific to BUDGETING tasks
Variable name Value
Table 8: Variable specific to SYNTHESIS tasks
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SignOff Flow Variables:
Variable name Value

G_ICPACK_CLASS class of pads to be used for IO libraries.
G_ICPACK_VERSION(<libra
ry>)
IO libraries versions. This variables also defines
the list of IO libraries.
Table 10: Variable specific to ICPACK tasks
Variable name Value
G_SIMPLE_FLOW Specifies a reduced set of netlist checks, for a
implementation flow able to keep all verilog
names.
Table 11: Variable specific to CHECKS tasks
Variable name Value
G_EXTRACTION_TOOL Specifies the extraction tool to be used: starrcxt
or arcadia. Default is computed from the technol-
ogy name.
G_EXTRACTION_MODE Specifies the extraction mode: best_worst or
typic. Default is best_worst.
Table 12: Variable specific to EXTRACTION tasks
Variable name Value
G_HOST_ARCH Defines the host architecture, for script genera-
tion. This variable is used by the VERIFICATION
variable, for calibre invocation.Default value is
64.
G_PR_FLOW Defines the implementation flow being used. This
variable is used by the VERIFICATION task, for cdl
netlist generation.
G_NETLIST2CDL_READ_DEF Let netlist2cdl read the routed def and to include
the physical cells into the output cdl.
Table 13: Variable specific to VERIFICATION tasks
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G_SIGNOFF_DRC_CALIBRE_O
PTIONS
Specifies options for drc calibre
G_SIGNOFF_LVS_CALIBRE_O
PTIONS
Specifies options for lvs calibre
G_POWER_AUTO_CONNECT When true (the default for 90nm and previous tech-
nologies), netlist2cdl will automatically con-
nect power ports with same name eventhough they
are not defined in the power.attx. When false (the
default for 65nm and bellow), netlist2cdl will
connect power port only if they are defined in the
power.attx. All remaining ports will be left
unconnected.
Variable name Value
G_PAD_OPENING_LAYER Normally automatically set by SignOffTechnoKit.
Available to override in case it is needed for a
workaround. Defines the layer:datatype to use to
identify pad openings.
G_PROBE_TEXT_LAYER Normally automatically set by SignOffTechnoKit.
Available to override in case it is needed for a
workaround. Defines the layer:datatype to use to
identify so called probe text which defines
where to place probes inside the pad opening.
Table 14: Variable specific to EWS tasks
Variable name Value
G_BLOCK_TA_MODE(<cell>) Describes how a hierarchical cell is to be used in
PrimeTime flow. In spef mode, the verilog and
spef are loaded flat this mode is required for
SignOff. Other modes are dspf, etm, ilm,
"budget".
Table 15: Variables specific to DELAY_CALC and TIMING_ANALYSIS tasks
Variable name Value
Table 13: Variable specific to VERIFICATION tasks
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G_DELAY_CALC_MAX_CAP Max capacitance to be checked during DELAY_CALC.
Typically, this variable is used to take an addi-
tional margin to the checks specified in librar-
ies, in consequence, the value specified should be
lower than the values specified in libraries. When
this variable is set to the value XXX, the
set_max_capacitance command is commented in the
DELAY_CALC.OPCOND.pt scripts, and the default
max_capacitance of each cell is used.
G_DELAY_CALC_MAX_TRAN Max transition to be checked during DELAY_CALC.
Typically, this variable is used to take an addi-
tional margin to the checks specified in librar-
ies, in consequence, the value specified should be
lower than the values specified in libraries. When
this variable is set to the value XXX, the
set_max_transition command is commented in the
DELAY_CALC.OPCOND.pt scripts, and the default
max_transition of the library is used.
G_DELAY_CALC_LIBRARY_ST
AMP_MODELS(<library>)
Specifies the library STAMP models to be used for
each library during DELAY_CALC. This variable is
an array whose index contains the library name and
value contains the list of stamp names.
G_DELAY_CALC_ANNOTATE_S
IMULATOR
Simulator to be used to check SDF annotation.
Allowed values are verilogxl, ncverilog, modelsim
and vcs. Default simulator is ncverilog.
G_DELAY_CALC_CHECK_CLOC
K_DRC
Enables the sourcing of the clock drc script gen-
erated by ctEdit, during delay-calculation.
G_PRIMETIME_TIMING_EXCE
PTIONS
Enables the management of exceptions as a separate
PrimeTime constraint file. Must be true.
G_DELAY_CALC_CHECK_CLOC
K_DRC
Specifies that primetime should check and export
clocks transition in DELAY_CALC or dspf mode
TIMING_ANALYSIS.
G_TA_REPORT_LEVEL none, short, medium or full, default is full.
Defines the verbosity of reports in DELAY_CALC and
TIMING_ANALYSIS tasks. See task description for
full details.
Variable name Value
Table 15: Variables specific to DELAY_CALC and TIMING_ANALYSIS tasks
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Variable name Value

G_TA_REPORT_TIMING Enable the generation of a full range of
report_timing commands in timing analysis if true.
Useful for debugging, but costly in run-time. If
not set, default value is true.
G_TA_REPORT_CLOCK_TIMIN
G
Enables the generation of report_clock_timing
script to analyse the clock trees of the design if
true. If not set, default value is false.
G_TA_QUIT If false, no quit will be present at the end of
the timing analysis primetime shell scripts. If
not set, default value is true.
G_TA_SAVE_SESSION When set to true, the primetime session is saved
before exiting. The session can then be restored
using restore_session command.
G_TA_CRPR_MODES Obsolete
G_CRPR_HOLD_ONLY Specify if CRPR is performed only for hold. A
default value is specified in the techno kit.
G_CRPR_DERATE Clock delay derating factor for the CRPR timing
analysis flow. Used in sign-off timing analysis
when CRPR flow is activated.
G_HOLD_UNCERTAINTY Minimum hold uncertainty for the CRPR timing anal-
ysis flow. Used in sign-off timing analysis when
CRPR flow is activated.Default is 20ps.
G_TA_MAX_FIX_CELL Maximum number of cells to be fixed when generat-
ing the fix hold report for the CRPR timing anal-
ysis flow in worst mode. Used in sign-off timing
analysis when CRPR flow is activated
G_TA_FIX_HOLD_ARRAY(Wor
st)
Specifies the buffers to be used when generating
the fix hold report for the CRPR timing analysis
flow in worst corner. Used in sign-off timing
analysis when CRPR flow is activated.
G_TA_FIX_HOLD_ARRAY(Bes
t)
Specifies the buffers to be used when generating
the fix hold report for the CRPR timing analysis
flow in best corner. Used in sign-off timing anal-
ysis when CRPR flow is activated.
Table 16: Variables specific to TIMING_ANALYSIS task
Central R&D - DAIS
CPF Design SETUP
May 2008
page 17
0.1.3 seed.cpf example
An example of seed.cpf is as follows:
set_design <design name>
create_power_domain -default -name TOP
create_nominal_condition -name 1.10V -voltage 1.10
create_power_mode -name functional -domain_conditions {TOP@1.10V}
create_power_mode -name test -domain_conditions {TOP@1.10V}
#####################
# operating corners #
#####################
Variable name Value
G_POWER_OPCONDS Obsolete.
G_POWER_ANALYSIS_PIPE_M
ODE
Set to true if the output of the simulator is
piped directly in PrimePower. Set to false if a
.vcd.gz is read.
G_POWER_VCD_STRIP_PATH(
<mode>)
G_POWER_VCD_STRIP_PATH
G_POWER_VCD_STRIP_PATH specifies the path of the
design in the vcd simulation file.
In case this path is mode dependent, the
G_POWER_VCD_STRIP_PATH(<mode>) must be used.
These two syntaxes are exclusive.
Table 17: Variables specific to POWER_ANALYSIS
Variable name Value
G_PACKAGE_LIBRARY_NAME Library name of the package. Set to the design
name by default
Table 18: Variable specific to PACKAGING , TIMING_ETM_MODEL and TIMING_FALT_MODEL
tasks
Central R&D - DAIS
CPF Design SETUP
May 2008
page 18
create_operating_corner -name nom_1.10V_25C_RCTYP -process 1.0 -voltage 1.10 -
temperature 25 -library_set Nom
create_operating_corner -name bc_1.20V_m40C_RCMIN -process 0.8 -voltage 1.20 -
temperature -40 -library_set Best
create_operating_corner -name bc_1.20V_m40C_RCMAX -process 0.8 -voltage 1.20 -
temperature -40 -library_set Best
create_operating_corner -name bc_1.20V_125C_RCMIN -process 0.8 -voltage 1.20 -
temperature 125 -library_set bc_1.20V_125C
create_operating_corner -name bc_1.20V_125C_RCMAX -process 0.8 -voltage 1.20 -
temperature 125 -library_set bc_1.20V_125C
create_operating_corner -name wc_1.05V_125C_RCMIN -process 1.2 -voltage 1.05 -
temperature 125 -library_set Worst
create_operating_corner -name wc_1.05V_125C_RCMAX -process 1.2 -voltage 1.05 -
temperature 125 -library_set Worst
create_operating_corner -name wc_1.05V_m40C_RCMIN -process 1.2 -voltage 1.05 -
temperature -40 -library_set wc_1.05V_m40C
create_operating_corner -name wc_1.05V_m40C_RCMAX -process 1.2 -voltage 1.05 -
temperature -40 -library_set wc_1.05V_m40C
set operating_corner_properties(nom_1.10V_25C_RCTYP) {rc RCTYP}
set operating_corner_properties(bc_1.20V_m40C_RCMIN) {rc RCMIN}
set operating_corner_properties(bc_1.20V_m40C_RCMAX) {rc RCMAX}
set operating_corner_properties(bc_1.20V_125C_RCMIN) {rc RCMIN}
set operating_corner_properties(bc_1.20V_125C_RCMAX) {rc RCMAX}
set operating_corner_properties(wc_1.05V_125C_RCMIN) {rc RCMIN}
set operating_corner_properties(wc_1.05V_125C_RCMAX) {rc RCMAX}
set operating_corner_properties(wc_1.05V_m40C_RCMIN) {rc RCMIN}
set operating_corner_properties(wc_1.05V_m40C_RCMAX) {rc RCMAX}

###############
# Extractions #
###############
create_analysis_view -name Best -mode functional {
TOP@bc_1.20V_m40C_RCMIN
}
create_analysis_view -name Best_125C -mode functional {
TOP@bc_1.20V_125C_RCMIN
}
create_analysis_view -name Worst -mode functional {
TOP@wc_1.05V_125C_RCMAX
}
create_analysis_view -name Worst_m40C -mode functional {
TOP@wc_1.05V_m40C_RCMAX
Central R&D - DAIS
CPF Design SETUP
May 2008
page 19
}
create_analysis_view -name Nom -mode functional {
TOP@nom_1.10V_25C_RCTYP
}
#######################
# functional analysis #
#######################
create_analysis_view -name functional_Best -mode functional {
}
create_analysis_view -name functional_Best_RCMAX -mode functional {
TOP@bc_1.20V_m40C_RCMAX
}
create_analysis_view -name functional_bc_1.20V_125C -mode functional {
}
create_analysis_view -name functional_bc_1.20V_125C_RCMAX -mode functional {
TOP@bc_1.20V_125C_RCMAX
}
create_analysis_view -name functional_wc_1.05V_m40C_RCMIN -mode functional {
TOP@wc_1.05V_m40C_RCMIN
}
create_analysis_view -name functional_wc_1.05V_m40C -mode functional {
}
create_analysis_view -name functional_Worst_RCMIN -mode functional {
TOP@wc_1.05V_125C_RCMIN
}
create_analysis_view -name functional_Worst -mode functional {
}
set analysis_view_properties(Best) {parasitics Best}
set analysis_view_properties(Best_RCMAX) {parasitics Best}
set analysis_view_properties(bc_1.20V_125C) {parasitics Best_125C}
set analysis_view_properties(bc_1.20V_125C_RCMAX) {parasitics Best_125C}
set analysis_view_properties(wc_1.05V_m40C_RCMIN) {parasitics Worst_m40C}
set analysis_view_properties(wc_1.05V_m40C) {parasitics Worst_m40C}
set analysis_view_properties(Worst_RCMIN) {parasitics Worst}
set analysis_view_properties(Worst) {parasitics Worst}
Central R&D - DAIS
CPF Design SETUP
May 2008
page 20
#################
# test analysis #
#################
create_analysis_view -name test_Best -mode test {
}
create_analysis_view -name test_Best_RCMAX -mode test {
TOP@bc_1.20V_m40C_RCMAX
}
create_analysis_view -name test_bc_1.20V_125C -mode test {
}
create_analysis_view -name test_bc_1.20V_125C_RCMAX -mode test {
TOP@bc_1.20V_125C_RCMAX
}
create_analysis_view -name test_wc_1.05V_m40C_RCMIN -mode test {
TOP@wc_1.05V_m40C_RCMIN
}
create_analysis_view -name test_wc_1.05V_m40C -mode test {
}
create_analysis_view -name test_Worst_RCMIN -mode test {
TOP@wc_1.05V_125C_RCMIN
}
create_analysis_view -name test_Worst -mode test {
}
set xtscenarios {
Best
Best_125C
Worst
Worst_m40C
Nom
}
set tascenarios {
functional_Best
functional_Best_RCMAX
functional_Worst_RCMIN
Central R&D - DAIS
CPF Design SETUP
May 2008
page 21
functional_Worst
test_Best
test_Best_RCMAX
test_Worst_RCMIN
test_Worst
functional_bc_1.20V_125C
functional_bc_1.20V_125C_RCMAX
functional_wc_1.05V_m40C_RCMIN
functional_wc_1.05V_m40C
test_bc_1.20V_125C
test_bc_1.20V_125C_RCMAX
test_wc_1.05V_m40C_RCMIN
test_wc_1.05V_m40C
}
set analysis_view_scenarios(IMPLEMENTATION) $tascenarios
set analysis_view_scenarios(EXTRACTION) $xtscenarios
set analysis_view_scenarios(DELAY_CALCULATION) $tascenarios
set analysis_view_scenarios(TIMING_ANALYSIS) $tascenarios
set analysis_view_scenarios(POWER_ANALYSIS) $tascenarios
set analysis_view_scenarios(STATIC_IRDROP_ANALYSIS) $tascenarios
set analysis_view_scenarios(DYNAMIC_IRDROP_ANALYSIS) $tascenarios
set analysis_view_scenarios(RAMPUP_ANALYSIS) $tascenarios
0.1.4 seed.tcl example
An example of seed.tcl file is as follows:
#============================================================================
# DEFINE DESIGN NAME, DESIGN RULE CHECKS
#============================================================================
set G_DESIGNS "<block 1> <block 2>"
set G_DESIGN_TYPE "top|block"
set G_TECHNO "cmos045lp_7m4x0y2z"
#============================================================================
# DEFINE LIBRARY AND HIERARCHICAL SUB-BLOCKS
#============================================================================
set G_LIBRARIES {<library 1> <library 2>}
Central R&D - DAIS
CPF Design SETUP
May 2008
page 22
# To specify specific libraries for block master
# set G_BLOCK_REFERENCE_LIBRARIES(<cell>) {<blockLibrary1> <blockLibrary2>}
# To specify the cell name and instance path of hierarchical
# sub-blocks, which are implemented separately. Please uncomment and
# duplicate the following statement as needed.
# set G_BLOCKINSTANCE(<instance path>) <cell>
# set G_BLOCK_PR_MODE(<cell>) {budget|library}
#============================================================================
# FLIP CHIP PARAMETERS
#============================================================================
# To generate Flip Chip tasks, set the following variable to true :
# Signoff RDL extraction (block or top) etc...
set G_FLIP_CHIP false
#============================================================================
# DEFINE DESIGN LIBRARY OPERATING_CONDITIONS
# define operating conditions persent in libraries
#============================================================================
set G_OPCOND_LIBRARY "<ref library>"
# set G_PHYSICAL_LIBRARIES {<library1> <library2> .....}
set G_NBTI_MISSING_LIBRARIES {}
set G_NBTI_MISSING_LIBRARY_SETS {bc_1.20V_125C}
#============================================================================
# Flow definition variables
#============================================================================
set G_HOST_ARCH 64
set G_SIMPLE_FLOW true
#============================================================================
# DELAY_CALC TASK PARAMETERS
#============================================================================
Central R&D - DAIS
CPF Design SETUP
May 2008
page 23
set G_DELAY_CALC_MAX_CAP "XXX"
set G_DELAY_CALC_MAX_TRAN "XXX"
# To use library STAMP models, the list of STAMP model names to be
# used for each library need to be specified. Please duplicate the
# following statement as needed.
set G_DELAY_CALC_LIBRARY_STAMP_MODELS(<libraryName>) {<model> <model2>}
# To Specify the timing model to be used for each hierarchical
# sub-block. Please uncomment and duplicate the following statement
# as needed. Allowed values are dspf, ilm, etm. Default value is
# dspf.
#set G_BLOCK_TA_MODE(<cell>) dspf
# in case the model has been generated only with fresh libraries
#set G_BLOCK_NONBTI { <list of cells> }
# Available simulators are ncverilog verilogxl modelsim
set G_DELAY_CALC_ANNOTATE_SIMULATOR {ncverilog}
#============================================================================
# TIMING ANALYSIS PARAMETERS
#============================================================================
set G_TA_NBTI_MISSING_LIBRARIES {}
set G_TA_CROSS_CORNERS true
set G_BLOCK_DESIGN_MODE_MAP(<cell>) {<tolevel mode> <block mode> ...}
set G_TA_QUIT true
set G_TA_SAVE_SESSION true
## G_TA_REPORT_LEVEL, G_TA_REPORT_TIMING, G_TA_REPORT_CLOCK_TIMING:
## these variables can be modified after script generation
## by modifying the variables.pt in DELAY_CALC or TIMING_ANALYSIS tasks
## G_TA_REPORT_TIMING possible values are none, short, medium, full
## MANDATORY for SIGNOFF: full
## DELAY_CALC: 4_case_analysis_log_file & 6_report_disable_timing only in full
Central R&D - DAIS
CPF Design SETUP
May 2008
page 24
## TIMING_ANALYSIS:
## none : minimum set of reports : report_constraints & check_timing
## short : add report_max_delay_violator & report_qor
## medium : add report_*_violator & report_clock, port, hierarhy, reference, cell
## full : add 4_case_analysis_log_file, 6_report_disable_timing,
## report_ignored_exceptions, analysis_coverage*, min_pulse_width
set G_TA_REPORT_LEVEL full
## G_TA_REPORT_TIMING possible values are true and false
## when true, timing/*.rpt reports are generated
set G_TA_REPORT_TIMING true
## G_TA_REPORT_CLOCK_TIMING possible values are true and false
## when true, report_clock_timing.rpt report is generated
set G_TA_REPORT_CLOCK_TIMING true
set G_CRPR_DERATE 0.1
set G_SETUP_UNCERTAINTY 0.1
set G_HOLD_UNCERTAINTY 0.02
set G_TA_MAX_FIX_CELL 7
# Variable available to customise defaults buffer list for hold fixing loop
#set G_TA_FIX_HOLD_ARRAY(Best) "<buffername> {<hold delay value> <setup delay value>}
EXAMPLE_BUF {0.1 0.15}"
#set G_TA_FIX_HOLD_ARRAY(Worst) "<buffername> {<hold delay value> <setup delay
value>} EXAMPLE_BUF {0.3 0.45}"
#============================================================================
# POWER ANALYSIS PARAMETERS
#============================================================================
set G_POWER_ANALYSIS_PIPE_MODE false
#set G_POWER_VCD_STRIP_PATH(<mode>) XXX/YYY
#============================================================================
# VERIFICATION PARAMETERS
#============================================================================
# Disk-space saving option to GZIP MASK GDSII, only if CALIBRE support it
# i.e. from CALIBRE 2002.9 (v9.1_9) on : To activate option, uncomment line.
#set G_CALIBRE_ZIP "true"

Design Setup FPR CPF

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