FPGA based Digital Pulse Width Modulator for

high power SMPS with Multiple Inductor

Grishma Bhawsar
#
! P "#swaran
$%
Department of Electronics and Communication Engineering,
SRM University Chennai,
#

b"grishm&'ahoo"com ! $
%
eswaranp(&gmail"com
Abstract Digital pulse width modulator is the critical
module in digital controller for high frequency SMPS.
This work focus on a new FPG !ased architecture for a
Digital pulse width modulator this architecture takes the
ad"antages of digital clock manager present in almost all
FPGs. The proposed architecture of DP#M allows the
switching pulses for multi switches !y using single fine
resolution !lock. The use of D$M increases resolution of
Digital Pulse #idth Modulator !y % !its. The design was
successfully simulated and "erified !y ModelSim
simulation tool with switching frequency of &M'( and )
phases.
Keywords: DP#M* D$M phase shift* FPG
implementation* F+, !lock.
I" I)*+,D-.*I,)
Digital controller is enabling technolog' for
controlling switching acti/ities of Switch Mode Power
Suppl' or D.0D. con/erter" Due to the numerous
ad/antages including ad/anced control strateg'! low
sensiti/it' to /ariations! simplicit' to use digital design
tools and re0programmabilit' to different tas1! digital
controller has become an attracti/e candidate for high0
performance switching mode power suppl' 2SMPS3 in
portable electronic applications" A sufficientl' high
resolution of the DPWM is critical for the stabilit' of
the output /oltage" .on/ersel'! a DPWM resolution
that is lower than an AD. resolution leads to limit
c'cling 456"
While DPWMs can be simpl' implemented using a
counter and a comparator! this design leads to
unreasonabl' high cloc1 demands for higher
resolutions" In order to implement a )0bit DPWM for a
switching fre7uenc' of fsw! a cloc1 fre7uenc' of
%)fsw is needed" For modern switching fre7uencies
e"g" M89! a :0bit counter0based DPWM would ha/e
to be cloc1ed at o/er G89 which can cause design
difficulties and increased power consumption"
*o o/ercome this problem different architectures
ha/e been proposed and implemented in I.s 4;<(6" A
common architecture is the use of an as'nchronous
dela' line in combination with a large multiple=er
2M->3" Both can be combined as a h'brid architecture
using a counter for the coarse and an additional short
dela' line for the fine resolution 4?6" *his architecture
suffers from the difficult' of matching the dela' times
with the counter period" All dela' times must be
identical and fit e=actl' between two counter time steps
in order to a/oid non0linear errors and non0monotonic
beha/iour" While most DPWM implementations target
application specific integratedcircuits 2ASI.s3!
practicing engineers e=tensi/el' utili9e field
programmable gate arra's 2FPGAs3 to protot'pe and
/alidate their designs" Modern high0current switched
mode power supplies use multiple inductors which are
dri/en in phases in order to split the inductor current
and to increase the control loop performance and
efficienc'" #ach phase re7uires its own DPWM dri/er
signal" *hese signals are generated b' a multi0phase
digital pulse width modulator 2MP0DPWM3! also
referred to as digital multiphase modulators 2MPM3"
Different architectures ha/e been proposed in the
literature which either re7uire the replication of timing
bloc1s for each phase 4?0:6 or share the fine resolution
bloc1 between the phases 4@6" Furthermore! some multi0
phase architecture onl' supports a single common dut'
c'cle for all phases" *his limits the controller
performance and onl' permits passi/e current sharing"
,ther architectures support independent dut' c'cles for
each phase" *his allows the update of the dut' c'cle
with a rate of P A fsw instead of fsw where P is the
number of phases and fsw is the switching fre7uenc'"
Also /ariances in the power suppl' inductors can be
compensated b' adBusting the dut' c'cle for
corresponding phases accordingl'"
II P+,P,S#D DPWM A+.8I*#.*-+#
In this paper a new FPGA0based architecture for
multi0phase digital pulse width modulators supporting
separate dut'0c'cles for each phase is proposed" It
allows the sharing of the fine resolution bloc1 across all
phases" *his architecture increases the DPWM
resolution b' two bits and re7uired four out of phase
cloc1s which are produced b' using dedicated digital
cloc1 manager present almost in all FPGAs"
Proceedings of National Conference on Advanced Computing and CommunicationNCACC11, April.1, !"11
Architecture contains a coarse resolution counter0
comparator DPWM stage with the bit width of
)counter"
*his uses the most significant bits 2MSBs3 of the
)total0bit wide dut' c'cle as input where )counter C
)total 0 %" *hese MSBs are compared against the
counter /alue" *he output pulse of this first stage is
dela'ed using the three phase0shifted cloc1s from the
D.M" *he two least significant bits 2DSBs3 of the dut'
c'cle are used to select one of these four pulses" *he
final pulse is generated b' a setEreset flip0flop 2S+0FF3
with the coarse pulse used as dominant set input and the
selected dela'ed pulse as negati/e reset input"
III M-D*IP8AS# DPWM
DPWM as shown in fig"% consist of following
bloc1s
A. Counter
A simple s'nchronous counter with )c bits which
counts up at e/er' positi/e cloc1 edge is implemented
using a )c bit wide register and an adder" An arra' of
)c bit adder subtract the phase difference of each phase
with common )c bit counter output
B. Comparator
*wo comparators arra's with the same bit width as the
counter are included" *he first produces a counter
match the signal which indicates if counter is greater or
e7ual to the )c MSBs of the dut' c'cle" *he second
comparator produces a counter full signal which
indicates if the counter is full! i"e" all0s! and will
o/errun to 9ero at the ne=t cloc1 edge" A counter 9ero
signal is generated b' dela'ing the counter full signal"
#ach comparator in the top arra' tests if the
corresponding phase /alue is all0ones" *his indicates
that the /alue will be 9ero after the ne=t cloc1 edge"
*heir output signals are named Fcounter fullG" Because
some parts of the DPWM need to be triggered when
an' of the phase /alues is all0ones! these signals are or0
ed together into a single signal nameFan' counter fullG"
C. nterface registers for duty cycle
*his is ensured b' the use of interface registers
which are onl' cloc1ed when the counter full signal is
high" *he two DSBs of the dut' c'cle which are used as
select signal of the M-> need to be dela'ed b' another
cloc1 edge to s'nchronise them with the coarse pulse
register" *he dut' c'cle interface shown in the lower
left corner of uses a single serial )c0bit wire to recei/e
all dut' c'cles" *he dut' c'cle of the ne=t phase must
be written on this wire and held until it is registered"
*he lower two DSBs are onl' needed b' the fine
resolution bloc1 for a few cloc1 c'cles directl' after
the' are registered" *herefore a single %0bit register can
be shared b' all phases which is controlled b' the Fan'
counter fullG signal" *his signal is also pro/ided to the
e=ternal bloc1 as handsha1e signal which indicates that
the current dut' c'cle was registered"
44
FigH Multi phase con/erter uses multi0phase pulse width
modulator
Ad#iparasa$t#i %ngineering College, &elmaruvat#ur
D. !ine Resolution Bloc"
*he proposed fine resolution bloc1 as shown in Fig" @
consist of four data flip0flops 2DFF3 and a 50to0 M->
which is controlled b' the two DSBs of the dut' c'cle"
Single fine resolution bloc1 allow to generate dut'
pulse for all phases" *he coarse pulse generated b' the
coarse DPWM is registered b' the DFFs at ?:A! (:A
and %I:A of the counter cloc1 2:A3 and is therefore
dela'ed b' E5! E% and @E5 of the cloc1 period!
respecti/el'"
All four resulting pulses are then fed to the M->!
the output of which is ta1en as the negati/e reset signal
for the final output setEreset FF" *he original coarse
pulse is used as the dominant set signal" *his sets the
final DPWM pulse high as long as the coarse pulse is
high" It is onl' reset to low after the selected dela'ed
pulse goes low" *his widens the pulse b' the
appropriate cloc1 period fraction"
E. #litch removal circuit $loc"
*o a/oid the setup and hold time /iolation a circuit
proposed for remo/ing the problem occurs due to
sudden transition of set signal called glitch shown in
fig"5
*his produces a stable registered cloc1 enable
signals" *he pulse registers are reset b' feeding the
registered /ersion of the corresponding Fcounter0e7ualG
signal to the reset effecti/el' s'nchronous to the :A
cloc1"
IJ" +#S-D* A)D DIS.-SSI,)
*he J8DD code used for proposed architecture for
/erifies the correct functional beha/iour of the circuit"
Fig"K shows the simulation result for the shifting cloc1
b' the phase difference of ?:!(:!%I: degree from
reference s'stem cloc1 used for the whole DPWM"
Fig"; shown abo/e e=plain that how the shifted cloc1
will be shift according to the input %0bit DSBs of the
dut' c'cle"
*he single phase DPWM results shown in fig"I and
fig"( e=plain the /ariation of width of dut' pulse called
on time of the dut' c'cle will /ar' for :::::: as
:L ,)0time and as a ::L ,)0time" In fig"I
shows the output of single phase DPWM for the input
dut' c'cle of :::: and fig"( shows the output for the
input :: bits and the on time for the input ::
of wa/eform shown in fig( should be greater than the
width for input :::: as e=plained abo/e"
45

Fig"@ Fine +esolution Bloc1
Fig"5 Proposed glitch free circuit
Fig"K Simulation of shifting cloc1


Fig"; Simulation wa/eform of F+B Simulation results of
single phase DPWM
Proceedings of National Conference on Advanced Computing and CommunicationNCACC11, April.1, !"11
J" .,).D-SI,)
Simulation results for single phase DPWM for two
different input shown in the fig"I and fig"( results
shown is the output for ; bit input dut' c'cle if we ta1e
:::::: as :L on time and as a ::L on time
then the /erified result is shown in figure for the
different input width of pulse is different" *his paper
the architecture is suitable for high resolution
application and architecture support the different dut'
c'cle for e/er' different phase"

+#F#+#).#S
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46