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Electrical and Electronics Engineering Department

EE 212-Semiconductor Devices and Modeling

Homework (not to be collected)

Due May 21, 2014

1. Fill in the boxes given in the figure.

2. Consider the following MOS capacitor Draw the energy band diagram (only on the

semiconductor side) and charge distribution (on the metal and semiconductor sides)

under the following conditions. Show Ei and EF on the energy band diagram and define

the sources of semiconductor side charge on the charge distribution diagram.

2

Condition Energy Band Diagram Charge Distribution

VG<0

VT >VG>0

(no inversion layer)

VG >VT

3

3. Draw the energy band diagram of a MOS capacitor on n-type substrate at the onset of strong

inversion under an applied bias of V. Include and label in your diagram the following:

Metal Fermi Level: E

FM

Semiconductor (Bulk) Fermi Level: E

FS

Intrinsic Level: E

i

E

C

and E

V

Surface Potential:

S

Provide all the other necessary labels.

The dashed lines below show the boundaries between metal-oxide and oxide-semiconductor.

Metal Oxide Semiconductor

4. The following figure shows the characteristics of an enhancement type MOSFET. Provide the

required information.

MOSFET Type (n or p-channel):

Threshold Voltage:

Transconductance Parameter:

4

5. Consider the following MOSFET. Assume that VD is small enough to operate the device

in the linear region.

a) Write the expression for the resistance (R) of the elemental volume (with length x) in

terms of x, electron mobility in the inversion layer (i), inversion charge per unit area (Q (x))

and the other necessary parameters.

b) Express the inversion layer charge per unit area at location x (Q(x)) in terms of oxide

permittivity(),oxide thickness(tox),channel potential (V(x)), VGS and other necessary

parameters.

c) Express the potential drop (V) on the channel elemental volume (with length x) in terms

of channel current (ID), tox , , V(x), VGS, i , x and the other necessary parameters.

d) Derive the expression for the drain current (ID) in terms of tox , , VDS=VD, VGS, i , x and the

other necessary parameters. You must use your result in part (c).

R=

R=

R=

V=

V(x)=V

D

=V

DS

at x=L

V(x)=V

S

=0 at x=0

Threshold voltage=V

T

Channel thickness (depth) at x=h(x)

R=

Q(x)=

5

6. Draw the internal structure of a p-channel enhancement type MOSFET operating in linear region on

the figure given below. Determine the range of the biasing voltage values (V

GS

and V

DS

) to operate the

transistor in linear region and fill in the boxes accordingly.

V

GS

V

DS

D

S

G

B

v(0)=

v

ox

(0)=

v(L)=

v

ox

(L)=

v(x)=Potential at

point x with respect

to source

v

ox

= Potential

across the oxide

layer

V

TP

0

a) The parameters of the transistor are: length of the channel (L), width of the channel (W), and the

capacitance per unit area (C

ox

). Express the average charge stored per unit length in the channel in terms

of the transistor parameters and biasing voltages. Clearly show each step of your derivation. (Hint:

Assume v(x) changes linearly across the channel and use its average value).

b) Express the average drift velocity of the holes in the channel in terms of

p

, transistor parameters and

biasing voltages. Clearly show each step of your derivation and use the hint given in part (a).

c) Express I

SD

in terms of transistor parameters and biasing voltages.

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