S e pt e mb e r 1 9 9 7

5-75

1997Actel Corporation



IEEE St andard 1149.1
( J TAG) in t he 3200DX Family

I n t r o duc t i o n

Due t o t he incr easing complexit y of cir cuit boar ds, t est ing
loaded boar ds is becoming pr ohibit ively expensive and mor e
difficult t o per for m. Boar d complexit y has r esult ed fr om t he
r apid development of sur face-mount t echnology and fr om t he
use of mult ilayer ed boar ds. Finer pin spacing and t he use of
double-sided boar ds also have cont r ibut ed t o t he incr eased
cost and difficult y of t r adit ional t est ing, which makes use of
met hods such as in-cir cuit t est ing by bed-of-nails and
funct ional t est ing. Alt hough funct ional t est ing can cope wit h
complex and dense boar ds, it is cost ly because differ ent
designs r equir e differ ent set s of t est pr ogr ams.
A new met hod of t est ing r educes t he cost and difficult y of
boar d-level t est ing. The new st andar d was pr oposed and
developed by t he J oint Test Act ion Gr oup ( J TAG) and lat er
adopt ed by IEEE as t he

IEEE Standard Test Access Port and
Boundary-Scan Architecture

also r efer r ed t o as

IEEE Std.
1149.1

or infor mally as

J TAG

.
The st andar d pr ovides a cost -effect ive met hod of boar d
t est ing t hr ough use of t he boundar y-scan t echnique.
Boundar y scan pr ovides t he means t o t est each component s
r equir ed per for mance, int er connect ions, and int er act ion. In
addit ion t o descr ibing boundar y scan, t he st andar d also
descr ibes t he design-for -t est feat ur e.

Ov e r v i e w

The Act el 3200DX family is fully compliant wit h t he IEEE
St andar d 1149.1. Figur e 1 shows t he major par t s t hat make up
t he J TAG t est logic cir cuit . The cir cuit pr ovides t he r equir ed
component s ( Test Access Por t ( TAP) cont r oller and
r egist er s) t o suppor t all t he mandat or y boundar y-scan
inst r uct ions ( EXTEST, SAMPLE/PRELOAD, BYPASS) and
t wo opt ional inst r uct ions ( HIGHZ and CLAMP) . The J TAG
t est logic cir cuit also suppor t s t wo pr ivat e inst r uct ions, USER
INSTRUCTION, and J PROBE.

J T AG Ac t i v a t i o n

The J TAG t est logic cir cuit is act ivat ed in t he Designer Ser ies
soft war e by select ing Opt ions/Set Die & Package. This br ings
up t he Device Select ion dialog box as shown in Figur e 2. Click
t he Rest r ict J TAG Pins check box and t hen click t he OK
but t on. Dur ing device pr ogr amming a special fuse called t he

J -Fuse

is pr ogr ammed, enabling t he J TAG t est logic cir cuit .
The J TAG t est logic cir cuit can also be act ivat ed when using
t he Act el Scr ipt language by adding t he command:
Set ( RESTRICTJ TAGPINS, YES) ;

T e s t Ac c e s s Po r t ( T AP)

Each t est logic funct ion is accessed t hr ough t he Test Access
Por t . Ther e ar e four pins associat ed wit h t he TAP, and t hey
ar e list ed in Table 1 wit h t heir cor r esponding descr ipt ions.
These pins ar e dedicat ed pins, which ar e used only wit h t he
t est logic. If J TAG is not enabled, t he TAP por t s ( TMS, TCK,
and TDI) ar e fr ee t o be used as a r egular I/O. The t est logic
has been designed t o be in t he r eset st at e upon
power -up.

Table 1

Test Access Port

Port Description

TCK
(Test Clock Input)
Dedicated test logic clock used serially to shift test instruction, test data, and control inputs on the
rising edge of the clock, and serially to shift the output data on the falling edge of the clock.
TMS
(Test Mode Select)
Serial input for the test logic control bits. Data is captured on the rising edge of the test logic clock.
This pin is equipped with a pull-up resistor to place the test logic in the Reset state when no input
is present.
TDI
(Test Data Input)
Serial input for instruction and test data. Data is captured on the rising edge of the test logic clock.
This pin is equipped with a pull-up resistor.
TDO
(Test Data Output)
Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive state
(high impedance) when data scanning is not in progress.
Application Note AC167

5-76

Figure 1

J TAG Block Diagram

Figure 2

DeviceSelection Dialog Box
TAP CONTROLLER
INSTRUCTION
DECODER
CONTROL LOGIC
INSTRUCTION
REGISTER
BYPASS
REGISTER
JFUS2
BOUNDARY SCAN REGISTER
CONTROL SIGNAL GENERATOR
FOR USER'S REGISTER
USRTDI
TDO
USER-DEFINED DATA REGISTER
JPROBE REGISTER
(SHARE WITH X1, Y1, X2, AND Y2
OF ACTEL'S LONG REGISTER)
OUTPUT
MUX
TMS
TCK
POWER-ON
RESET
TDI

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T AP C o n t r o l l e r

The TAP cont r oller is a 16-st at e st at e machine t hat per for ms
accor ding t o t he st at e diagr am shown in Figur e 3. The 1s and
0s shown adjacent t o t he st at e t r ansit ions r epr esent t he TMS
values t hat must be pr esent at t he t ime of a r ising edge at
TCK for a st at e t r ansit ion t o occur . In t he st at es t hat include
t he let t er s -IR, t he inst r uct ion r egist er oper at es; in t he st at es
t hat cont ain t he let t er s -DR, t he t est dat a r egist er oper at es
( bypass, boundar y-scan, and J PROBE r egist er s) .
The TAP cont r oller r eceives t wo cont r ol input s, TMS and
TCK, and gener at es cont r ol and clock signals for t he r est of
t he t est logic ar chit ect ur e, as illust r at ed in Figur e 4. The TAP
cont r oller s st at e changes based on t he value of TMS, and at
t he r ising edge of TCK or on power -up. Upon power -up, t he
TAP cont r oller ent er s t he Test -Logic Reset st at e. Since t he
TMS pin is equipped wit h a pull-up r esist or , t he TAP
cont r oller will r emain in or r et ur n t o t he Test -Logic-Reset
st at e when t her e is no input or when a logical 1 is on t he TMS
pin. To r eset t he cont r oller , TMS must be high for at least five
TCK cycles.

Note:

Thevalueshown adjacent to thestatetransitions in this figurerepresents thesignal present at TMS at thetimeof therising
edgeat TCK.

Figure 3

TAP Controller StateDiagram
Select-
DR-Scan
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Capture-DR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Capture-IR
Select-
IR-Scan
Update-IR Update-DR
0
0
0
0
1
0
1
1 1
1
0
1
Run-Test/
Idle
Test-Logic-
Reset
1
1
1
0
1
1 0 1 0
0
1
1 1
0
1
0
0 0
0
1
0

Figure 4

TAP Controller Block Diagram
CLKDR
UPDTDR
SELECT
ENABLE
BSEINB
CLKIR
UPDTIR
SHIFTIR
TMS
TCK
SHIFTDR
TAP
CONTROLLER

5-78

I n s t r uc t i o n R e g i s t e r

The inst r uct ion r egist er ( IR) consist s of t hr ee IR cells. Each
cell has a shift -r egist er st age and a lat ch st age ( Figur e 5) . On
t he Capt ur e-IR st at e, t he shift r egist er is loaded wit h bit s 001,
which ar e used for fault isolat ion of t he boar d-level ser ial t est
dat a pat h. The TDI-IR-TDO pat h is est ablished on t he Shift -IR
st at e. Dat a in t he shift r egist er is shift ed t owar d TDO, and
dat a in t he lat ch r emains t he same. The dat a in t he shift
r egist er s is lat ched out and becomes t he cur r ent inst r uct ion
on t he falling edge of t he TCK in t he Updat e-IR st at e. When
t he TAP cont r oller ent er s t he Test -Logic Reset st at e, bit s 111
ar e lat ched in IR, which cor r esponds t o t he BYPASS
inst r uct ion, and t he dat a in t he shift r egist er cell r et ain t heir
pr evious values. Table 2 shows t he summar y of t he oper at ion
of t he inst r uct ion r egist er .

Figure 5

Instruction Register Block Diagram

Table 2

Instruction Register Operation

Controller State Shift-Register Stage Latch Stage

Test-Logic-Reset Undened BYPASS Instruction
IR2 IR1 IRO = 1 1 1
Capture-IR 001 is loaded Retain previous state
Shift-IR Shift data toward TDO Retain previous state
Exit1-IR
Exit2-IR
Pause-IR
Retain previous state Retain previous state
Update-IR Retain previous state Latch data from the shift register
All other states Undened Retain previous state
Shift
Register
Latch
Shift
Register
Latch
Shift
Register
Latch
IR2 IR1 IR0
TDO
0 0 1
TDI
To The Instruction Register
Bits 001 are loaded into the shift register
on the Capture-IR state.

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I E E E S t a n da r d 1 1 4 9 . 1 ( J T AG) i n t h e 3 2 0 0 DX F a mi l y

I n s t r uc t i o n s

Table 3 list s t he suppor t ed inst r uct ions wit h t heir
cor r esponding IR codes and descr ipt ions.

B y pa s s R e g i s t e r

The bypass r egist er is a single-bit r egist er t hat pr ovides a
minimum dat a pat h bet ween t he TDI and TDO pins
( Figur e 6) . The bypass r egist er is select ed when t he BYPASS,
HIGHZ, or CLAMP inst r uct ion is t he cur r ent inst r uct ion in
t he inst r uct ion r egist er .
On t he Capt ur e-DR cont r oller st at e, 0 is loaded int o t he
bypass r egist er . Test dat a can t hen be shift ed fr om t he TDI t o
t he TDO pin on t he Shift -DR st at e. By moving int o t he
Updat e-DR cont r oller st at e, dat a movement t hr ough t he
bypass r egist er is t er minat ed. Table 4 shows t he summar y of
t he oper at ion of t he bypass r egist er .

Table 4

Bypass Register Operation

Controller State Bypass Register

Test-Logic-Reset Retain previous state
Capture-DR 0 is loaded
Shift-DR Shift data toward TDO
Exit1-DR
Exit2-DR
Pause-DR
Retain previous state
Update-DR Retain previous state
All other states Undened

Figure 6

Bypass Register Block Diagram
BYPASS
REGISTER
TDO TDI
0 (Capture-DR state)

Table 3

Supported Instructions

Instruction
IR Code = (IR2 IR1 IR0)
Instruction Type Description

EXTEST (000) Mandatory Permits board-level interconnect testing by applying specic test
data at the output pins to the external interconnection and
capturing the test result at the input pins.
SAMPLE/PRELOAD (001) Mandatory Used to capture data from the input pins and to apply test data
into the latched parallel outputs of the boundary-scan register
while the on-chip system logic is in normal operation.
JPROBE (011) Private Permits access to Actels probe register for system logic signal
probing.
USER INSTRUCTION (100) Reserved Permits access to the application-specic test data register
designed by the user with Actels logic modules.
HIGHZ (101) Optional Used to place the components system logic outputs into an
inactive drive statehigh-impedance state.
CLAMP (110) Optional Permits the use of data in the boundary-scan register to be
driven from component pins while the bypass register is
selected as the serial path between TDI and TDO.
BYPASS (111) Mandatory Permits access to the single-bit shift register data path between
the TDI and TDO pins to facilitate rapid movement of data
through a component when the component does not require
test operation.

5-80

B o un da r y -S c a n R e g i s t e r

The boundar y-scan r egist er is used t o obser ve and cont r ol t he
st at e of each syst em pin, including t he clock pins. Each
boundar y-scan cell consist s of ser ial input ( SI) and ser ial
out put ( SO) t hat ar e connect ed t o each cell, as shown in
Figur e 7. In addit ion, each cell consist s of a par allel input
( PI) and a lat ched par allel out put ( PO) t hat connect t o t he
syst em logic and syst em out put . Thr ee cells ar e used for each
I/O: an input cell ( BS2) , an out put cell ( BS1) , and an
out put -enable cell ( BS0) .
The oper at ion of t he boundar y-scan r egist er under specific
boundar y-scan inst r uct ion is illust r at ed in Tables 5 and 6.
If t he EXTEST inst r uct ion is not being used in conjunct ion
wit h t he SAMPLE/PRELOAD inst r uct ion, t he ext er nal t est
st ar t s by shift ing t he desir ed t est dat a int o t he boundar y-scan
r egist er in t he Shift -DR cont r oller st at e. By moving int o t he
Updat e-DR cont r oller st at e, dat a shift ing is t er minat ed, and
on t he falling edge of t he TCK, t he dat a fr om t he shift -r egist er
st age is t r ansfer r ed ont o t he par allel out put of t he lat ch
st age. The ext er nal t est r esult s ar e loaded int o t he
shift -r egist er st age fr om t he syst em input on t he next
Capt ur e-DR cont r oller st at e and ar e examined by shift ing t he
dat a t owar d TDO on t he next Shift -DR cont r oller st at e.
Dur ing t he SAMPLE/PRELOAD inst r uct ion, t he Shift -DR
st at e is used t o shift out t he dat a capt ur ed fr om t he syst em
input and out put pins for examinat ion dur ing t he Capt ur e-DR
st at e. At t he same t ime, t he Shift -DR st at e shift s in t est dat a
t o be used by t he next boundar y-scan inst r uct ion ot her t han
SAMPLE/PRELOAD. The EXTEST inst r uct ion is usually
init iat ed following t he SAMPLE/PRELOAD inst r uct ion. The
dat a pr eloaded dur ing t he SAMPLE/PRELOAD inst r uct ion
phase becomes available at t he par allel out put of t he
boundar y-scan cells when t he EXTEST becomes t he cur r ent
inst r uct ion on t he falling edge of TCK in t he Updat e-IR st at e.
Similar ly, t he CLAMP inst r uct ion is usually init iat ed
following t he SAMPLE/PRELOAD inst r uct ion. The lat ched
dat a in t he boundar y-scan cell becomes available t o t he
syst em out put pins when CLAMP becomes t he cur r ent
inst r uct ion and when t he bypass r egist er is select ed as t he
dat a pat h fr om TDI t o TDO.

Figure 7

Functional Schematic of Boundary-Scan Cell
BSREG
BSREG
SO
PI
SI
BSREG
SO
SI
EN
From Previous Stage
Output Buffer
BS1
BS2
BS0
To Next Stage
PO
SO
PO PI
SI
Output Enable
Output Data
Input Data
To/From
Sytem
Logic
PI PO

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J PR OB E R e g i s t e r

The J PROBE r egist er consist s of a 2-bit shift r egist er ( labeled
J PRBREG) connect ed t o t he exist ing pr obe r egist er s, as
shown in Figur e 8. The r egist er s t hat ar e dar kened ar e not
par t s of t he J PROBE r egist er . The pr esence of t he J PROBE
r egist er and t he J PROBE inst r uct ion per mit s t he use of t he
int er nal pr obe cir cuit r y t o obser ve and analyze any signal
inside an Act el chip via J TAG.
The desir ed pr obe addr ess is shift ed int o t he J PROBE
r egist er by fir st select ing t he J PROBE inst r uct ion and t hen
moving t o t he Shift -DR cont r oller st at e. Shift ing is
discont inued by ent er ing t he Updat e-DR cont r oller st at e. The
pr obe r esult s ar e loaded int o t he J PRBREG on t he r ising edge
of TCK in t he next Capt ur e-DR cont r oller st at e. The pr obe
r esult s can be examined by moving back t o t he Shift -DR
cont r oller st at e and shift ing t he r esult t owar d TDO. Table 7
shows t he summar y of t he J PROBE oper at ion. The pr obe
r esult s may also be obser ved at t he pr obe pins ( PRA and
PRB) , pr ovided t hat t hese pins have been r eser ved for pr obe
use.
Dur ing t he J PROBE oper at ion, DCLK and SDI input s ar e
disabled. However , if t he cur r ent t est inst r uct ion is differ ent
fr om J PROBE, t he pr obe cir cuit r y can be accessed and
oper at ed nor mally t hr ough t he pr obe pins ( DCLK, SDI, PRA,
and PRB) .

B o un da r y -S c a n De s c r i pt i o n L a n ua g e
( B S DL ) F i l e

Confor mance t o t he IEEE St andar d 1149.1 r equir es t hat t he
oper at ion of t he var ious J TAG component s be document ed.
The BSDL file pr ovides t he st andar d for mat t o descr ibe t he
J TAG component s which can be used by aut omat ic t est
equipment soft war e. The file includes t he inst r uct ions t hat
ar e suppor t ed, inst r uct ion bit pat t er n, and t he boundar y-scan
chain or der .
BSDL files for t he 3200DX family is available on t he Act el
Wor ld Wide Web Homepage ( www.act el.com) and in t he
Act el ft p sit e ( ft p.act el.com) .

Table 5

Summary of EXTEST Operation

Controller State
Boundary-Scan
Shift-Register Stage
Boundary-Scan
Latch Stage Parallel Output (PO)

Test-Logic-Reset Undened Undened Parallel In = Parallel Out
Capture-DR Data at PI is loaded Undened Latched Data
Shift-DR Shift data toward TDO Undened Latched Data
Exit1-DR
Exit2-DR
Pause-DR
Retain previous state Undened Latched Data
Update-DR Retain previous state Latches data from the
shift register
Latched Data = Parallel Out
(on the falling edge of TCK)
All other states Retain previous state Retain previous state Latched Data

Table 6

Summary of SAMPLE/PRELOAD Operation

Controller State
Boundary-Scan
Shift-Register Stage
Boundary-Scan
Latch Stage Parallel Output (PO)

Test-Logic-Reset Undened Undened Parallel In = Parallel Out
Capture-DR Data on PI is loaded Undened Parallel In = Parallel Out
Shift-DR Shift data toward TDO Undened Parallel In = Parallel Out
Exit1-DR
Exit2-DR
Pause-DR
Retain previous state Undened Parallel In = Parallel Out
Update-DR Retain previous state Latches data from the
shift register
Parallel In = Parallel Out
All other states Retain previous state Retain previous state Parallel In = Parallel Out

Note:

During theSAMPLE/PRELOAD instruction, theparallel input and output of theboundary-scan cells aretransparent
(PI equals PO).

5-82

References:

1. Colin M. Maunder & Rodham E. Tulloss.

TheTest Access
Port and Boundary-Scan Architecture

. IEEE Comput er
Societ y Pr ess, 10662 Los Vaquer os Cir cle, P.O. Box 3014,
Los Alamit os, CA 90720-1264.
2. IEEE St d 1149.1-1993, IEEE St andar d Test Access Por t ,
and Boundar y-Scan Ar chit ect ur e. IEEE, Inc., 345 East
47t h St ., New Yor k, NY 10017-2394.
3. Kennet h P. Par ker.

The Boundary-Scan Handbook

.
Kluwer Academic Publisher s, 101 Philip Dr ive, Assinippi
Par k, Nor well, MA 02061.

Table 7

Summary of theOperation of theJ PROBE Register

Controller State JPRBREG Probe Register

Test-Logic-Reset Undened Undened
Capture-DR Probe result loaded when valid address
is in the probe register
Retain previous state
Shift-DR Shift probe address (probe result)
toward TDO
Shift probe address (probe result)
toward TDO
Exit1-DR Exit2-DR Pause-DR Retain previous state Retain previous state
Update-DR Retain previous state Retain previous state
All other states Undened Undened

Figure 8

Functional Schematic of theJ PROBE Register
X2 REGISTER
X1 REGISTER
Y
2
R
E
G
I
S
T
E
R
Y
1
R
E
G
I
S
T
E
R
LOGIC ARRAY
X=x-1
Y=y-1
(0,0)
TDO
TDI
FILLER ZEROS
MODE REGISTER COUNTER REGISTER
PRB PRA
JPRBREG