Midterm Exam Statistics: - ADC Converters

EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling 2007 H.K.
Page 1
Midterm Exam Statistics
0
1
2
3
4
5
6
10 15 16 17 17.5 18
Grade
Max.=20
Number of
Occurrence
Mean=16
Standard Deviation: 2
EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling 2007 H.K. Page 2
EE247
Lecture 18
ADC Converters
Sampling (continued)
Sampling switch considerations
Switch induced distortion
Sampling switch conductance dependence on input
voltage
Clock voltage boosters
Sampling switch charge injection & clock feedthrough
Complementary switch
Use of dummy device
Bottom-plate switching
Track & hold circuits
T/H circuit incorporating gain & offset cancellation
Summary of Last Lecture
DAC Converters (continued)
Dynamic element matching
DAC reconstruction filter
ADC Converters
Sampling (continued)
Sampling switch considerations
Thermal noise due to switch resistance
Sampling switch bandwidth limitations
Switch induced distortion
Sampling switch conductance dependence on input
voltage
Practical Sampling
Summary So Far!
2
2
2
12
B
B
FS
C k T
V
( ) 1 for
in
ON o o ox DD th
DD th
W V
g g g C V V
V V
L

= =

0.72
s
R
B f C
<<
kT/C noise
Finite R
sw
limited bandwidth
g
sw
= f (V
in
) distortion
v
IN
v
OUT
C
M1
1
Switch On-Resistance
SwitchMOS operating in triode mode:
V
in
C
M1
1
V
DD
( ) ( )
( )
( )
0
1
,
2
1 1
is a function of results in distortion
What if instead of connecting G to a fixed voltage,
DS
D triode
DS
D triode ox GS TH DS
ON DS
V
ON
ox GS th ox DD th in
ON in
dI
W V
I C V V V
L R dV
R
W W
C V V C V V V
L L
R V

=

= =

a floating and fixed voltage source is connected to G & S?

Desirable to maximize on voltage of GS Minimize
ON
R
Boosted & Constant V
GS
Sampling
V
GS
=const.
OFF
ON
Increase gate overdrive voltage as
much as possible + keep V
GS
constant
Switch overdrive voltage
independent of signal level
Error due to finite R
ON
linear (to
1st order)
Lower R
on
lower time constant
Higher frequency of operation
Gate voltage V
GS
=low
Device off
Beware of signal
feedthrough due to parasitic
capacitors
Constant V
GS
Sampling
(= voltage @ the switch input terminal)
Constant V
GS
Sampling Circuit
VP1
100ns
M12
M8
M9
M6
M11
Vin
1.5V
1MHz
Chold
P
C1 C2
M1
M2
VDD=3V
M3
C3
M5
M4
P
This Example: All device sizes:10/0.35
All capacitor size: 1pF (except for Chold)
Note: Each critical switch requires a separate clock booster
Vg
Va Vb
Sampling switch & C
PB
Ref: A. Abo et al, A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter, JSSC
May 1999, pp. 599.
PB
Clock Voltage Doubler Operation
C1 C2
M1
0ff
M2
Saturation
mode
VP1
=clock
PB
VDD=03V
P
a) Startup
03V
03V 00
03V 0(3V-V
th
M2
)
Acquire
charge C1 C2
M1
Triode
M2
off
VP1
PB
VDD=3V
P
3V0
3V0
3V03V (3V-V
th
M2
)(6V-V
th
M2
)
b) Next clock transition
03V
VP1
Clock Voltage Doubler Operation
C1 C2
M1
0ff
M2
VP1
PB
VDD=3V
P
03V
03V
3V~6V
3V0
c) Next clock phase
(6V-V
th
M2
)(3V-V
th
M2
)~ 3V
M2
Triode
Acquires
charge
Both C1 & C2
charged to
VDD after one
clock cycle
Note that
bottom plate
of C1 & C2 is
either 0 or
VDD while top
plates are at
VDD or 2VDD
Clock Voltage Doubler
Simulation
C1 C2
M1
M2
VP1
Clock period: 100ns
PB
P_Boost
VDD
2VDD
0
VDD=3V
R1 R2
*R1 & R2=1GOhm
dummy resistors added for simulation only
P
Constant V
GS
Sampler: Low
Sampling switch M11
is OFF
C3 charged to ~VDD
Input voltage
source
M3
Triode
C3
M12
Triode
M4
OFF
VS1
1.5V
1MHz
Chold
1pF
~ 2 VDD
(boosted clock)
VDD
VDD
OFF M11
OFF
Device
OFF
VDD=3V
Constant V
GS
Sampler: High
C3 previously
charged to VDD
M8 & M9 are on:
C3 across G-S of M11
M11 on with constant
VGS = VDD
C3
1pF
M8
M9
M11
VS1
1.5V
1MHz
Chold
1pF
VDD
Constant V
GS
Sampling
Simulation
Input Switch V
Gate
Input Signal
Chold Signal
Boosted Clock Sampling
Complete Circuit
Ref: A. Abo et al, A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter, JSSC
May 1999, pp. 599.
Clock Multiplier
Switch
M7 & M13 for
reliability
Remaining issues:
-V
GS
constant only
for V
in
<V
out
-Nonlinearity due to
Vth dependence of
M11on body-
source voltage
Advanced Clock Boosting Technique
Ref: M. Waltari et al., "A
self-calibrated pipeline
ADC with 200MHz IF-
sampling frontend,"
ISSCC 2002, Dig.
Tech. Papers, pp. 314
Sampling
Switch
clklow
Capacitors C1a & C1b charged to VDD
MS off
Hold mode
Sampling
Switch
clklow
Sampling
Switch
clkhigh
Top plate of C1a & C1b connected to gate of sampling switch
Bottom plate of C1a connected to V
IN
Bottom plate of C1b connected to V
OUT
VGS & VGD of MS both @ VDD & ac signal on G of MS average of V
IN
&
V
OUT
clkhigh
Gate tracks average of input and output, reduces effect of IR drop at
high frequencies
Bulk also tracks signal reduced body effect (technology used allows
connecting bulk to S)
Reported measured SFDR = 76.5dB at f
in
=200MHz
Ref: M. Waltari et al., "A
self-calibrated pipeline
ADC with 200MHz IF-
sampling frontend,"
ISSCC 2002, Dig.
Tech. Papers, pp. 314
Sampling
Switch
Constant Conductance Switch
Ref: H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB
SFDR," IEEE J. Solid-State Circuits, pp. 1769-1780, Dec. 2000
OFF
ON
M2Constant current
constant g
ds
M1replica of M2
& same VGS
as M2
M1 also
constant g
ds
Note: Authors report requirement
of 280MHz GBW for the opamp for
12bit 50Ms/s ADC
Also, opamp common-mode
compliance for full input range
required
Switch Off-Mode Feedthrough Cancellation
Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IF-sampling frontend,"
ISSCC 2002, Dig. Techn. Papers, pp. 314
Practical Sampling
V
o
C
M1
1
R
sw
= f(V
i
) distortion
Switch charge injection & clock feedthrough
V
i
Sampling Switch Charge Injection
Switching from Track to Hold
V
i
V
O
C
s
M1
V
G
First assume V
i
is a DC voltage
When switch turns off offset voltage (V) induced on C
s
Why?
V
G
t
V
H
V
i
V
L
V
i
+V
th
V
O
V
i
t
off
V
t
Sampling
Switch Charge Injection
Channel distributed RC network formed between G,S, and D
Channel to substrate junction capacitance distributed & voltage dependant
Drain/Source junction capacitors to substrate or well voltage dependant
Over-lap capacitance C
ov
= L
D
xWx C
ox
associated with G-S & G-D overlap
MOS xtor operating in triode region
Cross section view
Distributed channel resistance &
gate & junction capacitances
S
G
D
B
L
D
L
C
ov
C
ov
C
j
db
C
j
sb
C
HOLD
Slow Clock
Slow clockclock fall time >> device speed
During the period (t- to t
off
) current in channel discharges channel
charge acquired during the previous clock cycle into low
impedance signal source
Only source of error Clock feedthrough from C
ov
to C
s
V
G
t
V
H
V
i
V
L
V
i
+V
th
t
off
t-
Device still
conducting
Switch Clock Feedthrough
Slow Clock
V
G
t
V
H
V
i
V
L
V
i
+V
th
V
O
V
i
t
off
V
t
D
C
ov
V
G
( )
( )
( ) ( )
( )
( )
ov
i t h L
ov s
ov
i t h L
s
o i
ov ov ov
o i i t h L i t h L
s s s
o i os
ov ov
os t h L
s s
C
V V V V
C C
C
V V V
C
V V V
C C C
V V V V V V 1 V V
C C C
V V 1 V
C C
where ; V V V
C C
= +
+
+
= +

= + =

= + +
= =
t-
C
s
V
O
Switch Charge Injection & Clock Feedthrough
Slow Clock- Example
( )
' 2
ov ox t h L
ov
s
ov
os t h L
s
C 0. 1f F / C 9 f F / V 0. 4V V 0
C 10 x0. 1f F /
. 1%
C 1pF
Al l owi ng 1/ 2LSB ADC resol ut i on ~ 9bi t
C
V V V 0. 4mV
C

= = = =
= = =
= <
= =
V
G
t
V
H
V
i
V
L
V
i
+V
th
V
O
V
i
t
off
V
t
V
i
V
O
C
s
=1pF
M1
V
G
10/0.18
t-
Fast Clock
V
G
t
V
H
V
i
V
L
V
i
+V
th
V
O
V
i
t
off
V
t
V
i
V
O
C
s
=1pF
M1
V
G
Fast gate voltage drop no gate voltage to establish current in channel
channel charge has no choice but to escape out towards S & D
Q
ch
mQ
ch
nQ
ch
n+m=1
For simplicity it is assumed channel charge divided equally between S & D
Source of error channel charge transfer + clock feedthrough via C
ov
to C
s
V
G
t
V
H
V
i
V
L
V
i
+V
th
V
O
V
i
t
off
V
t
Fast Clock
Clock Fall-Time << Device Speed:
( )
( )
( ) ( )
( )
( )
( )
ov ch
o H L
ov s s
ox H i t h ov
H L
ov s s
o i os
ox
s
ov ox H t h
os H L
s s
C 1 Q
V V V
C C 2 C
WC L V V V C 1
V V
C C 2 C
V V 1 V
1 WC L
where
2 C
C 1 WC L V V
V V V
C 2 C
=
+

+
= + +
=
=
Fast Clock- Example
V
i
V
O
C
s
=1pF
M1
V
G
10/0.18
V
G
t
V
H
V
i
V
L
V
i
+V
th
V
O
V
i
t
off
V
t
( )
( )
2
ov ox t h DD L
2
ox
s
ov ox H t h
os H L
s s
C 0. 1f F / , C 9 f F / V 0. 4V,V 1. 8V, V 0
WLC 10 x0. 18 x9 f F /
1/ 2 1. 6% ~ 5 bi t
C 1pF
C 1 WC L V V
V V V 1. 8mV 14. 6mV 16. 4mV
C 2 C
,

= = = = =
= = =
= = =
V
o
V
V
i
Slow Clock versus Fast Clock
Slow Clock
V
o
V
V
i
Fast Clock
Example-Summary
Error function of:
Clock fall time
Input voltage level
Source impedance
Sampling capacitance
Switch size
Clock fall/rise should be well-controlled & not to be faster
(sharper) than necessary
Clock fall time
V
OS
Clock fall time
1.6%
-.1%
16mV
0.4mV
Error Reduction
( )
( )
( ) ( )
ch
o
s
s s
ON s
ox GS t h
ox GS t h
s
o s ox H i t h
2
1Q
V
2 C
C T
R C ( not e : k
W
2
C V V
L
Consi der t he f i gure of meri t ( FOM) :
W
C V V
1 C
L
FOM 2
V C WC L V V V
FOM
L
)
=
= = =
How do we reduce the error?

Reduce switch size?
Reducing switch size increases increased distortion not a viable solution
Small and small V use minimum chanel length (mandated by technology)
For a given technology x V ~ constant
Sampling Switch Charge Injection & Clock Feedthrough
Summary
Extra charge injected onto sampling capacitor @
switch device turn-off
Channel charge injection
Clock feedthrough to C
s
via C
ov
Issues due to charge injection & clock feedthrough:
DC offset induced on hold C
Input dependant error voltage distortion
Solutions:
Complementary switch?
Addition of dummy switches?
Bottom-plate sampling?
Complementary Switch
In slow clock case if area of n & p devices widths are equal (W
n
=W
p
)
effect of overlap capacitor for n & p devices to first order cancel
(cancellation accuracy depends on matching of n & p width and overlap
length L
D
)
Since in CMOS technologies
n
~2.5
p
choice of W
n
=W
p
not optimal
from linearity perspective (W
p
>W
n
preferable)
1B
1B
V
G
t
V
H
V
i
V
L
1

1B
Complementary Switch
Fast Clock
In fast clock case
To 1
st
order, offset due to overlap caps
cancelled for equal device width
Input voltage dependant error worse!
1B
V
G
t
V
H
V
i
V
L
( )
( )
( )
ch n n ox n H i t h n
t h p ch p p ox p i L
ch p ch n
o
s s
o i os
n ox n p ox p
s
Q W C L V V V
V Q W C L V V
Q 1 Q
V
2 C C
V V 1 V
1 W C L W C L
2 C

=
=

= + +
+

Dummy Switch
V
i
V
O
C
s
t
V
H
V
i
V
L
V
G
V
GB
W
M2
=1/2W
M1
V
G
V
GB
M1
M2
M1 M1
1 ch ov
M2 M2
2 ch ov
M2 M1 2 1
1
Q Q Q
2
Q Q 2Q
1
For W W Q Q
2
+
+
= =
Q
1 Q
2
Dummy Switch
V
i
V
O
C
s
t
V
H
V
i
V
L
V
G
V
GB
Dummy switch same L as main switch but half W
Main device clock goes low, dummy device gate goes high dummy
switch acquires same amount of channel charge main switch needs to
lose
Effective only if exactly half of the charge stored in M1 is transferred to M2
(depends on input/output node impedance) and requires good matching
between clock fall/rise
W
M2
=1/2W
M1
V
G
V
GB
M1
M2
Q
1 Q
2
Dummy Switch
V
i
V
O
M1
V
G
M2
V
GB
To guarantee half of charge goes to each sidecreate the same
environment on both sides
Add capacitor equal to sampling capacitor to the other side of the switch
+ add fixed resistor to emulate input resistance of following circuit
Issues: Degrades sampling bandwidth
C
s C
s
R
W
M2
=1/2W
M1
Dummy Switch Effectiveness Test
Ref: L. A. Bienstman et al, An Eight-Channel 8 13it Microprocessor Compatible NMOS D/A
Converter with Programmable Scaling, IEEE JSSC, VOL. SC-15, NO. 6, DECEMBER 1980
Dummy switch
W=1/2W
main
As Vin is
increased Vc1-Vin
is decreased
channel charge
decreasedless
charge injection
Note large Ls
good device
area matching
Differential Sampling
V
i+
V
O+
V
i-
V
O-
To 1
st
order, offset terms cancel
Note gain error still about the same
Has the advantage of better immunity to
noise coupling and cancellation of even
order harmonics
Cs
Cs
( )
( )
( )
( )
o o od i i i d
o o i i
oc i c
o i 1 os1
o i 2 os2
1 2
od i d i d 1 2 i c os1 os2
V V V V V V
V V V V
V V
2 2
V V 1 V
V V 1 V
V V V V V V
2

+ +
+ +
+ +

= =
+ +
= =
= + +
= + +
+
= + + +
Avoiding Switch Charge Injection
Bottom Plate Sampling
Switches M2 opened slightly earlier compared to M1
Injected charge by the opening of M2 is constant since its DS voltage
is zero & eliminated when used differentially
Since C
s
bottom plate is already open when M1 is opened
No charge injected on C
s
1a
V
H
V
L
t
1b
V
i
V
O
M1
1b
1a
M2
Cs
Flip-Around Track & Hold
v
IN
v
OUT
C
S1A
1D
S2
2
S2A
2
S3
1D
1 S1
v
CM
Concept based on bottom-
plate sampling
1D
Flip-Around T/H-Basic Operation
1
high
v
IN
v
OUT
C
S1A
1D
S2
2
S2A
2
S3
1D
1 S1
v
CM
Charging C
1D
2
Note: Opamp has to be
stable in unity-gain
configuration
Q
1
=V
IN
xC
Flip-Around T/H-Basic Operation
2
high
v
IN
v
OUT
C
S1A
1D
S2
2
S2A
2
S3
1D
1 S1
v
CM
Holding
1D
Q
2
=V
OUT
xC
V
OUT
=V
IN
Flip-Around T/H - Timing
S1 opens earlier than S1A
No resistive path from C
bottom plate to Gnd charge
can not change
"Bottom Plate Sampling"
v
IN
v
OUT
C
S1A
1D
S2
2
S2A
2
S3
1D
1 S1
v
CM
1D
Charge Injection
At the instant of transitioning from track to hold
mode, some of the charge stored in sampling
switch S1 is dumped onto C
With "Bottom Plate Sampling", only charge
injection component due to opening of S1 and
is to first-order independent of v
IN
Only a dc offset is added. This dc offset can be
removed with a differential architecture
Flip-Around T/H
v
IN
v
OUT
C
S1A
1D
S2
2
S2A
2
S3
1D
1 S1
v
CM
Constant switch V
GS
to minimize distortion
Note: Among all switches
only S1A & S2A
experience full
input voltage swing
1D
Flip-Around T/H
S1 is chosen to be an n-channel MOSFET
Since it always switches the same voltage, its on-
resistance, R
S1
, is signal-independent (to first order)
Choosing R
S1
>> R
S1A
minimizes the non-linear
component of R = R
S1A
+ R
S1
Typically, S1A is a wide (much lower resistance than S1) &
constant V
GS
switch
In practice size of S1A is limited by the (nonlinear) S/D
capacitance that also adds distortion
If S1As resistance is negligible delay depends only on S1
resistance
S1 resistance is independent of V
IN
error due to finite
time-constant independent of V
IN
Differential Flip-Around T/H
Ref: W. Yang, et al. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDR at Nyquist Input, IEEE
JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001 1931
Offset voltage associated with charge injection of S11 & S12 cancelled by differential
nature of the circuit
During input sampling phaseamp outputs shorted together
S11
S12
Gain=1
Feedback factor=1
2
Issues: Input Common-Mode Range
V
in-cm
=V
out_com
-V
sig_com
Amplifier needs to have large input common-mode compliance
Issues: Input Common-Mode Range
V
in-cm
=V
out_com
-V
sig_com
Amplifier needs to have large input common-mode compliance
Input Common-Mode
Cancellation
Ref: R. Yen, et al. A MOS Switched-Capacitor Instrumentation Amplifier, IEEE JOURNAL OF
SOLID-STATE CIRCUITS, VOL. SC-17, NO. 6,, DECEMBER 1982 1008
Note: Shorting switch M3 added
Input Common-Mode Cancellation
Track mode ( high)
V
C1
=V
I1
, V
C2
=V
I2
V
o1
=V
o2
=0
Hold mode ( low)
V
o1
+V
o2
=0
V
o1
-V
o2
= -(V
I1
-V
I2
)(C
1
/(C
1
+C
3
))
Input common-mode level removed
T/H + Charge Redistribution Amplifier
Track mode: (S1, S3 on S2off)
V
C1
=V
os
V
IN
, V
C2
=0
V
o
=V
os
T/H + Charge Redistribution Amplifier
Hold Mode
Hold/amplify mode (S1, S3 off S2on)
Offset NOT cancelled, but not amplified
Input-referred offset =(C
2
/C
1
) x V
OS
, & often C
2
<C
1
2
1
2
T/H & Input Difference Amplifier
Sample mode (S1, S3 on S2off)
V
C1
=V
os
V
I1
, V
C2
=0
V
o
=V
os

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EECS 247- Lecture 18 Nyquist Rate ADCs-Sampling 2007 H.K.

a floating and fixed voltage source is connected to G & S?

How do we reduce the error?

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