VHDL was originally developed at the behest of the U.

S Department of Defense in order to document

the behavior of the ASIs that supplier companies were including in e!uipment.
"he idea of being able to simulate the ASIs from the information in this documentation was so
obviously attractive that logic simulators were developed that could read the VHDL files. "he ne#t step
was the development of logic synthesis tools that read the VHDL$ and output a definition of the
physical implementation of the circuit.
Due to the Department of Defense re!uiring as much of the synta# as possible to be based on Ada$ in
order to avoid re%inventing concepts that had already been thoroughly tested in the development of
Ada$&citation needed' VHDL borrows heavily from the Ada programming language in both concepts
and synta#.
"he initial version of VHDL$ designed to I((( standard )*+,%)-.+$ included a wide range of data
types$ including numerical /integer and real0$ logical /bit and boolean0$ character and time$ plus arrays
of bit called bit1vector and of character called string.
A problem not solved by this edition$ however$ was 2multi%valued logic2$ where a signal3s drive
strength /none$ wea4 or strong0 and un4nown values are also considered. "his re!uired I((( standard
)),5$ which defined the -%value logic types6 scalar std1logic and its vector version std1logic1vector.
"he updated I((( )*+,$ in )--7$ made the synta# more consistent$ allowed more fle#ibility in naming$
e#tended the character type to allow IS8%..9-%) printable characters$ added the #nor operator$ etc.
&specify'
:inor changes in the standard /;*** and ;**;0 added the idea of protected types /similar to the
concept of class in <<0 and removed some restrictions from port mapping rules.
In addition to I((( standard )),5$ several child standards were introduced to e#tend functionality of
the language. I((( standard )*+,.; added better handling of real and comple# data types. I(((
standard )*+,.7 introduced signed and unsigned types to facilitate arithmetical operations on vectors.
I((( standard )*+,.) /4nown as VHDL%A:S0 provided analog and mi#ed%signal circuit design
e#tensions.
Some other standards support wider use of VHDL$ notably VI"AL /VHDL Initiative "owards ASI
Libraries0 and microwave circuit design e#tensions.
In =une ;**,$ the VHDL "echnical ommittee of Accellera /delegated by I((( to wor4 on the ne#t
update of the standard0 approved so called Draft 7.* of VHDL%;**,. >hile maintaining full
compatibility with older versions$ this proposed standard provides numerous e#tensions that ma4e
writing and managing VHDL code easier. ?ey changes include incorporation of child standards /)),5$
)*+,.;$ )*+,.70 into the main )*+, standard$ an e#tended set of operators$ more fle#ible synta# of case
and generate statements$ incorporation of VH@I /interface to A<< languages0 and a subset of @SL
/@roperty Specification Language0. "hese changes should improve !uality of synthesiBable VHDL
code$ ma4e testbenches more fle#ible$ and allow wider use of VHDL for system%level descriptions.
In Cebruary ;**.$ Accellera approved VHDL 5.* also informally 4nown as VHDL ;**.$ which
addressed more than -* issues discovered during the trial period for version 7.* and includes enhanced
generic types. In ;**.$ Accellera released VHDL 5.* to the I((( for balloting for inclusion in I(((
)*+,%;**.. "he VHDL standard I((( )*+,%;**. was published in =anuary ;**-.