PAL SYSTEM IMAGE CAPTURING DOCUMENT FOR IIREP

1 Scope of the Document

This Document will explain about the Glue logics Implemented for Capturing the image from
PAL Decoder(AD7180) and DDR3 SDRAM Usage and Image displayed to PAL Encoder(AD7393)
chip.
2 Introduction of the Module
Infrared Image and Range Enhancement Processing (IIREP) unit is image enhancement
system which is based on multi million gate Xilinx Kintex-7 FPGA, TI Davinci DSP and with its
associated memory. It supports the PAL analog video inputs, outputs and Digital Video input, output.
IIREP is used for image enhancement of the target picture or video even in adverse weather
conditions. The system combines set of special algorithms that will specifically useful for image
enhancement, Filtering and target detection and tracking, shall consists of controllers, which is two 7
series FPGA and DaVinci DSP Processors.
The FPGA and DSP based card shall have three numbers of FPGA's and one number of TI
DaVinci DSP processor for analog and digital video signal processing. Ten million logic gate capacity
of FPGA's to meet the logic and computational requirements. All image processing algorithms shall be
implemented in FPGA to meet the real time requirements and TI DaVinci DSP processor to meet the
networked media encode and decode in digital media video processing.
The brief explanation is below for the logic's implemented for Capturing image and displaying
image by using PAL decoder and Encoder chips in the board.
3 Logic Diagram
PAL DECODER
YCBCR DATA
CAPTURING
MACRO
PAL_IN_DATA(7: 0)
(Ycbcr = 4:2:2)
int erlaced
PAL_LLC_CLK
(27Mhz)
PAL_IN_Hsync_n
PAL_IN_Vsync_n
Macro_enable
Ycbcr(63: 0)
Ycbcr_Dat a_wr
FIFO
(4K)
DDR3
INTERLACED
WRITE FSM
MACRO
Ycbcr_Data_rd
YCbCr_dat a( 127:0)
DDR3 CORE 1
(SDRAM_1)
DDR3_1_WRDATA(
127:0)
DDR3_1_ADDR(26:
0)
DDR3_1_WR_CTRL
SIGNALS
DDR3
PROGRESSIVE
READ FSM
MACRO
DDR3_1__RDVALID
DDR3_1_RDDATA(
127: 0)
FIFO
(8K)
Progressive
Ycbcr( 127:0)
Progressive_dat a
_wr
IMAGE
PROCESSING
ALGORITHAMS
PROCESSING
DATA GET
LOGICS
PROCESSING
DATA SEND
LOGICS
ALGORITHM_DATA_EN
ALGORITHM_IN_DATA( 31:0)
Macro_enable
PAL ENCODER
YCBCR DATA
SENDING
MACRO
PAL_IN_DATA(7:0)
( Ycbcr = 4: 2:2)
interlaced
PAL_LLC_CLK
(27Mhz)
Macro_enable
Algor _Ycbcr( 63:0)
Ycbcr_Dat a_rd
IMAGE
READ
FIFO
(8K)
DDR3
INTERLACED
READ FSM
MACRO
Algor_Ycbcr
Data_wr
ALGOR_YCbCr
data( 127: 0)
DDR3 CORE 2
(SDRAM_2)
DDR3_2_RDDATA(
127:0)
DDR3_2_RDVALID
DDR3
PROGRESSIVE
WRITE FSM
MACRO
DDR3_2_ADDR(26:0)
DDR3_2_WRDATA(
127: 0)
OUT FIFO
(8K)
Progressive
Algor_ycbcr(127:0)
Progressive_dat a
_rd
ALGORITHM_DATA_RDY
ALGORITHM_OUT_DATA( 31:0)
PAL_OUT_DATA(7:0)
( Ycbcr = 4:2:2)
interlaced
PAL_LLC_OUT_CLK
(27Mhz)
Signals From
PAL Decoder Chip
Signals To
PAL Encoder Chip
DDR3_1_RD_CTRL
SIGNALS
DDR3_2_RD_CTRL
SIGNALS
DDR3_2_WR_CTRL
SIGNALS
IIREP PAL SYSTEM DATA
PROCESSING LOGICS
4 Design Description
1 PAL DECODER YCBCR DATA CAPTURING MACRO
In this IIREP Module the PAL Decoder(ADV7180) chip is used to capture the PAL
Video data. It will automatically detects and converts standard analog base band television
signals compatible with worldwide NTSC, PAL, and SECAM standards into 4:2:2 component
video data compatible with the 8-bit ITU-R BT.656 interface standard.
This macro gets the digitized data from this ADV7180 in the form of interlaced 4 : 2 : 2
(Cb, Y, Cr, Y) shown below.
This macro will detect the SAV code only for active video from the received digital
data and decode the YCBCR data and forms the 64 bit data as ((x00,xY2,xCb,xCr) &
(x00,xY1,xCb,xCr)) along with generate FIFO write signal.
This data will be continuously write in to the 4K FIFO. This FIFO will generate enable
signal to the DDR3 interlaced write FSM when it gets more than one line data. The Interface
Macro generates the necessary DDR3 control signal to write into the DDR3 memory.
Whenever this macro gets enable signal and DATA_RDY signal from the FIFO it will generate
the write control signals and interlaced address as (lines count & field in & data count) for the
DDR3_1_core along with 128 bit YCBCR data from the FIFO to the DDR3_1_MIG core.
2 DDR3 INTERLACED WRITE FSM MACRO
The FIELD_IN signal determines the input data processed is odd or even. If the value of the FIELD_IN
is '0' odd data is processed and '1' data is even. For single frame processing we apply a FLD RST
(Field Reset). This is ensure the proper line counting and other logic function exactly as prescribed by
the user.
Timing Diagram of DDR3 (WRITE) :
Timing Diagram of DDR3 (READ) :
3 DDR3 PROGRESSIVE READ FSM MACRO
Whenever this macro gets enable signal and Programmable empty signal from the 8K FIFO it
will generate the read control signals and progressive address as (lines count & data count) for the
DDR3_1_core.
And it will get the DDR3_1_core, 128 bit progressive read data and Rd_valid signal from the
MIG core and continuously write to the 8K FIFO. This 8K FIFO will generate the Data rdy signal to the
Image processing algorithm logic's when more than one line data present.
4 IMAGE PROCESSING ALGORITHAMS
Processing Data Get/Send Logic's
This macro is used for get the Progressive image 32 bit YCBCR pixel data from the 8K FIFO
continuously and send to the selected image processing algorithm.
After processing, this macro is responsible to generate the FIFO(8K) write signal along with the
processed YCBCR data to 8K out FIFO.
The processed 32 bit YCBCR pixel data is continuously written to the 8K out FIFO. This 8K
FIFO will generate the Data rdy signal to the Progressive write FSM when more than one line data
present.
5 DDR3 PROGRESSIVE WRITE FSM MACRO
Whenever this macro gets enable signal and DATA_RDY signal from the out 8K FIFO it will
generate the write control signals and Progressive address as (lines count & data count) for the
DDR3_2_core along with 128 bit YCBCR processed data from the out 8K FIFO to the DDR3_2_MIG
core.
6 DDR3 INTERLACED READ FSM MACRO
Whenever this macro gets enable signal and Programmable empty signal from the 8K IMAGE
READ FIFO it will generate the read control signals and Interlaced address as (lines count & Field In
& data count) for the DDR3_2_core.
And it will get the DDR3_2_core, 128 bit interlaced read data and Rd_valid signal from the MIG
core and continuously write to the 8K IMAGE READ FIFO.
7 PAL ENCODER YCBCR DATA SENDING MACRO
In this IIREP Module the PAL Encoder(ADV7393) chip is used to Display the PAL
Video data. The ADV7393 have an 8-bit video input port that supports SD video formats over
an SDR interface. The logic's implemented here will route the Digitized YCBCR data from the
PAL decoder Chip(ADV7180) to the PAL encoder chip(ADV7393) via this macro.
If this macro gets enable, this will detects the SAV code for active video from the digitized
YCBCR data , and encode the Processed data instead of the actual received data, by generating
FIFO read signal to the IMAGE READ 8K FIFO, and send to the PAL Encoder Chip(ADV7393).
8 PAL DECODER(ADV7180) REGISTER SETTINGS
9 PAL ENCODER(ADV7393) REGISTER SETTINGS