ANALOG ELECTRONIC CIRCUITS LAB

[ICE 212]
2 BIT SYNCHRONOUS COUNTER USING T
FLIPFLOPS
Submitted by
1.Sunanda Rajmohan 12!"211#!
2. $o%& $ohn 'a(ha) 12!"212*!
+EPART'ENT OF INSTRU'ENTATION AN+ CONTROL ENGINEERING
'ANIPAL INSTITUTE OF TECHNOLOGY
(A Constituent College of Manipal University)
MANIPAL 5761!" #A$NA%A#A" IN&IA
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S)0na(u,%
1. Sunanda Rajmohan
2. $o%& $ohn 'a(ha)
La1 In.2ha,0% ',. 'u3und 4uma, '%non

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Page No
A'stra(t )
List *f +igures )
List *f %a'les )
Cha7(%, 1 INTRO+UCTION
1.
1
Intro,u(tion
1.
2
Literature $evie-s
1./.1 / input N*$ gate
1.
9
0000000000000
1.
/
000000000000....
Cha7(%, 2 'ETHO+OLOGY
2.
1
Intro,u(tion (N*%12 brief about the outline of the chapter)
2.
2
%3eory
2.
9
&esigning Pro(e,ure
Cha7(%, 9 RESULT
9.
1
Intro,u(tion (N*%12 brief about the outline of the chapter)
9.
2
*'servation
Cha7(%, / CONCLUSION:INFERENCE
9.
1
Con(lusion4Inferen(e
9.
2
15tension to t3e pro6e(t
/
REFERENCE
ANNE;URE (N*%12 Include transistor datasheets etc.)
ABSTRACT
A syn(3ronous up (ounter using % flip flop is ,esigne, using /n//// transistors an, resistors.
1a(3 flip flop -as in,ivi,ually (onstru(te, an, t3en (onne(te, toget3er to o'tain t3e (ounter.
LIST OF TABLES
Ta1&% No Ta1&% T)(&% Pa0% No
1 / input N*$ gate 7
/ ) input An, gate 7
) % flip flop 7
LIST OF FIGURES
F)0u,% No F)0u,% T)(&% Pa0% No
1 Asyn(3ronous (ounter output 8
/ Logi( &iagra9 % flip flop 8
) Cir(uit for :;%(3ara(teristi(s (/N////a)
! $ising an, falling e,ges of syn(3ronous (ounters
)
CHAPTER 1
INTRO+UCTION
1.1 In(,odu2()on
%3is spe(ifi( (3apter ,is(usses t3e usage" (onstru(tion an, 9a<ing of an syn(3ronous )
'it (ounter using %(toggle)= flipflop.
Counters are spe(ialise, registers. %3ey go t3roug3 a pres(ri'e, se>uen(e of states upon
t3e appli(ation of input pulses. %3ere are / (atagories of (ounters 'ase, on ,ifferent
,esign styles2
a) Asyn(3ronous4 $ipple Counters 2 In t3is (ounter t3e flipflop are not triggere, 'y t3e
(o99on (lo(< pulse 'ut 'y t3e transition in t3e ot3er flip flop outputs.

') ?yn(3ronous (ounter 2 In t3is (ounter t3e flipflops are triggere, 'y a (o99on (lo(<
pulse.
1.2L)(%,a(u,% R%<)%=
1./.1 In ele(troni(s" a flip=flop or lat(3 is a (ir(uit t3at 3as t-o sta'le states an, (an 'e
use, to store state infor9ation. A flip=flop is a 'ista'le 9ultivi'rator. %3e (ir(uit (an 'e
9a,e to (3ange state 'y signals applie, to one or 9ore (ontrol inputs an, -ill 3ave one
or t-o outputs. It is t3e 'asi( storage ele9ent in se>uential logi(. +lip=flops an, lat(3es
are a fun,a9ental 'uil,ing 'lo(< of ,igital ele(troni(s syste9s use, in (o9puters"
(o99uni(ations" an, 9any ot3er types of syste9s.
+lip=flops an, lat(3es are use, as ,ata storage ele9ents. ?u(3 ,ata storage (an 'e use, for
storage of state" an, su(3 a (ir(uit is ,es(ri'e, as se>uential logi(. @3en use, in a finite=
state 9a(3ine" t3e output an, ne5t state ,epen, not only on its (urrent input" 'ut also on
its (urrent state (an, 3en(e" previous inputs). It (an also 'e use, for (ounting of pulses"
an, for syn(3roniAing varia'ly=ti9e, input signals to so9e referen(e ti9ing signal.
+lip=flops (an 'e eit3er si9ple (transparent or asyn(3ronous) or (lo(<e, (syn(3ronous)"
(lo(<e, ,evi(es are ,es(ri'e, as flip=flops.
!
1./.1 %-o input N*$ gate
+ig 1.
+ig /.
?tate %a'le for / input N*$ gate
In7u( 1 In7u(2 A2()on
1
1 1 1
!
! 1
%a'le 1.
5
1././ %3ree input AN& gate
+ig ).
+ig !.
6
?tate %a'le for a ) input AN& gate
In7u( 1 In7u( 2 In7u( 9 A2()on
!
! 1
! 1
! 1 1
1
1 1
1 1
1 1 1 1
%a'le /.
1./.) ?tate ta'le of % flipflop
In7u( In7u(2 A2()on
! 1 No (3ange
1 1 %oggle
%a'le ).
1./.! %i9ing ,iagra9 of ) 'it syn(3ronous (ounter using % flip flop
7
+ig 5.
7
CHAPTER 2
'ETHO+OLOGY
2.1 INTRO+UCTION
A syn(3ronous up (ounter using % flip flop is ,esigne, using /n//// transistors an, resistors
of ))<" !.7< an, 1<. ?yn(3ronous se>uential (ir(uit is a syste9 -3ose 'e3avior (an 'e ,efine,
fro9 t3e <no-le,ge of its signals at ,is(rete instants of ti9e
2.2 THEORY
A syn(3ronous 'inary (ounter (ounts fro9 to /n=1 -3ere n is t3e nu9'er of 'its or
flipflops in t3e (ounter. 1a(3 flipflops is use, to represent one 'it . %3e flipflops in t3e lo-est
or,er position is (o9ple9ent4 toggle, -it3 every (lo(< pulse an, a flipflop in any ot3er
position is (o9ple9ente,.
%3e flipflop in t3e lo-est or,er position is (o9ple9ente, on t3e ne5t (lo(< provi,e, to all
t3e 'its in t3e lo-er or,er positions are e>ual to one.
%3e (ounter -or<s in t3is fas3ion2
A
)
A
/
A
1
B 11
*n t3e ne5t (ount A) A/ A1 B 1.
A1" t3e lo-est or,er 'it is al-ays (o9ple9ente,. A/ is (o9ple9ente, 'e(ause all t3e lo-er
or,er positions (A1 only in t3is (ase are 1s. A) is t3e (o9ple9ent 'e(ause all t3e lo-er or,er
positions A/ an, A1 are 1s.
%o i9ple9ent a syn(3ronous (ounter " -e nee, a flipflop for every 'it" e5(ept t3e first an,
t3e last 'it.
Alt3oug3 t3e (ounter is syn(3ronous an, is suppose, to (3ange si9ultaneously" -e 3ave a
propagation ,elay t3roug3 t3e AN& gates -3i(3 a,, up to give an overall propagation ,elay
-3i(3 is proportional to t3e nu9'er of t3e 'its of t3e (ounter.
8
2.9 +ESIGNING PROCE+URE
1. %3e syn(3ronous (ounter (onstru(te, is a ) 'it" 3en(e (onsist of ) 'it %(toggle) flip flop.
/. %3e toggle flip flop -as (onstru(te, using / t3ree input AN& C / t-o input N*$ gates.
). %3e output of t3e first flip flop is fe, to t3e se(on," -3i(3 is fe, to t3e t3ir, an, t3e final
output is ta<en fro9 3ere.
!. %3e % flip flop 3as a ten,en(y to toggle -3en 'ot3 inputs are 3ig3.
5. %3e transistors use, in t3e (ir(uit are (o99on e9itter transistors -it3 output fro9 t3e
e9itter.
6 . %3e t3ree flip flops are 9a,e on t3e 'rea, 'oar,s using (onne(ting -ires an, t3en
(onne(te, to t3e IC trainer <it using pat(3 (3or,s.
7. &ata s3eet of t3e transistor /N////A
?DM:*L PA$AM1%1$ C*N&I%I*N? MIN. MAE. UNI%
FC:* (olle(tor='ase voltage open e9itter
/N////A G 75 F
FC1* (olle(tor=e9itter voltage open 'ase
/N////A G ! F
IC (olle(tor (urrent (&C) G 7 9A
Ptot total po-er ,issipation %a9' H /5 IC G 5 9@
3+1 &C (urrent gain IC B 1 9AJ FC1 B 1 F 75 G
f% transition fre>uen(y IC B / 9AJ FC1 B / FJ f B 1 MKA
/N////A ) G MKA
1
CHAPTER 9
RESULT
9.1 INTRO+UCTION
%3e t-o 'it syn(3ronous (ounter -as ,esigne,. It -as teste, 'y triggering ea(3 t flip flop
in,ivi,ually an, (3e(<ing t3e outputs a((or,ing to t3e state ta'le of a % flip flop. %3en t3e
t-o flip flops -ere (onne(te, toget3er as a t-o 'it syn(3ronous (ounter.
9.2 OBSER>ATION
It is o'serve, t3at t3e % flip flop retains t3e state -3en %BLL an, t3e % flip flop toggles its
state -3en %BL1L .
%3e % input of ea(3 Mip=Mop is (onne(te, to a (onstant 1" -3i(3 9eans t3at t3e
state of t3e Mip=Mop -ill 'e toggle, at ea(3 a(tive e,ge of its (lo(<. %3e purpose of t3is
(ir(uit is to (ount t3e nu9'er of pulses t3at o((ur on t3e pri9ary input (alle, Clo(<.
%3us t3e (lo(< input of t3e Nrst Mip=Mop is (onne(te, to t3e Clo(< line. %3e ot3er t-o Mip=
Mops 3ave t3eir (lo(< inputs ,riven 'y t3e output of t3e pre(e,ing Mip=Mop. %3erefore" t3ey
toggle t3eir states -3enever t3e pre(e,ing Mip=Mop (3anges its state fro9 O B 1 to O B "
-3i(3 results in a positive e,ge of t3e signal.
11
CHAPTER /
CONCLUSION:INFERENCE
/.1 CONCLUSION:INFERENCE
With the Synchronous Counter, the external clock signal is connected to the clock input of
every individual flip-flop within the counter so that all of the flip-flops are clocked together
simultaneously (in parallel) at the same time giving a fixed time relationship. In other words,
changes in the output occur in synchronisation with the clock signal.
!he result of this synchronisation is that all the individual output "its changing state at exactly the
same time in response to the common clock signal with no ripple effect and therefore, no
propagation delay.
Synchronous Counters use edge-triggered flip-flops that change states on either the positive-
edge (rising edge) or the negative-edge (falling edge) of the clock pulse on the control input
resulting in one single count when the clock input changes state.
#enerally, synchronous counters count on the rising-edge which is the low to high transition of
the clock signal and asynchronous ripple counters count on the falling-edge which is the high to
low transition of the clock signal.
$ig %.

It may seem unusual that ripple counters use the falling-edge of the clock cycle to change state,
"ut this makes it easier to link counters together "ecause the most significant "it (&'() of one
counter can drive the clock input of the next.
!his works "ecause the next "it must change state when the previous "it changes from high to
low ) the point at which a carry must occur to the next "it. 'ynchronous counters usually have a
carry-out and a carry-in pin for linking counters together without introducing any propagation
delays.
1/
REFERENCE
1. T%?(1oo3 @ A. Anand 4uma,
2. +a(a6h%%(2a(a&o0.2om
9. A)3)7)d%a.2om
/. a&&a1ou(2),2u)(6.2om
B. )&o<%2),2u)(6.2om
*. (,an6)6(o,23(=,&d.2om
1)
ANNE;URE
1!