A PRACTICAL APPROACH IN

MODELLING SILICON-CROSSTALK
IN SYSTEMS-ON-SILICON.
PAUL T.M. VAN ZEIJL
ERICSSON
EMMEN
THE NETHERLANDS
Paul.van.Zeijl@eln.ericsson.se

S eptember 6, 2001 1
 Table of contents.

• Introduction: problem statement.

• Approaches to Si-crosstalk: state-of-the-art and its problems.
• Our strategy.
– Modelling digital circuitry.
– Modelling pure CMOS substrates.
– Modelling BiCMOS/RFCMOS substrates.
– Modelling analog circuitry.
• Requirements on digital and analog design.
• Conclusions.

S eptember 6, 2001 2 © E rics s on, Paul T .M. van Z eijl

 Problem Statement 1(3).
• Possible causes of crosstalk:
– Crosstalk on the PCB.
– Crosstalk via the bonding wires and package.
– Crosstalk via ground and supply lines.
– Crosstalk due to the Si-substrate.
• Consequences of interfering signals due to crosstalk:
– Addition of signals (linear).
– Modulation of signals (non-linear):
• May create extra spurious components.
• May shift bias points.
• May give pushing/pulling effects on VCO/XO.
• We don’t have ways to easily predict the magnitude
effect(s) of crosstalk-on-silicon.

S eptember 6, 2001 3 © E rics s on, Paul T .M. van Z eijl

 Problem Statement 2(3).

S eptember 6, 2001 4 © E rics s on, Paul T .M. van Z eijl

 Problem Statement 3(3).

• Options for minimising Si-crosstalk:

– Separate in the frequency domain (this may prove difficult due
to high data-rates).
– Separate in the time domain (no digital activity during
reception/transmission of signals).
– Lower amplitude of interference source (introduce jitter on
clocks).
– Isolate (use extra layout measures such as shielding or triple-
well).
– Compensate or balance.
• BUT how much improvement do we get from these
measures?

S eptember 6, 2001 5 © E rics s on, Paul T .M. van Z eijl

 Approaches to Si-crosstalk: state-of-the-art
limitations
• Large number of digital gates (> 1M); not practical in
analog simulations.
• Fast slopes in digital circuits in state-of-the-art CMOS
processes.
• Complexity in substrate extraction (practical size and
simulation time for the substrate model).
• Low-frequency digital (~ MHz) vs analog/RF (~ GHz).
• Can only done after layout has been finalised.
• Usually done after receiving 1st silicon, because there
are “problems”.
• For a lot of designers it is like “black-magic”.

S eptember 6, 2001 6 © E rics s on, Paul T .M. van Z eijl

 Our strategy.

• Start during the design phase of the ASIC.

• Use the knowledge of the digital circuitry/functionality to
start modelling it; use a simple model.
• Use the floorplan to get a model for the substrate.
• Specify analog/RF circuitry properly.
• Use the analog circuitry and simulate for interference
sensitivity.
• Use a simple model for the digital circuitry, the model for
the substrate and the analog circuitry to do analog
simulations on the overall performance. Compare with
specifications.

S eptember 6, 2001 7 © E rics s on, Paul T .M. van Z eijl

 Example of specification of VCO pulling.

∆f = 5 kHz when switching RX/TX mixers ON

Ref.: P.T.M. van Zeijl et all, ESSCIRC, Southampton, 1997
S eptember 6, 2001 8 © E rics s on, Paul T .M. van Z eijl
 Modelling digital circuitry 1(4).

• Model the digital interfering source by:

– Icc at given Vcc.
– Frequency.
– Is the behaviour dominated by clocked signals or more like a
pseudo-random-bit-sequence (PRBS)?
– Use simple LARGE inverter to speed up simulation.
– If needed model VCC/GND capacitive coupling to substrate.

S eptember 6, 2001 9 © E rics s on, Paul T .M. van Z eijl

 Modelling digital circuitry; clocked signals 2(4).

Spectrum of clock signals:

f_clock=10 MHz
t_rise=t_fall=1ns
duty-cycle=45/55.

f_clock= 10MHz,
t_rise=t_fall=100ps
duty-cycle=45/55.

Frequency from DC to 2.5 GHz.

Amplitude from -100 to 0 dB.
S eptember 6, 2001 10 © E rics s on, Paul T .M. van Z eijl
 Modelling digital circuitry; PRBS 3(4).
Spectrum of PRBS signals:

f_clock=10 MHz.
t_rise=t_fall=100p.

Frequency from DC to 2.5 GHz.

Amplitude from -100 to 0 dB.

Frequency from DC to 50 MHz.

Amplitude from -50 to 0 dB.

S eptember 6, 2001 11 © E rics s on, Paul T .M. van Z eijl

 Modelling digital circuitry; I_substrate 4(4).
1k inverter:
• Substrate voltage, 1 nH series
inductance to PCB-gnd, 10 MHz
clock, 1 Vpp.
• Substrate short-circuit current,
+20 mAp, -40 mAp.

• Spectrum of substrate voltage:

resonance at 4 GHz: 1 nH//1.3 pF.

Frequency from DC to 5 GHz.

Amplitude from -100 to 0 dB.

S eptember 6, 2001 12 © E rics s on, Paul T .M. van Z eijl

 Substrate modelling 1(8); low-impedance
substrate: 0.35u pure CMOS.

• Contents of ASIC:
– Analog blocks: LNA, VCO, front-end, etc.
– Digital blocks: large inverters, at various places in the layout to
check distance dependency.
• Inverters are driven by sinusoidal signals so that
crosstalk on the PCB, or crosstalk due to the bonding
wires and package is avoided.

S eptember 6, 2001 13 © E rics s on, Paul T .M. van Z eijl

 Substrate modelling 2(8): 0.35um pure CMOS;
low-impedance substrate.

1998

S eptember 6, 2001 14 © E rics s on, Paul T .M. van Z eijl

 Substrate modelling 3(8): simulation model for
0.35u pure CMOS substrate.

S eptember 6, 2001 15 © E rics s on, Paul T .M. van Z eijl

 Substrate modelling 4(8): comparison of
measurements versus simulations.

T hird harmonic:
Meas ured: *
S imulated: o

0.35um pure CMOS

F requency from 1 MHz to 2 GHz.

Amplitude from -50 to =100 dB uV.
S eptember 6, 2001 16 © E rics s on, Paul T .M. van Z eijl
 Substrate modelling 5(8): 0.35u pure CMOS
substrate; conclusions.

• A pure CMOS substrate can be modelled as a short.

• Impedance to PCB-ground (bonding-wire and package)
should be taken into account (including series
resistance and inductance).
• Separation distance is not important.

S eptember 6, 2001 17 © E rics s on, Paul T .M. van Z eijl

 Modelling BiCMOS/RFCMOS substrates 6(8).

• Buried-N, triple-well can be used for extra isolation.

• Sometimes extra mask, sometimes part of standard
processing.
• Modelling substrate:
– Estimate area per block (from floorplanning).
– Estimate number of substrate contacts per block.
– Use tools to generate netlist model.

S eptember 6, 2001 18 © E rics s on, Paul T .M. van Z eijl

 Modelling BiCMOS/RFCMOS substrates:
example 7(8).

Acknowledgement goes to:

Didier Belot from STMicroelectronics
Francois Clement from Simplex
S eptember 6, 2001 19 © E rics s on, Paul T .M. van Z eijl
 Modelling BiCMOS/RFCMOS substrates 8(8):
conclusions.

• Remarks when generating such a substrate model:

– Minimise the number of substrate contacts.
– Up to ~ GHz, the substrate model can be considered purely
resistive.
– Minimise the size of the netlist (32 Mbyte vs 1 Mbyte).
– Limit the values of the elements in this netlist to reasonable
values and range.

S eptember 6, 2001 20 © E rics s on, Paul T .M. van Z eijl

 Modelling analog circuitry.

S eptember 6, 2001 21 © E rics s on, Paul T .M. van Z eijl

 Example of simulation testbench.

S eptember 6, 2001 22 © E rics s on, Paul T .M. van Z eijl

 Requirements on digital and analog circuitry.

• Specify PSRR for all analog/RF circuits.

• Specify CM-rejection for all analog/RF circuits.
• Specify CM⇒DM conversion for all analog/RF circuits.
• Specify pushing/pulling for oscillators and VCO’s.
• Separate power supplies.
• Use shielded bonding-pads or shielded bump-pads.
• Use bumping for very low impedance to PCB-ground.

S eptember 6, 2001 23 © E rics s on, Paul T .M. van Z eijl

 Conclusions.

• Do pre-layout simulations
• Create problem awareness in design-team
• Get input from digital designers.
• Si-crosstalk has to be taken into account from the start:
one more issue on the list of the analog designers,
increasing design complexity.
• Consequently: more compromises in (RF) design!
RF design becomes (even more) multidimensional.

S eptember 6, 2001 24 © E rics s on, Paul T .M. van Z eijl