296 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO.

2, FEBRUARY 2006

Evolution of Substrate Noise Generation Mechanisms

With CMOS Technology Scaling
Mustafa Badaroglu, Member, IEEE, Piet Wambacq, Member, IEEE, Geert Van der Plas, Member, IEEE,
Stéphane Donnay, Member, IEEE, Georges G. E. Gielen, Fellow, IEEE, and Hugo J. De Man, Fellow, IEEE

Abstract—Substrate noise is a major obstacle for single-chip

integration of mixed-signal systems. To reduce this problem and
to assess its evolution with CMOS technology scaling, the different
mechanisms that generate substrate noise and their dependen-
cies on different parameters need to be well understood. In this
paper, we show that with downscaling of the technology, substrate
noise due to supply coupling becomes the dominant coupling
mechanism when the chip substrate is directly biased with the
digital ground. With Kelvin ground substrate biasing on the other
hand, source/drain capacitive coupling becomes the dominant
coupling mechanism. Further, we show that with downscaling,
the peak value of the supply coupling noise component becomes
more dependent on the relative ratio of the switching capacitance Fig. 1. Three substrate noise coupling mechanisms in an inverter. (1) Impact
to the nonswitching capacitance, which is formed by the circuit ionization. (2) S/D coupling. (3) Supply coupling.
decoupling and the nonswitching circuit elements, rather than the
Ldi/dt noise. These insights illustrated in a quantitative framework
are believed to be very useful for the systematic use of digital parasitic inductance will reduce substrate noise. However, for a
low-noise design techniques in future CMOS technologies. large circuit a reduction of the inductance does not necessarily
reduce the peak value of the substrate noise voltage [5]. If
Index Terms—Circuit analysis, deep submicron, International
Technology Roadmap for Semiconductors (ITRS), low-noise this is the case, the only ways to reduce the peak value of the
design, mixed analog–digital integrated circuits (ICs), substrate substrate noise voltage are to increase the decoupling and/or to
noise, supply noise, technology scaling. increase the isolation of the substrate.
The work in [5] and [6] presents an effective use of low-noise
digital design techniques by addressing that most of the supply
I. INTRODUCTION
current via the impedance goes through the gate and

S UBSTRATE noise is a major obstacle for single-chip in-

tegration of mixed-signal systems [1]. The previous pub-
lications have mostly analyzed the substrate noise generation
mechanisms individually and have compared them only experi-
mentally to each other in an effort to find the dominant mecha-
nism without looking at the boundary conditions determining
their dominance [2], [3]. These publications only considered
small or fixed-size circuits such as I/O buffers [4].
However, the size constraints of digital circuits together with
external (package) parasitics define the boundary conditions
for substrate noise generation and determine which mechanism
dominates in practice. This is important for a designer to choose
the most efficient technique to reduce the substrate noise gener-
ation. For example, general practice suggests that reducing the
Manuscript received June 7, 2004; revised April 26, 2005. This paper was
recommended by Associate Editor M. Stan.
M. Badaroglu is with the IMEC, B-3001 Leuven, Belgium (e-mail:
badar@imec.be).
P. Wambacq is with the IMEC, B-3001 Leuven, Belgium, and also with Vrije
Universiteit Brussel, 1050 Brussels, Belgium.
G. Van der Plas and S. Donnay are with the IMEC, B-3001 Leuven, Belgium.
G. G. E. Gielen is with the Katholieke Universiteit Leuven, B-3001 Leuven,
Belgium.
H. J. De Man is with the IMEC, B-3001 Leuven, Belgium, and also with the
Katholieke Universiteit Leuven, B-3001 Leuven, Belgium.
Digital Object Identifier 10.1109/TCSI.2005.856049
1057-7122/$20.00 © 2006 IEEE
its load, while a part of this current capacitively couples into the
substrate. However, that work has not addressed the conditions
that determine the dominant noise injection mechanism. We will
demonstrate that there are other noise generation mechanisms,
and that the dominance of one of these mechanisms highly de-
pends on the circuit size, on the method of substrate biasing,
and on the external parasitics. In this paper, such boundary con-
ditions are derived to find the dominant coupling mechanism.
Technology scaling has been exploited in order to design
high-performance and low-power digital circuits. The future
projection of the substrate noise has usually been addressed
with a focus on the efficiency of decoupling [7] or layout-level
techniques [8]. In this paper, we predict the scaling of sub-
strate noise using the International Technology Roadmap for
Semiconductors (ITRS) 2004 [9] roadmap parameters with a
focus on the significance of the generation mechanisms in the
light of low-noise design techniques [10]. It is shown that the
supply coupling becomes more severe in future technology
nodes when the substrate is directly biased with the digital
ground while the source/drain (S/D) capacitive coupling loses
importance. With Kelvin ground biasing of the substrate, the
S/D coupling is more dominant.
The paper is organized as follows. Section II describes the
mechanisms that cause substrate noise (illustrated for an inverter
in Fig. 1): 1) impact ionization; 2) S/D coupling; and 3) supply

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BADAROGLU et al.: EVOLUTION OF SUBSTRATE NOISE GENERATION MECHANISMS 297

TABLE I
DESCRIPTION OF VARIABLES

Fig. 2. Schematic flow of the substrate currents in and around a digital gate,
and an analog circuit on the same die.

Fig. 3. Equivalent resistive substrate network configurations for: (a) substrates

with a grounded backside node, (b) bulk-type substrate with a floating backside
node, and (c) EPI-type substrate with a floating backside node. Depending on
the technology used, the proper configuration has to be inserted in Fig. 2. values by uppercase symbol with no time argument. In addi-
tion, whenever it is necessary, we also discuss the power of these
coupling. Section III presents an analysis to determine the dom- time-varying signals.
inant injection mechanism. Section IV analyzes the future evo- We now consider the three injection mechanisms.
lution of substrate noise as a function of the ITRS 2004 roadmap
parameters. Section V provides conclusions. A. Impact Ionization
The hole current flowing out of the drain into the substrate
II. SUBSTRATE NOISE INJECTION MECHANISMS due to hot-electron effects is known as impact ionization current
The flow of the generated substrate currents in and around a . An approximate expression for the impact ionization
digital gate is shown in Fig. 2, while the different resistive sub- current , which is related to the total ground return
strate network configurations that depend on the type of sub- current , is given by [13]
strate are shown in Fig. 3, with a description of all variables
in Table I. The resistances are computed analytically [2], [11]
or using an extraction tool [12]. The capacitances are computed (2)
using the SPICE parameters and the geometry data. The package
parasitics are extracted from measurements. where and are parameters that must be fitted empirically
For the sake of simplicity in comparison, we assume that the to measurement data. Typical values for are 1 to 3 V , and
injection mechanisms are mutually exclusive. That is, when the for 10 to 30 V. is the drain-source voltage.
noise is injected into the bulk via the S/D junction capacitance, is the drain-source voltage at the onset of saturation. is
neither supply noise nor impact ionization exists, or vice versa. given by [14]
In fact, the current (similarly for ) is given as the
sum of different injection mechanisms (3)

(1)
where is the critical electrical field at which the mobility of
where and are the parts of the cur- the carriers (electrons/holes) saturates. is the effective
rent due to impact ionization, S/D coupling, and supply length of an nMOS (pMOS) transistor.
coupling, respectively. For the sake of quantitative comparison As an illustration, we consider an nMOS device with
of the currents, we use the peak values of the time-varying cur- m, V, V, V/ m,
rents although these peaks do not necessarily happen at the same V , and V. Using (2) we find that the
time. In this paper we represent the peak value of the time-do- current is several orders of magnitude smaller than the
main currents by the notation , while we represent the dc current (Fig. 4) at = . At this point,

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298 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 2, FEBRUARY 2006

where is the sum of the oxide capacitances of the fanout

logic and the interconnect capacitance seen at the output of the
switching gate. is the sum of all capacitances of the
switching gate, which need to be charged by the gate itself. Note
that also contains .
The current injected from the junction splits into
three parts: represents the part taken away via the
substrate contacts, whereas is the part that is picked up
by the sensitive analog circuit (Fig. 2), and is the part
that is picked up by the backside contact if grounded. We typi-
cally have since the analog well is
placed far away from the digital well and also the well doping is
order(s) of magnitude larger than the substrate doping. For a far
away analog circuit we also have
Fig. 4. The [i (t)] =[i (t)] ratio for an nMOS device in a 0.18 m
1.8 V CMOS process with V = 1:8 V. since the vertical resistance from the digital bulk to the backside
node is much lower than the lateral resistance. Using the approx-
the current in a switching digital circuit becomes imations above and using the networks in Fig. 3, the
maximum. In some other operating points, on the other hand, value is found for the following cases.
the ratio is only around 100, but the • For substrates with a grounded backside node [Fig. 3(a)]
absolute values are negligibly small at these operating points.
The measurements described in [3] are in line with these
conclusions.
(6)
B. S/D Capacitive Coupling
Due to the pn-junctions between the S/D regions of the tran- • For bulk-type substrates with a floating backside node
sistors and the substrate/well, switching noise is injected into [Fig. 3(b)]
the substrate during switching of a S/D node (current
in Fig. 2). The unit area/perimeter capacitance of such a junc- (7)
tion is given in [15]
• For EPI-type substrates with a floating backside node
[Fig. 3(c)], see (8) at the bottom of the page.
(4)
Similarly, the current picked up by a backside ground con-
tact yields a conservative bound for the current leaving the well.
where is the built-in junction voltage. and are the
Here, we consider a hypothetical analog circuit where we as-
doping levels of the substrate/well (p-type) and the drain/source
sume that its sensitive local bulk node is shorted to this ground
(nMOS) regions, respectively. is the junction grading expo-
plane and that no other analog substrate contact exists. In this
nent. is the magnitude of unit electronic charge (
case, we find for both EPI-and bulk-type substrates
C). is the permittivity of silicon ( F/cm). Fur-
ther, is the junction reverse-bias voltage. The total capaci-
tance consists of the bottom-plate and sidewall components, the
latter ones being negligible in modern processes that use shallow (9)
trench isolation (STI).
We now compute the ratio for a dig- The resistance between the bulk underneath the
ital gate. By assuming that the time constants of the load and drain and a square-shaped substrate contact with an edge size
of the junction capacitances are equal, we can neglect the time within the p-well and separated by a distance
dependence of the ratio. We also assume that all drain nodes in is given by [11]
the gate switch at the same time. With these assumptions, the
ratio is given by the ratio of the load
to the drain junction capacitances of the nMOS transistor. Note
that the effect from the pMOS is neglected due to the shielding (10)
by the n-well. The ratio is defined by
where we typically have . is
the resistivity of the p-well (typically 100 m cm) and is
(5)
the thickness of the contact (typically 1 m).

(8)

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BADAROGLU et al.: EVOLUTION OF SUBSTRATE NOISE GENERATION MECHANISMS
TABLE II
COMPUTATION OF DIFFERENT COMPONENTS OF [i (t)] =[i (t)]
RATIO (K ) FOR THREE TECHNOLOGIES: A 0.18-m PROCESS (BULK-TYPE),
A 0.35-m AND A 0.50-m PROCESS (BOTH EPI-TYPE)
The resistance between two square p-wells with
an edge size and with a separation on a bulk-
type substrate is given by [11]
when
2D case
when
3D case
where we typically have . and
are the thickness values of the substrate and of the well,
respectively. is the resistivity of the substrate (typically
10 cm). For the calculation of on bulk-type sub-
strates, the 2-D case is applicable when analog circuits are as-
sumed to be placed far from digital circuits with a distance larger
than the thickness of the substrate ( – m).
Table II lists the values computed for the load capacitances
and the ratio for the CMOS inverter
in several technologies: 0.18-, 0.35-, and 0.50 m CMOS.
The backside contact is grounded. Each inverter drives another
identical inverter. For the 0.18- m inverter, the layout and
the extracted substrate parameters are shown in Fig. 5. The
ratio for the 0.18 m inverter is the
higher than for the 0.35 m and 0.50 m inverters due to two
reasons: (1) higher resistivity of the bulk-type substrate, and
(2) larger values due to a smaller S/D area due to 45 degree
poly lines and STI (which reduces the drain-bulk capacitances).
Similar analysis for other standard cells has shown that the
resistive division from (6) and (7) has about the same value
as a result of using a fixed-height standard cell library where
the substrate contact area is proportional to the width of the
standard cell.
From the results of Table II, we conclude that the
value is at least an order of magnitude larger than the
value. On the other hand, these conclusions
are not enough to decide that S/D coupling is not a dominant
injection mechanism. Therefore, we first need to know the
injection mechanism due to the supply coupling. This will be
described in the next section. Then, in Section III, we present
a quantitative framework that uses these results for finding
which noise injection mechanism actually dominates under the
size constraints of the circuit together with external (package)
parasitics.
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299
Fig. 5. Layout and extracted substrate resistances for the nMOS device of the
inverter in a 0.18-m 1.8-V CMOS process on a bulk-type substrate.
(11)
Fig. 6. Illustration of switching in a circuit with ideal switches.
C. Supply Coupling
In digital circuits, high peaks of the supply current of the
switching gates create supply noise in the supply network
(Fig. 6). In a p-type substrate this supply noise couples ca-
pacitively into the substrate from via the n-well junction
capacitance, and resistively from via the substrate contacts.
The supply noise consists of two parts: common-mode (CM)
and differential-mode (DM) noise [16]. CM noise is caused
by the imbalance between supply current and ground return
current when a circuit is driven by input signal(s) referenced to
power region(s) different from the one of this circuit. DM noise
is caused by the oscillations of the damped LC tank formed
between the circuit capacitance and the supply parasitics. For
a digital circuit of practical size, the portion of gates driven by
input(s) referenced to different power regions is substantially
low. Also the combinations of rising/falling transitions at the
input(s) have a canceling effect on the CM noise, which is not
the case for the DM noise. From now on, we assume that the
supply noise only consists of DM noise.
The amount of DM supply noise oscillations is found by ana-
lyzing the network shown in Fig. 6. In this network the equiva-
lent switching capacitance is represented by , which is the
average (dis)charged capacitance of the switching gates. Here
the term is the switching activity factor that is defined as the
ratio of the equivalent switching circuit capacitance to the total
circuit capacitance . The term is typically between
and . We define the equivalent nonswitching capacitance of
300 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 2, FEBRUARY 2006

the circuit , which is the average capacitance of From Section II.A, it was concluded that the impact ionization
the nonswitching gates. In addition, the decoupling capacitance mechanism can be neglected.
is a part of the equivalent nonswitching capacitance be- The dominance of supply coupling versus S/D coupling will
tween and . We define as the total duration of the now be judged by comparing (7) and (14). For the sake of
current charging the switching capacitance. This current is indi- brevity, here we consider bulk-type substrates with a floating
cated as in Fig. 6. We assume that this current is a trian- backside node. We will now describe the scaling of the currents
gular waveform with equal rise/fall times. The current coming with the number of gates . For the part we
from the external power supply and from the nonswitching ca- need to scale the resistance of a unit gate with
pacitances are indicated as and , respectively, in the total number of gates due to many parallel resistive
Fig. 6. There are two extreme cases that indicate which param- paths from the digital substrate contacts (that are connected to
eters to control in order to reduce the supply noise: (1) the case a single voltage source that models the total ground
when the nonswitching capacitance provides most of the cur- bounce in the system). For the part, we need to
rent required by the switching circuits, and (2) the case when scale the value with the total number of switching
the external power supply provides most of the current required gates . On the other hand, we do not scale the resis-
by the switching circuits. tances since for each gate the junction-related noise is injected
The first case occurs when where is from an individual source, which is the switching node of the
the resonance frequency where circuit. We also ignore the contribution of the impedance from
. We have in the comparison since the spec- the substrate contact(s) to the off-chip ground on the overall
tral bandwidth of the switching current is determined by impedance from the bulk node to the off-chip ground. After
either the rise or fall time, which is half of the total duration this scaling procedure, the supply coupling current is dominant
. We define the voltage transients and if the following condition is satisfied:
as the bounces on the ground and the positive supply rail, re-
spectively, measured on the die, referred to the external power
supply, which is assumed to be clean. For , and
, the ground bounce value at

(12) (15)

Equation (12) suggests that a smaller ratio of the switching where

capacitance to the nonswitching capacitance is useful for noise
reduction.
The second case occurs when . The supply
current of the switching circuits is now mostly supplied from the for each gate.
external power supply. In this case, for and , If the relation holds, then (13) is appli-
we have cable for . By combining (13) and (15), we
find the ratio
(13)
(16)
In the case where (13) is applicable, reducing the inductance
and increasing the switching time has a first-order effect on re- Equation (16) states that using a package with a smaller
ducing the supply noise [17]. inductance and/or decreasing will reduce the
The current injected from the substrate contact, ratio. On the other hand, if the re-
which is typically connected to the ground of a digital circuit, lation holds, then (12) is applicable for
flows toward the ground of an analog circuit. The part of the cur- . In this case, the
rent that is picked up by the analog circuit due to the supply-cou- ratio becomes
pling mechanism is . The value is given by

(14)

where is given by (11). For , we have

. (17)

Equation (17) states that the ratio

III. ANALYSIS OF DOMINANT MECHANISM IN does not change with since increasing will increase
SUBSTRATE NOISE GENERATION at the same rate, therefore resulting in no change in the overall
In the previous sections, the peak values of the currents that ratio. Therefore, if we increase in a system, initially the
arise from the two major mechanisms of substrate noise in- ratio increases with due to (16),
jection (supply coupling and S/D coupling) have been derived. then the ratio starts to level off as a result of the transition from

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BADAROGLU et al.: EVOLUTION OF SUBSTRATE NOISE GENERATION MECHANISMS 301

(16) to (17) since with increasing values of , the term

increases and exceeds the term .
Important for substrate noise coupling is also the way in which
the substrate is connected to the ground. The dedicated bias for
the well, the so-called Kelvin grounding (KG), is an effective
technique for avoiding the coupling of supply noise into the
substrate at the expense of an increase in cell area and a reduction
of decoupling capacitance. The latter is due to the fact that the
well capacitance would otherwise have added to the decoupling
capacitance. A reduction of decoupling increases the ground
Fig. 7. Effect of GR on (a) supply coupling and (b) S/D coupling.
bounce in the system but the shielding between the substrate
and the noisy ground rail is now better than without KG. In this
case, the S/D coupling can become a dominant substrate noise
injection mechanism if the following condition is satisfied:

where

(18)

where is the resistance between the bulk and the

Kelvin ground, and is the parasitic capacitance be-
tween the digital ground and the bulk. Here, the term is
defined as the factor of reduction of the supply coupling as a re-
sult of KG. When we have
Fig. 8. [i (t)] =[i (t)] ratio (from SPICE simulations) as a
, we have . In addition, the Kelvin ground should function of the number of gates (Lp(g ) = 1 nH and A = 0:15) for two CMOS
be well separated from the digital ground to avoid capacitive processes with a grounded backside plane: 0.18 m on a bulk-type substrate
coupling between these rails. In 0.18 m CMOS for a ground and 0.35 m on an EPI-type substrate.
rail (in Metal 1) with a length of 2.0 m and a width of 0.96 m,
the extracted value of is 0.39 fF. For a similar geom- for extra I/O pins providing a low-impedance (clean) ground bi-
etry in a gate with a width of 2.0 m, is typically asing GR [19].
in the order of a few tens of k . For instance, if for each gate in The derived formulas for the ratio
a circuit we have fF and are also valid for the ratio with the
k , then this circuit should have a resonance frequency less than only difference that the factor
7.95 GHz in order to make KG effective. should be added in (16) to (18).
Guard rings (GRs) can also reduce the substrate noise cou- This factor is not dependent on technology scaling. Here, we
pling. On the other hand, the GR grounding should be properly consider a hypothetical analog circuit where its sensitive local
done, otherwise, GR could act as a highway for the noise to bulk node is shorted to the backside ground plane and that no
propagate into the sensitive circuits. The use of GR grounding other analog substrate contact exists. From now on we will
for the isolation of supply coupling is illustrated in Fig. 7(a). use the ratio for the simulations
In the case of a grounded GR, the path passing through the presented in this section, but remember that it is proportional to
GR node is shorted to ground with the GR ground impedance. the ratio.
Only the resistance remains, hence supply cou- Fig. 8 demonstrates the ratio (by
pling is reduced since where SPICE simulations) for two CMOS processes: (1) 0.18 m on a
is the resistance between the digital well and the bulk-type substrate, and (2) 0.35 m on an EPI-type substrate.
analog well before the introduction of a GR. Similar conclu- In the figure the ratio is shown as a function of the number of
sions are derived for S/D coupling by means of Fig. 7(b). For unloaded inverters with pH and for a
instance, in [18], the authors show that properly grounding the grounded backside plane and with the substrate directly biased
GR reduces the spurious components in the measured output by the digital ground. The simulated netlist also contains the
spectrum of a VCO by 75 dB below the VCO frequency at substrate network extracted using the tool in [12]. Note that for
3.5 GHz. Note that noise levels that degrade the performance the values used, the saturated ratio is lower for the 0.35 m
of the analog circuit depend on the transfer function from sen- EPI-type substrate than for the 0.18 m bulk-type substrate.
sitive substrate node(s) of that analog circuit to its output. The In fact, the ratio can be much
guard-ring impedance requirements become more difficult in a higher in reality since the output of simultaneously switching
mixed-signal system with a large digital circuit. These require- gates can be either falling or rising when they are switching
ments bring the need for a wider GR using extra silicon area and simultaneously (rather than switching all in the same direction

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302 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 2, FEBRUARY 2006

( K gates) when the chip substrate is directly biased with the

digital ground. With KG the S/D coupling current becomes the
dominant injection mechanism. In the next section we describe
the impact of technology scaling on the significance of the in-
jection mechanisms in the light of the efficiency of low-noise
digital design techniques.

IV. EFFECT OF THE ITRS TECHNOLOGY

ROADMAP ON SUBSTRATE NOISE
In the technology nodes below 0.13 m, subthreshold
leakage current becomes an important limitation for further
downscaling of the threshold voltages with the supply voltage
when the geometric dimensions scale down. For this reason, the
semiconductor industry today uses different scaling schemes for
Fig. 9. The [i (t)] and [i (t)] values as a function of the the dimensions and the voltage [9], namely by scaling factors
inductance with the number of inverters as a parameter and with activity factor and , respectively. The inductance is scaled down
A = 0:30.
by in order to accommodate the scaling of the package
inductance. In this section we describe the consequences of this
as assumed in Fig. 8). This will create a significant reduction scaling on the generation mechanisms of substrate noise.
on the current but not on the current . In The relation between substrate doping and scaling has ini-
addition, the value is much larger than the tially been introduced in [20]. In order to reduce the depletion
value since the current consists of region width by a factor , the channel doping should be in-
damped oscillations while the current is a short trian- creased with a factor [20]. In this case, the substrate/well
gular waveform. We conclude that the supply-coupling current doping concentration should also be increased in order to avoid
is always dominant above a certain circuit size ((16)) regardless bulk punchthrough [21]. Today’s technologies employ selec-
of which substrate type is used. However, it is more dominant tive doping such as p-wells in a p-type substrate, rather than
in high-ohmic substrates than in EPI-type substrates. This changing the whole doping of the substrate. Therefore, the wafer
conclusion can also be reached by comparing the saturation resistivity is a given parameter by the wafer manufacturer
values of the ratio (Fig. 8). and it does not change with scaling.
These results are now verified by SPICE simulations for We will now discuss the scaling of the substrate noise injec-
several circuits of different sizes in a 0.18 m 1.8 V CMOS tion mechanisms: impact ionization, S/D coupling, and supply
process on a bulk-type substrate. The netlist also contains the coupling (Fig. 1). The resistance from the bulk
substrate network extracted using the tool in [12]. Fig. 9 shows node of a transistor to the substrate contact (Fig. 2) is approxi-
the and values as a function of the mately proportional to the inverse of the well doping. Therefore,
inductance with the number of unloaded inverters as the doping level and hence scales with a factor
parameter. The parameters and the layout of each inverter are . On the other hand, the resistance from a bulk
shown in Fig. 5. Each circuit has a switching activity factor node of a transistor in digital circuits to the bulk of analog cir-
of . The values have a dependency on cuits is proportional to the resistivity of the substrate. The
but the values do not. For each circuit, the resistance is considered here due to the fact that a
value is linearly dependent on below a certain similar equation holds for the part of the impact ionization cur-
inductance value. On the other hand, reducing is always rent affecting analog circuits:
better for a reduction of the RMS value as a result of more
damping. Above this value the peak value of the transients is not
(19)
dependent on . We call this inductance value as the corner
value of for the circuit where each value has been indicated
with a circle in Fig. 9. Above the corner value, the By this, the value scales with
value is determined by the circuit size , the switching ac- (by using (2) and (19)). Here indicates the scaling
tivity factor , and the substrate (15). Below the corner value, factor of the substrate resistivity. The constant in the exponen-
the value decreases linearly with until the tial refers to the term dependent on the variables and
substrate noise is dominated by . For example, for the ((2)) of the technology node used as reference for scaling.
circuit with 5K inverters, the substrate noise is dominated by The increase of the well doping also increases the junction ca-
for inductance values below 2 pH. In a circuit where pacitance per unit area/perimeter with a scaling factor of
S/D coupling is the dominant mechanism, substrate noise can (from (4) for an abrupt junction ). The voltage de-
be reduced by increasing the number of substrate contacts, by pendence of the junction capacitance can be ignored due to low
increasing the isolation of the substrate, and by balancing the supply voltages. The overall junction capacitance scales down
amount of rising and falling transitions at a given time instant. by considering the scaling of the bottom-plate area
From this section we conclude that the supply coupling is . As a result, the normalized peak value of the S/D cou-
the dominant injection mechanism for circuits of practical size pling current will scale by .

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BADAROGLU et al.: EVOLUTION OF SUBSTRATE NOISE GENERATION MECHANISMS 303

TABLE III TABLE IV

SCALING CONSEQUENCES ON CMOS CIRCUITS AND
MECHANISMS OF SUBSTRATE NOISE GENERATION
ON EFFECT OF ITRS 2004 SCALING ON SUBSTRATE NOISE COMPONENTS FOR A
CIRCUIT WITH 10 K (LEFT) AND 5 (RIGHT) TWO-INPUT NAND GATES
(W = 10 L AND FANOUT = 3). FOR EACH COMPONENT, THE TABLE SHOWS
RELATIVE FACTORS OF CHANGE WITH RESPECT TO HIGH-PERFORMANCE
LOGIC IN 90 nm. EACH COMPONENT IS NORMALIZED TO THE SUPPLY
VOLTAGE OF THE TECHNOLOGY NODE

grounding is properly done. On the other hand, technology

scaling brings requirements for the number of ground bumps
used for the GR. When supply coupling is the dominant mech-
anism, the resonance frequency of the supply determines this
number. In this case, the number of ground bumps should scale
with . When S/D coupling is the dominant mechanism,
The normalized peak value of the supply coupling current the switching time of the gates determines this number. In this
scales either with for small cir- case, the number of ground bumps should scale with .
cuits ( K-gates) or with for large circuits ( K-gates). Next, we will illustrate this evolution using the ITRS 2004
These results show that without KG supply coupling becomes roadmap parameters [9]. Table IV shows the effect of scaling
a severe problem in future technology nodes while S/D cou- on the normalized substrate noise components for 10 K (left)
pling loses its importance due to the increase of the well doping. and 5 (right) two-input NAND gates . Each cir-
Table III summarizes the impact of technology scaling on the cuit has an activity factor . Each NAND gate drives
mechanisms of substrate noise generation. a load equivalent to three times its input capacitance. For each
Technology scaling has a significant impact on the efficiency technology node the noise components were computed using
of KG where its efficiency is judged by the factor ((18)). the formulas defined in Table III and the ITRS 2004 parame-
When we have , the ters. In Table IV there are three normalized substrate noise com-
factor scales with , due to the direct multiplica- ponents: 1) impact ionization current, 2) S/D coupling current,
tion of the terms (scales with ), (scales and 3) supply coupling current without/with KG. The last term
with , and (scales with ). Here, is computed in two ways, the one using the traditional formula
is a scaling factor in order to accommodate the scaling of the Ldi/dt and the other simulating the network in Fig. 6. During
dielectric constant between the metal and the bulk. The term the simulations for every technology node, the package para-
for is used in order to scale down the width of the sitics are kept fixed at nH and the substrate resis-
power rail as a result of decrease in the peak current of each tivity does not change with scaling . Using 10 K and 5
switching gate. It can be concluded that KG becomes more ef- NAND gates during the simulation is an arbitrary choice. Using
fective with technology scaling. 10 K gates gives while using 5 gates gives
Contrary to KG, the technology scaling does not have a . The results for 10 K gates are similar for
significant impact on the use of GRs since the efficiency of say 5 M NAND gates with the same inductance since for 5 M
a GR is only dependent on the substrate resistivity when the NAND gates we still have . With the choice

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304 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 2, FEBRUARY 2006
of these two extreme cases, the conclusions from these simula-
tions can be generalized for other circuits. We hereby demon-
strate a worst-case situation for S/D coupling where all gates
are switching in the same direction. During the simulations we
consider a practical system where each gate and its input(s) are
referenced to a single power region. Therefore, the supply noise
only consists of DM noise. Similar conclusions can also be de-
rived when we consider the CM noise [16].
For all cases in the simulation the significance of impact ion-
ization decreases substantially. Therefore, it can be ignored. It
scales down the slowest in low-standby-power logic due to the
fact that the supply voltage scales down the slowest in this logic.
For 10 K gates with no KG, the supply coupling com-
puted using the equivalent network given by Fig. 6 does not
scale with technology scaling. On the other hand, for 5 gates
with no KG, the supply coupling scales at the same rate as
(di/dt)/ given by (13). The rate of
scaling is the fastest in high-performance logic due to the fact
that the switching time scales down the fastest in this logic. In
both cases the supply coupling dominates the S/D coupling.
When we use KG, the situation reverses, i.e., the supply
coupling scales down much faster than the S/D coupling. This
means that the S/D coupling continues to be the dominant in-
jection mechanism (if for the current technology we achieve to
reduce the supply-coupling by means of KG). Fast downscaling
of the supply coupling is due to downscaling of the metal-bulk
parasitic capacitance of each gate despite the fact that the
resonance frequency increases with technology scaling. But
the impact of the decreasing capacitance is much faster than
the impact of the increasing resonance frequency. This capac-
itance decreases since with technology scaling the metal-bulk
dielectric material improves and the geometric dimensions of
the power rail of each gate scale down.
V. CONCLUSION
In this paper we have analyzed the different generation mech-
anisms of substrate noise under the size constraints of the circuit
together with external (package) parasitics and depending on the
substrate grounding. We have also analyzed their evolution with
ITRS 2004 roadmap. By knowing the significance of all injec-
tions, a designer can choose the most efficient low-noise design
technique for enabling the integration of mixed-signal systems
in future CMOS technologies.
The supply coupling will become an even more dominant
mechanism in future technology nodes when the substrate is di-
rectly biased with the digital ground. The relative ratio of the
supply coupling current to the supply voltage will increase 4.5 x
when a circuit is fabricated in a 22 nm technology node com-
pared to a 90 nm realization with the same package. This in-
crease happens for circuits having their supply resonance fre-
quency larger than the inverse of their switching time. Other-
wise, the peak value of the supply coupling becomes depen-
dent on the switching activity factor and not on the technology
scaling. The latter case is likely to dominate in future technology
nodes. In this case, supply coupling can only be reduced by
adding more decoupling, by shaping the supply current, and/or
by reducing switching activity.
The use of KG can eliminate the dominance of supply cou-
pling but at the expense of an increase in the ground bounce
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and an increase in die area. With technology scaling KG be-
comes more effective. With proper KG, the S/D coupling will
become the dominant noise injection mechanism. In this case,
substrate noise can be reduced by increasing the number of sub-
strate contacts, by using a high-ohmic substrate, and by em-
ploying GRs. For GRs the grounding should be properly done,
otherwise the GR could act as a highway for the noise to propa-
gate into the sensitive circuits. Technology scaling increases the
required number of bumps used for grounding the GR, but oth-
erwise does not change the efficiency of a GR. For all cases the
significance of impact ionization can be ignored.
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Mustafa Badaroglu (S’00–M’05) received the
B.Sc.degree from Bilkent University, Ankara, Turkey,
in 1995, the M.Sc. degree from Middle East Technical
University, Ankara, Turkey, in 1998, and the Ph.D.
degree from Katholieke Universiteit Leuven, Leuven,
Belgium, in 2004, all in electrical engineering.
Since 1999, he has been with IMEC, Leuven,
Belgium, where he is now a Senior Researcher.
From 1996 to 1998, he was a Researcher with the
Scientific and Technical Research Council of Turkey
(TUBITAK), Ankara, Turkey, where he worked
on design and implementation of embedded microcontrollers, digital signal
processors, and several mixed-signal integrated circuits. At IMEC, he has
worked on deep-submicron design automation, low-power design, and design
and implementation of WLAN and UWB transceivers. His research interests
include deep-submicron effects analysis/suppression, low-noise/power design,
and supply/clock networks.
Dr. Badaroglu was the recipient of the 2004 European Design and Automation
Association (EDAA) doctoral dissertation award and of the Best Paper Award
at the Design, Automation and Test Conference (DATE) in 2004.
Piet Wambacq (S’89–M’91) was born in Asse,
Belgium, in 1963. He received the M.Sc. degree in
electrical and mechanical engineering and the Ph.D.
degree from the Katholieke Universiteit Leuven
(K.U. Leuven), Leuven, Belgium, in 1986 and 1996,
respectively.
From 1986 to 1996, he was a Research Assistant at
the ESAT-MICAS Laboratory, K.U. Leuven. Since
1996, he is with IMEC, Leuven, Belgium, working
as a Principal Scientist on design methodologies for
mixed-signal and RF integrated circuits. He is also a
Lecturer at Vrije Universiteit Brussel, Brussels, Belgium. His research inter-
ests are design and computer-aided design of mixed-signal and RF integrated
circuits. He has authored or coauthored two books and more than 100 papers
in edited books, international journals, and conference proceedings. He is the
co-inventor of two patents.
Dr. Wambacq is an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS
AND SYSTEMS—I: REGULAR PAPERS. He is the co-recipient of the Best Paper
Award at the Design, Automation and Test Conference (DATE) in 2002 and
2004. He regularly is a member of the Program Committees of international
conferences (e.g., DATE).
Geert Van der Plas (S’01–M’03) was born in
Merchtem, Belgium, in 1969. He received the M.Sc.
and Ph.D. degrees from the Katholieke Universiteit
Leuven (K.U. Leuven), Leuven, Belgium, in 1992
and 2001, respectively.
From 1992 to 2001, he was a Research Assistant
with the ESAT-MICAS Laboratory of K.U. Leuven,
where he worked in the field of analog modeling and
design automation. In 2002, he was appointed as a
Postdoctoral Research Assistant in the same research
group. Since 2003, he has been with the Design Tech-
nology Division of IMEC, Leuven, Belgium, where he is working on noise cou-
pling in mixed-signal integrated circuits. His current research interests include
deep-submicron signal integrity analysis and design of mixed-signal circuits.
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:36 from IEEE Xplore. Restrictions apply.
305
Stéphane Donnay (M’00) received the M.S. and
Ph.D. degree in electrical engineering from the
Katholieke Universiteit Leuven (K.U. Leuven),
Leuven, Belgium in 1990 and 1998, respectively.
He was a Research Assistant in the ESAT-MICAS
Laboratory of K.U. Leuven from 1990 until 1996,
where he worked in the field of analog and RF
modeling and design automation. In 1997. he joined
IMEC, where he is now a Program Director. His
current research interests include circuit and system
design in very deep submicron technologies, ultra-
low-power radios for sensor networks, system-in-a-package integration of RF
front-ends and the modeling and simulation of substrate noise coupling in mixed-
signal integrated circuits. He has authored or coauthored more than 100 papers in
books, journals and conference proceedings. He is co-editor of Substrate Noise
Coupling in Mixed-Signal ASICs (Norwood, MA: Kluwer, 2003).
Dr. Donnay is a member of the Technical Program Committee of the Euro-
pean Solid-State Circuits Conference (ESSCIRC) since 2001. He was co-recip-
ient of the best paper award at the Design, Automation and Test (DATE) con-
ference in 2002 and 2004.
Georges G. E. Gielen (S’87–M’02–SM’99–F’02)
received the M.Sc. and Ph.D. degrees in electrical
engineering from the Katholieke Universiteit Leuven
(K.U. Leuven), Leuven, Belgium, in 1986 and 1990,
respectively.
In 1990, he was appointed as a Postdoctoral Re-
search Assistant and Visiting Lecturer in the Depart-
ment of Electrical Engineering and Computer Sci-
ence, University of California, Berkeley. From 1991
to 1993, he was a Postdoctoral Research Assistant of
the Belgian National Fund of Scientific Research at
the ESAT Laboratory, K.U. Leuven. In 1993, he was appointed as a tenure Re-
search Associate of the Belgian National Fund of Scientific Research and at the
same time as an Assistant Professor at the K.U. Leuven. In 2000 he promoted to
Full- Time professor at K.U. Leuven. His research interests are in the design
of analog and mixed-signal integrated circuits, and especially in analog and
mixed-signal computer-aided design tools and design automation (modeling,
simulation and symbolic analysis, analog synthesis, analog layout generation,
analog and mixed-signal testing). He is coordinator or partner of several (indus-
trial) research projects in this area. He has authored or coauthored four books
and more than 250 papers in edited books, international journals, and conference
proceedings. He is Editor-in-Chief of the Integration Journal, and a member of
the Editorial Board of the International Journal on Analog Integrated Circuits
and Signal Processing.
Dr. Gielen has been a regular member of the Program Committees of inter-
national conferences (DAC, ICCAD, ISCAS, DATE, CICC...). He received the
1995 Best Paper Award from the International Journal on Circuit Theory and
Applications, and was the 1997 Laureate of the Belgian Royal Academy on
Sciences, Literature, and Arts in the discipline of Engineering. He received the
2000 Alcatel Award from the Belgian National Fund of Scientific Research for
his innovative research in telecommunications. He is a the President of the IEEE
Circuits and Systems (CAS) society for the 2005–2006 term.
Hugo J. De Man (M’81–SM’81–F’86) is Professor
of Electrical Engineering at the Katholieke Univer-
siteit Leuven, (K.U. Leuven), Leuven, Belgium since
1976. In 1975, he was a Visiting Associate Professor
at the University of California, Berkeley, teaching
device physics and integrated circuit design. His
early research was devoted to the development of
mixed-signal, switched capacitor and digital signal
processing (DSP) simulation tools as well as new
topologies for high-speed CMOS circuits. He is Co-
founder of IMEC, where he was Vice-President from
1984–1995, in charge of design methods for DSP and telecom oriented chip
architectures. Since then, he is a Senior Research Fellow of IMEC, working on
design methods for low-power post-PC systems in nanoscale technologies. The
work of his research team at IMEC has lead to many novel tools and methods
in the area of high level synthesis, hardware-software co-design and C++ based
design now available through a number of spin-off companies.
Dr. De Man received the Technical Achievement Award of the IEEE Signal
Processing Society, The Phil Kaufman Award of the EDA Consortium, and the
Golden Jubilee Medal of the IEEE Circuits and Systems Society in 1999. In
2004, he received the lifetime achievement awards, respectively, of the Euro-
pean Design and Automation Association (EDAA) as well as the European Elec-
tronics Industry. He is a member of the Royal Academy of Sciences in Belgium.