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646 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 6, JUNE 2000
Fig. 2. N-channel drain and substrate currents for channel width W = 15 m Fig. 3. P-channel drain and substrate currents for channel width W = 15 m
and channel length L as shown. V = 3:5 V for all measurements. The bias and channel length L as shown. V = 3:5 V for all measurements. For low
and geometry dependence indicates that impact ionization is the primary cause source-gate voltages GIDL is the dominant substrate contribution, for higher
of the observed substrate current. voltages impact ionization current dominates.
near the drain. Some fraction of the carriers in this region will
gain enough energy to become “hot” [9], [10]. When these hot
carriers do eventually scatter, they can dissipate their excess en-
ergy by creating additional, energetic electron-hole pairs, in a
process known as impact ionization. For an NMOS transistor,
the holes created by impact ionization are swept to the substrate,
such that the transistor has current flowing from the drain into
the substrate. In studies addressing the damaging effects of hot
electrons, this substrate current is often examined, because it is
an easily measurable quantity that is correlated to the hot car-
riers of interest. In contrast, the focus of this work is the sub-
strate current itself, since it can lead to fluctuations in bulk po-
tential as it flows through the resistive substrate.
Fig. 2 shows the drain and substrate currents measured on
NMOS transistors with three different channel lengths, as a Fig. 4. Normalized substrate currents for n-channel and p-channel MOS
transistors. The relative n-channel impact ionization current is seen to be at
function of the gate-source voltage . The observed substrate least a factor of ten higher than for the p-channel devices.
current is due to impact ionization over this entire range of bias
conditions. Fig. 3 shows the same currents measured on PMOS
pact-ionization coefficient , which depends on the local elec-
transistors. For these -channel devices, gate-induced drain
tric field
leakage (GIDL) also causes significant substrate current at low
values of . (1)
The proportionality between and is shown in Fig. 4,
for both NMOS and PMOS transistors. The relative level of where and are positive parameters [11]. For long-channel
impact ionization current is seen to exponentially depend on devices, it is then straightforward to relate this electric field to
. At low gate voltages, where the transistors are in deep the applied terminal voltages [8], [12]. However, for smaller
saturation, the impact ionization current is independent of geometries, the channel electric fields in saturation are affected
channel length. At higher gate voltages, the behavior of dif- by velocity saturation, such that carrier behavior depends on the
ferent channel-length devices diverges, reflecting differences in nonlocal electric field [13]. Thus, recent work in this area relies
how the channel electric field evolves as a function of voltage. on Monte Carlo simulations [14], and no robust compact models
It is clear that the relative impact ionization current in our exist to describe impact-ionization currents in submicrometer
PMOSFET’s is about an order of magnitude less than in the MOSFET’s [15].
NMOSFET’s. This lower substrate current, in combination We require a predictive description of impact-ionization
with capacitive shielding from the -well junction, makes substrate current to allow quantitative comparisons to other
the PMOSFET contribution to impact-ionization current in substrate injection mechanisms within the framework of a
the common substrate negligible. Thus, we will model the circuit simulator. As expected from the previous discussion,
impact-ionization component of substrate crosstalk using only existing long-channel substrate current models were not
the -channel substrate current. successful in describing our measured short-channel results.
Simple models have been used to describe the relationship Instead, we fit our measured results to an interpolated empirical
between the drain current and substrate current with an im- function, based on the long channel model, over the entire
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BRIAIRE AND KRISCH: PRINCIPLES OF SUBSTRATE CROSSTALK GENERATION IN CMOS CIRCUITS 647
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648 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 6, JUNE 2000
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BRIAIRE AND KRISCH: PRINCIPLES OF SUBSTRATE CROSSTALK GENERATION IN CMOS CIRCUITS 649
Fig. 9. Simulated substrate current due to impact ionization (solid) and due Fig. 11. Simulated substrate current due to impact ionization (solid) and
to capacitive coupling (dashed) during switching of a single, unloaded CMOS due to capacitive coupling (dashed) during switching of a single inverter.
inverter. The input excitation is a 10-MHz sine wave, as shown in the inset, and The input excitation is a square wave with a 0.2-ns rise time, as shown in
the output voltage is dashed. The device sizes are W =L = 3:6=0:32 and the inset. The output voltage is also shown (dashed). The device sizes are
W =L = 2:66=0:32. W =L = 3:6 m=0:32 m and W =L = 2:66 m=0:32 m, and
100-fF load capacitors are connected from the inverter output to V and from
the inverter output to V .
Fig. 10. The simulated rms substrate current in a single inverter, as a function
of input frequency. The input excitation and device sizes are as shown in Fig. 9. Fig. 12. The simulated rms substrate current in a single inverter, as a function
The rms inverter switching current, i.e., the transient current that flows from of the load capacitance. The input excitation and device sizes are as shown
V to V during switching, is plotted for comparison. The average currents in Fig. 11. Substrate current is dominated by capacitive coupling through the
are also shown, illustrating the net inverter and net substrate current flow during junctions over the range of loads investigated. The rms inverter switching current
a switching cycle. and average currents are also plotted for comparison.
bulk-current. Fig. 9 shows the NFET substrate current due to currents are about an order of magnitude smaller than capaci-
each mechanism as a function of time, for an unloaded inverter tive currents, which are in turn an order of magnitude smaller
driven by a 10-MHz sine-wave input. The resulting impact-ion- than the switching current through the inverter.
ization substrate current is always greater than or equal to zero,
while the capacitive current has larger peak-to-peak fluctua- B. The Influence of Circuit- and Substrate Parasitics
tions, but an average value of zero. We summarize these results So far, we have only described substrate coupling due to cur-
in terms of the root-mean-square (rms) and the average current rent injection from active devices in an ideal inverter. In prac-
over a switching cycle. In Fig. 10, we compare the currents from tice, these injected currents will be shunted to and ground
the two injection mechanisms as a function of input signal fre- through resistive wells and tub-ties, setting up a potential distri-
quency. For low-frequency excitations, impact ionization is seen bution throughout the substrate. It is these voltage fluctuations
to cause the larger rms current. The capacitive coupling current, in the substrate, and not the injected current itself, which couple
which is linearly proportional to frequency, begins to dominate to the sensitive analog transistors and cause crosstalk. Conse-
around 10 MHz. quently, we now focus on substrate voltage, and discuss the role
Similarly, we also simulated substrate injection from an in- that different integrated-circuit parasitics in the injecting circuit
verter as a function of the output load. In this case we applied a play in substrate voltage fluctuations. Both the NFET and PFET
square wave to the input with rise and fall times of about 0.2 ns. bulk currents are included in these simulations, as the PFET cur-
The time response of the substrate currents, for a 100-fF load, is rent can couple to the substrate via the -well to substrate ca-
shown in Fig. 11. The rms and average values of the currents as pacitance.
a function of the load are given in Fig. 12. It is clear from these 1) Substrate- Impedance and the Bond Wire Impedance:
simulations that, for typical internal loads, impact ionization A schematic of the parasitic circuit environment for a single
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650 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 6, JUNE 2000
Fig. 13. Circuit model of a single inverter stage, with the associated substrate- Fig. 14. The substrate voltage (dashed), and the difference between the
and power-supply parasitics that influence substrate injection. substrate voltage and V (solid) that result when the circuit in Fig. 13 is
simulated with the dotted lines taken as short circuits. The input (solid) and
output voltages (dashed) are as shown in the inset. The values of the parasitic
elements are chosen to reflect the values in a large digital circuit. The results
inverter is shown in Fig. 13. For now, we assume that the dotted indicate that V and V are almost equal during switching.
lines in Fig. 13 are solid, such that the substrate node is
resistively connected, via , to the rail of the circuit.
The substrate is also capacitively connected to , through
the capacitance between the metal lines and the substrate, and
more significantly, through all the NMOSFET source junctions
connected to . We previously noted that an individual
FET has a capacitance to the substrate in the range of tens of
fF. If there are such devices, then the total capacitance
that each device sees is already is above 1 nF.
At 1 GHz, which is a typical frequency for switching of
submicrometer MOSFET’s, has an impedance of
less than 1 , such that it is effectively shorted out. There is
also a series resistance, , in this path, due to wiring,
contact resistance and the substrate resistance of the source
diffusion and substrate. Finally, a voltage can develop between
and ground, across the bond wire inductance and the
line resistance . Fig. 15. The substrate voltage (dashed), and the difference between the
substrate voltage and V (solid) that result when the circuit in Fig. 13 is
The substrate voltage that results from simulation of this cir- simulated with the dotted lines taken as open circuits. The input (solid) and
cuit is shown in Fig. 14. We have assumed some typical values output voltages (dashed) are as shown in the inset. The result is that V and
for these parasitic elements, with fF, V have an equivalent high-frequency behavior to the previous case, but V
has additional low-frequency fluctuations, and a nonzero average component.
nF, nF, , , ,
and nH. The difference between and is also
plotted, which reveals strong coupling between and the sub- transmitted to the substrate. Overall, this result suggests that
strate, and substrate fluctuations that are nearly identical to those separate connections of and to ground will not result
on . Therefore, for the parasitic values used in this example, in significant improvements in substrate isolation. While this is
substrate voltage fluctuations are mainly governed by the circuit true for a single inverter, we will describe in Section IV how
switching current and not by the MOSFET substrate current. the low-frequency components can play a significant role in a
2) Separate Connection of the Substrate to the Power complete integrated circuit, such that separate power-supply
Supply: If separate bias connections are used for the and connections are advantageous.
nodes, the dotted lines in Fig. 13 are open circuits and 3) Parasitic Decoupling Capacitance: The discussions in
there will only be capacitive coupling left between and the previous sections are based on a model in which there is a
. To examine this scenario, this modified circuit was low-impedance connection between the substrate and , in
re-simulated with the same parameter values used in Fig. 14. combination with a relatively small current flowing between the
As shown in Fig. 15, is still seen to follow the high-fre- two. The latter assumption is not necessarily true. In addition
quency behavior of , due to coupling via the source diodes. to the fact that there is a large capacitance between and the
The difference between the two node voltages reveals that the substrate, there also is a large capacitance between and all
current at has an additional low-frequency component the -wells combined. Furthermore, the junction capacitance
with a nonzero average, which does not couple to the substrate. between these -wells and the substrate, , can be very
When the substrate was resistively connected to the line, large, due to the large -well area. The combination of these
this small average component of the switching current was three capacitances leads to a parasitic decoupling capacitance
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BRIAIRE AND KRISCH: PRINCIPLES OF SUBSTRATE CROSSTALK GENERATION IN CMOS CIRCUITS 651
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652 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 6, JUNE 2000
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ACKNOWLEDGMENT
The authors would like to thank G. Alers, J. Bude, H.-I. Cong,
P. Davis, R. Gupta, P. Kinget, P. Larsson, S. Martin, and D.
Monroe for their helpful advice, suggestions, and technical dis-
cussions.
J. Briaire received the M.Sc. degree in electrical
engineering at Eindhoven University of Technology,
REFERENCES Eindhoven, The Netherlands, in 1996 . Presently, he
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1993. 1=f noise in the ferromagnet Ni Fe .
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BRIAIRE AND KRISCH: PRINCIPLES OF SUBSTRATE CROSSTALK GENERATION IN CMOS CIRCUITS 653
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