IEEE JOURNAL Ob SOLID-STATE CIRCUITS. VOL. 25. NO. 1.

FEBRUARY 1990 55

An a-Immune, 2-V Supply Voltage SRAM

Using a Polysilicon PMOS Load Cell

Abstract -A SRAM for a supply voltage of as low as 2 V is investigated 11. A PPL CELL:ADVANTAGES
IN DESIGNING
for realizing high-density SRAM's using deep submicrometer devices. The A MEMORY
CELL
key technology for achieving the low-voltage operation is shown to be a
polysilicon PMOS load (PPL) cell. The polysilicon PMOS device is
In this section, the structure, process technology, and
successfully stacked on the bulk MOSFET, using 0.5- pm CMOS technol-
ogy. The investigation emphasizes the soft error rate (SER) and the design of the PPL cell are described.
stability of the cell. The SER of the PPL cell at a supply voltage of 2 V is
comparable to that of the conventional high-resistivity polysilicon load cell A. Polysilicon P M O S Load Cell
at a supply voltage of 5 V. The cell stability is also improved using a PPL
cell, so that the low-voltage operation is assured. Fig. 1 shows a cross section and circuit diagram of the
PPL cell. As shown in the circuit diagram, polysilicon
PMOSFET's are used as the cell-load devices. To attain a
I. INTRODUCTION small cell area, the polysilicon PMOSFET's must be
stacked on the driver MOSFET's. The first polysilicon

A S THE gate length of MOSFET's in static RAM's is layer forms the gate electrodes of the bulk MOSFET's of
scaled down to deep submicrometer dimensions for the cell. The second and t h r d polysilicon layers form the
achieving very high-density SRAM's, the supply voltage gate electrodes and the channel regions of the polysilicon
must be reduced to less than 5 V to avoid hot-carrier PMOSFET's, respectively. The load PMOSFET's can be
degradation and to reduce power dissipation. Therefore, formed without an excessive cell area as compared with the
the low-voltage operation margin of a memory cell is hgh-resistivity polysilicon load cell (hgh-R cell). The over-
becoming increasingly important. lap capacitors between the second polysilicon layer and the
A polysilicon load cell [l] has been generally used for third polysilicon layer (C,), and the second polysilicon
high-density, low-standby-current static RAM's because of layer and the first polysilicon layer ( C l ) , improve the SER
its small cell area and the low leakage current of the of the cell in the retention mode [3]. The total capacitance
polysilicon load. However, the polysilicon load cell is not of the storage node of the memory cell, including the
good enough for low-voltage operation in terms of a-par- overlap capacitors, is about 10 fF.
ticle-induced soft errors and cell stability [2]. Although a Fig. 2 shows the drain current characteristics of the
full CMOS cell operates well at low voltage, its cell area is polysilicon PMOSFET fabricated in the cell. The current
generally too large to realize a high-density static RAM. flowing in the PMOSFET at a gate voltage of 0 V (OFF
We have proposed the polysilicon PMOS load (PPL) cell current) corresponds to the standby current of a SRAM.
to achieve both good low-voltage operation characteristics As the OFF current is less than 0.5 PA, the standby current
and a small cell area [3]. In the PPL cell the polysilicon of the 4-Mbit SRAM using the PPL cell will be 2 pA,
PMOSFET's were successfully stacked on the bulk MOS- which is low enough for battery back-up operation. On the
FET's. This paper describes a 2-V supply voltage SRAM other hand, the current flowing in the PMOSFET at a gate
using the PPL cell. A 4-kbit test array of the PPL cell was voltage of - 2 V means the ON current at a supply voltage
fabricated using 0.5-pm CMOS technology. The soft error of 2 V. The ON current is about 10 PA, which is one-and-
rate (SER) in the operating mode and the stability of the a-half orders of magnitude larger than the OFF current. On
cell were evaluated and found to realize 2-V supply voltage the contrary, the current flowing in the polysilicon load in
operation. the high-R cell is almost the same as the OFF current of the
polysilicon PMOSFET regardless of the supply voltage,
Manuscript received July 20, 1989; revised September 20, 1989. because the resistivity of the load is not changed by the
The authors are with the Central Research Laboratory, Hitach Ltd., supply voltage. The ON current of the polysilicon PMOS-
1-280 Higashikoigakubo, Kokubunji-shi, Tokyo, 185 Japan.
IEEE Log Number 8932219. FET, whch rapidly charges up the high-storage node, is

0018-9200/90/0200-0055$01.00 01990 IEEE

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 56
POLY-SI PMOS POLY-SI PMOS
CHANNEL REGION GATE ELECTRODE
(a)
Fig 1 (a) Cross section and (b) circuit diagram of the PPL cell
8 - 2
GATE VOLTAGE, Vg ( V )
Fig. 2. Drain current characteristics of the polysilicon PMOS fabricated
in the cell.
the key to the 2-V operation of the SRAM, as will be
discussed later.
B. Threshold Voltage Reduction in the PPL Cell
In order to realize a SRAM which operates at a supply
voltage of 2 V or less, keeping the high-storage node
voltage at the v,,
level is important. In a conventional
high-R cell, the threshold voltages of the bulk MOSFET's
had to be high enough to keep the high-storage node at the
V,, level. However, the PPL cell can use a lower threshold
voltage of bulk MOSFET's than the conventional high-R
cell does without degrading data retention characteristics.
The high-storage node voltage (V,) is determined by the
balance of the load current and subthreshold current of the
bulk MOSFET. In the data-retention mode, when the
bit-line voltage is high enough, the subthreshold current of
the transfer MOSFET does not discharge the high-storage
node. However, the subthreshold current of the driver
MOSFET discharges the high-storage node. On the con-
trary, as the voltage of one of the bit lines is almost at
ground level in the write operation, the subthreshold cur-
rent of the transfer MOSFET's in unselected cells dis-
charges the high-storage node. Therefore, the subthreshold
currents of both transfer MOSFET's and driver MOSFET's
play an important role in achieving good data-retention
capability.
Fig. 3 shows the high-storage node voltage as a function
of the threshold voltage of the bulk MOSFET. As the
threshold voltage decreases, the hgh-storage node voltage
decreases because of the subthreshold current increase. In
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 1, FEBRUARY 1990
$4
WORD LINE
POLY-si
BL (b)
c=2v
Load Current 1
Subthresholdl
Current )!
0.3 0.4 0.5 0.6
BULK MOSFET
THRESHOLD VOLTAGE ( V )
Fig. 3. High-storage node voltage as a function of threshold voltage (10
nA, W=10 pm) of bulk MOSFET in the retention mode. The solid
line shows the hgh-storage node voltage of the PPL cell, and the
broken line shows that in the high-R cell. The threshold voltage of the
bulk MOSFET's in the high-R cell must be the voltage shown by the
open circle, while that in the PPL cell can be lowered as shown by
the closed circle.
the case of the PPL cell, the high-storage node voltage
remains almost at the V,, level for a threshold voltage of
more than 0.4 V. However, the high-storage node voltage
of the hgh-R cell starts decreasing at a threshold voltage
of 0.6 V. This is because the ON current of the polysilicon
PMOSFET in the PPL cell is larger than the current of the
polysilicon load in the high-R cell. As a result, the thresh-
old voltage of the bulk MOSFET can be lowered using the
PPL cell, keeping the same data-retention characteristics.
In Fig. 3, the closed circle indicates the minimum thresh-
old voltage of bulk MOSFET's in the PPL cell, and the
open circle indicates the minimum threshold voltage in the
hgh-resistivity load cell to attain 2-V data retention. As
shown in this figure, the threshold voltage of the bulk
MOSFET's in the PPL cell can be decreased by 0.2 V
without sacrificing the data-retention capability.
The threshold voltages of both the transfer MOSFET's
and driver MOSFET's in the PPL cell can be lowered from
the viewpoint of the data-retention capability. However,
only the threshold voltage of the transfer MOSFET's was
lowered to keep the static stability of the cell, as will be
discussed in Section V. The lower threshold voltage of the
transfer MOSFET's was realized by using an additional
mask and channel implantation of B on the driver MOS-
 ISHIBASHI et U / : AN a- IMMIJNE, 2-v SUPPLY VOLTAGE SRAM 51

TABLE I
OF 0.5-pm CMOS TECHNOLOGY
SUMMARY Lcr
Technology Triple-poly. Double Metal
Bulk MOSFET
Gate Length 0.6 pm (Leff=0.5 p m )
Gate Oxide 15 nm
Isolation 0.6 pm
Polysilicon PMOSFET
Channel Lengthlwidth 1.6/0.6 pm
Gale Oxide 25 nm
Memory Cell Size 25.38 pm2
1 - 1

Select s i g n a l

Fig. 5. Sensing circuit for the 4-kbit test array.

tors, a sense amplifier, and a data-out buffer. The array

consists of 64 columns and 64 rows and has a 4 K x 1
organization.
Fig. 5 shows the sensing-circuit diagram of the 4-kbit
test array. In the cell array, the bit-line load devices are
PMOSFET's, therefore the bit-line voltages are kept at the
V,, level. Since no current flows from the high-storage
node of the cell to the bit line in a read operation, the
degradation of the SER and stability of the cell can be
excluded by using the PMOSFET's bit-line loads [4]. The
sensing amplifier is a current mirror type, which is gener-
ally used in SRAM's. The supply voltage of the sensing
amplifier is supplied separately, and the voltage supplied is
larger than the bit-line voltage in order to amplify the
bit-line differential voltage at the V,, level.

Fig. 4. Optical micrograph of the 4-kbit test array of the PPL cell. IV. SOFTERRORRATEIN THE OPERATION
MODE

When the supply voltage and cycle time are reduced,

FET. The dose of the implantation was 4X1Ol2 cmp2, soft errors induced by a particles become a major problem
which resulted in about a 0.2-V threshold voltage differ- in the high-R cell [5]. This is because the high-storage node
ence between driver MOSFET's and transfer MOSFET's. voltage cannot be charged in the short cycle time after the
write operation due to the high-load resistivity. In contrast,
the SER in the PPL cell can be decreased, because the ON
current of the PMOSFET charges the high-storage node
111. 4-KBIT TESTARRAY
very quickly after the write operation.
A 0.5-pm CMOS technology was used to obtain a small The high-storage node voltage in the cell becomes yC-yi
cell area of 25 pm'. This technology is summarized in after the write operation, where vi is the threshold voltage
Table I. The channel length and width of the polysilicon of the transfer MOSFET that includes the body effect. The
PMOSFET are 1.6 and 0.6 pm, respectively. The OFF time t , , for charging the hgh-storage node from y,-vi
current of the polysilicon PMOSFET can be decreased to V,, is described as follows:
when the channel length is larger [3]. However, the channel
length was chosen so that the cell area of the PPL cell
would not be larger.
Fig. 4 shows an optical micrograph of the 4-kbit test
array of the PPL cell fabricated by using the 0.5-pm
CMOS technology. The upper right-hand side of the figure where I , is the current flowing in the load device in the
shows the 4-kbit array of the PPL cell, while the other cell, and C, is the node capacitance. The average interval
portion shows the peripheral circuit, including shift resis- time t , for word-line selection is described as follows:

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 58 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 1,FEBRUARY 1990

PPL
2.0v
2.4V
n
2.8V

U
>
cv
10-2t >
In

10-
1 0 0 pCi Am241

Incident Angle 75'

I

5.0V'
.

".,'.
10-5 10-4 10-3 io-2 10-1 100
INTERVAL TIME (s)
Fig. 6 . SER of the PPL cell and the high-R cell as a function of the v1 (VI
interval time. The corresponding interval time of a 4-Mbit S U M is
denoted by the circle.

where N is the number of memory cells per chip, M is the

number of memory cells per word line, and tcycleis the
operating cycle time. The condition for charging the high-
storage node to V,, is expressed as follows:

"ch-
When a 64-cell/word-line 4-Mbit SRAM operates at a
cycle time of 70 ns, the average interval time calculated by
(2) is 4.6 ms. In the high-R cell, t,h is larger than 100 ms
because the current flowing in the load resistor is as low as
1X A. The charge-up time is 20 times longer than the
average interval time of a 4-Mbit SRAM, so the high-stor-
age node voltage stays at around Vcc-v;. However, the
time t,, for the PPL cell becomes about 1 ms even for a V,,
of 2 V due to the current flowing in the PMOSFET, as
shown in Fig. 2. Consequently, the condition in ( 3 ) is
satisfied. Thus, the high-storage node in the PPL cell is
quickly charged up to the V,, level. For t h s reason, the
SER of the PPL cell in the operation mode should be
much lower than that of the high-R cell.
Measured SERs of the PPL and hgh-R cells that are
irradiated by 100-pCi 241 Am are given in Fig. 6 as a
function of the average interval time. The SER of the
high-R cell was measured at a 1-Mbit SRAM that was
fabricated using 0.8-pm CMOS technology [l]. The SER of
the PPL cell was measured at the 4-kbit array, described in
Section 111. The radiation angle was set at 75", whch is the
worst condition for the SER [6]. In both cells, as the
interval time increases, the SER decreases. This means that
the high-storage node voltage is charged up through the
load devices to improve the SER. As shown in Fig. 6, the
SER of the PPL cell starts decreasing at a shorter interval
time than that of the high-R cell for any supply voltage.
This means that the polysilicon PMOSFET in the PPL cell
rapidly charges up the high-storage node. It can be clearly
seen in the figure that the SER of the PPL cell, even at a
supply voltage of 2 V, is almost the same as that of the
high-R cell at a supply voltage of 5 V. Therefore, as far as
minimizing the SER in the operation mode is concerned,
the supply voltage can be reduced to 2 V by using the PPL
cell.
(3)
v1 (VI
(b)
Fig. 7. Simulated transfer curves in the read operation of the (a) PPL
cell, and (b) high-R cell.
v. ELECTRICAL
STABILITY AT LOWERVOLTAGE
To obtain SRAM's that can operate at a supply voltage
of 2 V, not only the SER but also the cell stability should
be improved. In this section, cell stability is discussed:
first, static stability, and second, dynamic stability.
A . Static Stability
Fig. 7 shows simulated transfer curves [7] in the read
operation of the PPL cell and high-R cell. In the simula-
tion, a 10-percent threshold-voltage variation and a 15-
percent channel-width variation for the bulk MOSFET's
were assumed, so some asymmetry is seen in these curves.
The memory cell ratio R is expressed by the following
equation:
(4)
where W, and W, are the channel widths of the transfer
and driver MOSFET, and L , and L , are the channel
lengths of the transfer and driver MOSFET, respectively.
The ratio R is 3 in t h s simulation.
The crosspoints of these curves indicate the stable points
of the low-storage node and high-storage node. Therefore,
to keep the data in the memory cell, three crosspoints are
needed. Those are: data ONE storage, data ZERO storage,
and the quasi-stable point.

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 ISHIBASHI et u l : AN a- IMMUNE, 2-v SUPPLY VOLTAGE SRAM 59

-h

> 5 -
W
' ' '

(3 4 -
a

w 2 -

I
I 0 1 2 3 4 5
WORD LINE VOLTAGE ( V I
5
Y 3 Fig. 9. High-storage node voltage of the cell as a function of word-line
voltage. The solid line indicates the high-storage node voltage of the
PPL cell. The broken line indicates that of the high-R cell. The dotted
% 2 region. whose boundary is shown at the bottom line, indicates the
a high-storage node voltages that cause data destruction in both kinds of
5
0
1 cells. If the high-storage node voltage is in the dotted region, the data
will change in the next read operation.
>
'0 10 20 30 40 50
is low, as shown in Fig. 8(b), the stored data change during
TIME (ns) the read operation. The high-storage node voltage must be
(b) high enough so that the stored data does not change even
Fig. 8. Simulated waveforms of the high-R cell when the data is at the worst operating condition, even in the existence of
(a) unchanged, and (b) changed. bulk MOSFET imbalance.
The high-storage node voltage becomes lowest just after
When a read operation is performed, the low node the write operation. So the worst operating condition means
-
voltage is about 0.2 0.4 V, depending on the supply the read operation just after the write operation. The
voltage. So the subthreshold current flows in the driver lowest hgh-storage node voltage just after the write opera-
MOSFET, whose drain is connected to the high-storage tion is described as follows:
node. There is no current from the hgh-storage node to
the bit line through the transfer MOSFET, because the bit VH= V,, - + AV (5)
line is kept at the y c level. In the case of the hgh-resistiv- where AV is the voltage that is charged through the cell
ity load cell at supply voltages of 3 and 4 V, the high-stor- load devices. AV is then described as follows:
age node voltage is reduced to Vcc-K;. This is because the
current flowing in the polysilicon load is less than the
subthreshold current. Additionally, in the case of a supply
voltage of 2 V, there are only two crosspoints; that is, the
cell cannot store data when the supply voltage is 2 V. By As discussed in Section 11, the vi of the PPL cell can be
contrast, in the case of the PPL cell, since the ON current set 0.2 V lower than that of the high-R cell, so the yi in
of the polysilicon PMOSFET is larger than that of the ( 5 ) in the PPL cell is 0.2 V smaller than that of the high-R
subthreshold current of the driver MOSFET, the cross- cell. In addition, the current flowing through the PMOS-
points of the curves are almost at the V,, levels, even with FET ( I , in (6)) charges the high-storage node of the cell,
a supply voltage of 2 V. There are three crosspoints at any so that AV in the PPL cell is larger than that in the high-R
supply voltage. This means that in the PPL cell, the cell. For these two reasons, the V, in ( 5 ) is higher in PPL
memory cell can store data at any supply voltage. As a cells than in high-R cells, resulting in a high stability.
result, from the viewpoint of static stability, the PPL cell The hgh-storage node voltage obtained from ( 5 ) just
can store data even for a supply voltage of down to 2 V. before the read operation is presented as shown in Fig. 9
as a function of the word-line voltage. The solid line
B. Dynamic Stability indicates the high-storage node voltage of the PPL cell,
and the broken line indicates that of the high-R cell. The
Fig. 8 shows the simulated waveforms of word line V,, dotted region, whose boundary is shown as the bottom
hgh-storage node voltage V,, and low-storage node volt- solid line, indicates the high-storage node voltage that
age V,, respectively, in a read operation. In t h s simula- induces data destruction in both cells during the following
tion, the variation of the threshold voltage and the channel read operation. As shown in Fig. 9, the hgh-storage node
width of the bulk MOSFET's are the same as those for the voltage in the PPL cell is higher than that in the high-R
simulation in Fig. 7. In Fig. 8(a), the stored data are not cell. The data change starts below the supply voltages
destroyed during the read operation, while the stored data corresponding to the crosspoints of the high-node voltages
are destroyed in Fig. 8(b). The difference between Fig. 8(a) and dotted region. Therefore, the data of the high-R cell
and (b) is the high-storage node voltage just before the should start changing at a supply voltage of 2.5 V, while
read operation. When the initial hgh-storage node voltage the data of the PPL cell should do so at a supply voltage of

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 60
h
tcycle= 1OOns 1,
8olkPL
I
II
I Tech. Pupers, Feb. 1987, pp. 260-261.
1I High-R
0 6o
0 I
2ou
2 SC-20, pp. 383-390, Feb. 1985.
0 [5] S. Murakami, K. Ichnose, K. Anami, and S. Kayano, “Improvement
0 1.5 2.0
POWER SUPPLY VOLTAGE (V)
Fig. 10. Fail bit count as a function of the power supply voltage.
2 V. This means that the PPL cell is more stable electri-
cally, and the minimum supply voltage can be lowered
to 2 v.
The measured bit failure count is gven in Fig. 10 as a
function of the power-supply voltage in the high-R cell
and PPL cell. In this experiment, the read cycle and write
cycle are conducted alternatively. This case gives the low-
est high-storage node voltage. The minimum supply volt-
age of the PPL cell is about 2 V, while that of the high-R
cell is about 2.5 V, which corresponds to the simulated
data as shown in Fig. 9.
Moreover, if V, can be charged to V,, during the write
operation by using an improved polysilicon PMOSFET,
the electrical stability must be identical to that of the full
CMOS SRAM cell. One approach to improve the polysili-
con PMOSFET would be rapid thermal annealing (RTA)
[3]. Hence it is concluded that the PPL cell is a promising
candidate for future high-density SRAMs that will operate
at low-power supply voltages of less than 5 V, because of
the advantages of the full CMOS cell’s SER and stability
and the high-R cell’s small cell area.
VI. CONCLUSION
The SER and stability of the PPL cell at a supply
voltage of as low as 2 V were investigated. Since the
current flowing in the polysilicon PMOSFET in the PPL
cell rapidly charges up the high-storage node of the cell,
the SER of a PPL cell in the operation mode at a supply
voltage of 2 V is as low as that of a hgh-R cell at a supply
voltage of 5 V. Because the ON current flowing in the
polysilicon PMOSFET enhances static stability, the SRAM
with a PPL cell operates well at a supply voltage of 2 V,
keeping good data-retention characteristics. Therefore the
PPL cell is a promising candidate for future high-density
S U M ’ S , which will need the supply-voltage decrease.
ACKNOWLEDGMENT
The authors would like to thank K. Sasaki, T.
Hashimoto, N. Hashimoto, T. Nishida, A. Shmizu, K.
Ueda, and F. Kojima for their many helpful discussions.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 25, NO. 1, FEBRUARY 1990
REFERENCES
[l] 0. Minato, et al., “A 42 ns 1 Mb CMOS SRAM,” in ISSCC Dlg.
. - [2] F. J. List, “The static noise margin of SRAM cells,” in ESSCIRC
I Dig. Tech. Papers, Se?: 1986, pp. 16-18.
[3] Y. Yamanaka et al., A 25 pm’, new poly-Si PMOS load (PPL)
1
\ SRAM cell having excellent soft error immunity,” in IEDM Tech.
4 Dig., Dec. 1988, fp. 48-51.
[4] B. Chappell, S. E. Schuster, and G. A. Sai-Halasz, “Stability and
SER analvsis of static RAM cells.” IEEE J . Solid-State Circuits, vol.
2.5 3.0 of soft error rate in MOS SRAMs,” in S-vmp. VLSI Circuits Dig.
Tech. Papers, Aug. 1988, pp. 57-58.
[6] T. Toyabe et U / . , “A soft error rate model for MOS dynamic
RAM’S,” IEEE Trans. Electron Devices, vol. ED-29, pp. 732-737,
Apr. 1982.
[7] J. Lohstroh, E. Seevinck, and J. D. Groot, “Worst-case static noise
margin criteria for logic circuits and their mathematical equivalence,”
IEEE J . Sohd-State Circuits, vol. SC-18, pp. 803-807, Dec. 1983.
Koichiro Ishihashi (M86) received the B.S. de-
gree from Sopha University, Tokyo, Japan, in
1980. He received the M.S. and Ph.D. degrees in
engineering from the Tokyo Institute of Technol-
ogy, Tokyo, Japan, in 1982 and 1985, respec-
tively.
In 1985 he joined the Central Research Labo-
ratory, Hitachi Ltd., Tokyo, Japan, where he has
been engaged in the research and development of
Si static RAM’S.
Dr. Ishibash is a member of the Japan Society
of Applied Physics and the Institute of Electronics, Information and
Communication Engineers of Japan.
Toshiaki Yamanaka (M’87) received the B.S. and
M.S. degrees in electrical engineering from the
University of Electro-Communications, Tokyo,
Japan, in 1980 and 1982, respectively.
In 1982 he joined the Central Research Labo-
ratory, Hitachi Ltd., Tokyo, Japan, where he has
been working on the research and development
of hgh-density CMOS static RAM processes.
Mr. Yamanaka is a member of the Japan
Society of Applied Physics.
Katsuhiro Shimohigashi (M77) received the
B.S., M.S.. and Ph.D. degrees in electrical engi-
neering from Kyushu University, Fukuoka,
Japan, in 1969, 1971, and 1988, respectively.
He joined the Central Research Laboratory,
Hitachi Ltd., Tokyo, Japan, in 1971. Since 1973
he has been working on the circuit and device
design of dynamic MOS memories. He was a
Visiting Research Scholar at Stanford Univer-
sity, Stanford, CA, from September 1977 to
August 1978, where he worked on submicrome-
ter device physics and the modeling of VLSI devices. Currently he is
supervising the development of CMOS/BiCMOS devices and circuits for
advanced logic/memory applications, nonvolatile memories, and low-
temperature devices for future LSI’s.
Dr. Shimohigashi is a member of the Institute of Electronics, Informa-
tion and Communication Engineers of Japan.