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D. Ho1, K. Iniewski2, S. Kasnavi2, A. Ivanov1, S. Natarajan3
1 2 3
Dept. of Elec. and Comp. Engineering Dept. of Elec. and Comp. Engineering Emerging Memory Technologies Inc.
University of British Columbia University of Alberta, Ottawa, Canada
Vancouver, Canada Edmonton, Canada
Abstract—This paper presents a comparative study of technology to find an optimal design for ultra-low power
leakage reduction techniques applied to a 90nm 6T SRAM to wireless sensor applications primarily from a power
find an optimal design for ultra-low power wireless sensor perspective. The techniques include the use of multi-VT
applications. A 4-Kb SRAM implemented with the proposed transistors, scaling supply voltage, sizing above minimum
techniques has a leakage as low as 26.5nA in the idle mode, a
gate length, and implementing sleep transistors. The leakage
189X improvement over a memory without applying such
techniques. reduction ability and the corresponding sacrifice in SNM of
each technique are compared. Section II examines major
sources of leakage present in the 6T cell. Section III
I. INTRODUCTION describes the impact of the supply voltage and the transistor
The emerging Wireless Sensor Network technologies are threshold values on leakage. Section IV analyzes the effect
facilitating novel applications in health monitoring, of transistor sizing on leakage. Section V investigates the
industrial monitoring and security surveillance. The small effectiveness of sleep transistors in leakage reduction,
physical dimensions of wireless sensor nodes often restrict followed by a comparison and conclusion in Section VI.
the energy source to a small battery. The limited energy
II. 6T SRAM LEAKAGE ANALYSIS
consumption requirement demands for ultra-low power
sensing, processing and communication. Ultra-low power The standard 6T SRAM cell is shown inside the box in
approaches at the device, circuit, system and network level Figure 1, with M2 and M4 normally connected to ground
have been proposed for reliable implementations of sensor rather than to Msleep (Msleep included only in Section V
networks [1-3]. simulations). M5 and M6 are the access transistors for read
SRAM, being a key component of the processing system and write operations. M1-4 form a cross coupled inverter
of sensor nodes, has to satisfy the low-power requirement as with positive feedback to statically retain data.
well. As feature size shrinks, the key component of power
consumption will be leakage [4]. In the past 5 years, there
has been significant effort to find ways to reduce leakage,
amongst them are supply voltage scaling [5, 6], idle mode
implementation [7-9], and body biasing [5, 10]. While the
existing solutions provide good leakage reduction, they
mostly target microprocessor cache, with circuit
performance being a critical parameter to be optimized. This
limits the extent to which leakage reduction techniques can
be applied, rendering them ineffective for the ultra-low
power domain. In a sensor node, there are two modes of
operation, namely data processing and idle. Since the
memory spends almost its entire operating time in the idle
mode, it is critical to vastly reduce leakage while retaining Figure 1 The standard 6T SRAM cell with the addition of a
data. With the primary function of retaining data and speed
sleep transistor.
being only a secondary requirement, good cell stability,
reflected by a high Static Noise Margin (SNM), becomes a
To clarify the leakage sources in the cell, assume V1 and
critical design objective for a SRAM used in a wireless
V2 are biased to a logic zero and a logic one respectively.
sensor application. Thus M1 and M4 are turned off. M1 and M4 give rise to the
This paper compares leakage reduction techniques leakage currents IS1 and IS2 respectively. IS1 and IS2 form the
applied to the 6T SRAM cell implemented in a 90nm supply leakage as they drain charges from the supply grid.
L eakag e (p A )
Bitline Lk. (LVT)
small voltage difference between the drain and source of 100 Supply Lk. (SVT)
SNM (mV)
300
250
that can corrupt the data stored in the cell. For SNM 200
HVT
simulations, noise sources are added to the inputs of both 150
SVT
100
inverters with the worst case polarity as shown in Figure 2 50 LVT
30
Supply voltage scaling is a well known method to
25
reduce the power consumption of a circuit. The leakage is
reduced due to smaller voltage differences between the 20
gates are at logic zero. The sleep transistor has leakage ISleep, Sleep Transistor Width (um)
which is the total leakage of a column. In the idle mode, the (b)
sleep transistor’s control input VC is low, disconnecting the Figure 5 Leakage for different numbers of cells per column
memory cells from ground. When the cell is active, VC is using one NMOS sleep transistor: (a) Supply leakage, (b)
high, providing a path that connects the cells to ground with Bitline leakage.
ideally low resistance. The choice of an NMOS instead of a
PMOS as the sleep transistor is due to the fact that both 200
supply and bitline leakage current flow through the pull- 180
160
down network. 140 1 Cell
Figures 5a and 5b show respectively the dependencies of
SNM (mV)
120 2 Cells
100
the supply and the bitline leakage on the size of a high 80
4 Cells
30
1 Cell for a larger size memory. Future work may investigate the
25
2 Cells performance impact of leakage reduction techniques so that
20 4 Cells a power-performance tradeoff can be made.
15 16 Cells
10 ACKNOWLEDGMENT
5
0
The authors gratefully acknowledge Alicja Pierzynska
1 2 3 4 5 6 7 8 9 10 for providing insightful comments on the paper.
Sleep Transistor Width (um)
(b) REFERENCES
[1] B. Otis, Y. H. Chee, and J. Rabaey, “A 400µW RX, 1.6mW TX
Figure 7 Leakage reduction using 2 NMOS sleep transistors Super-Regenerative Transceiver for Wireless Sensor Networks”,
Proceedings of the International Solid-State Circuits Conference
for different numbers of cells per column: (a) Supply (ISSCC), San Francisco, CA, February 2005, pp. 396 – 397.
leakage, (b) Bitline leakage. [2] K. Iniewski, C. Siu, S. Kilambi, S.Khan, B. Crowley, P. Mercier,
and C. Schlegel, “Ultra-low power circuit design for smart sensor
160
network applications”, International Conf on Information and
Communication Technology (ICICT), invited paper, Dec 2005.
140
120
[3] V. Ekanayake, C. Kelly, R. Manohar, “An Ultra-Low-Power
1 Cell
100
Processor for Sensor Networks,” Proceedings of the 11th International
SNM (mV)