LIBRARY ieee;

USE ieee.std_logic_1164.all ;

ENTITY main IS

PORT ( clk : IN STD_LOGIC ;

zone : IN STD_LOGIC_VECTOR(3 downto 0) ;

arm : in std_logic;

led : out STD_LOGIC;

led1: out std_logic );

END main ;

ARCHITECTURE behv OF main IS

TYPE State_type IS
(DISARMED,ARMED,SET1,EXIT_DELAY,ENTRY_DELAY,SET2) ;

SIGNAL state : State_type ;

signal ledstate: std_logic;

signal led1state: std_logic;

BEGIN

PROCESS

variable count: integer range 0 to 5;

BEGIN

wait until clk = '1';

CASE state IS

WHEN DISARMED =>

ledstate <= '0';

IF arm = '1' THEN

 state <= EXIT_DELAY;

ELSE

state <= DISARMED;

END IF ;

WHEN EXIT_DElAY =>

led1state <= '1';

IF arm = '0' THEN

state <= DISARMED;

ElSIF arm = '1' THEN

IF (count >= 5) THEN

count := 0;

ELSE

count := count + 1;

END IF;

ELSE

state <= EXIT_DELAY;

END IF;

WHEN ARMED =>

IF arm = '0' THEN

state <= DISARMED;

ELSIF

ZONE > "0000" THEN

state <= SET1;

ELSE

state <= ARMED;

END IF ;
 WHEN SET1 =>

IF zone = "0001" THEN

state <= ENTRY_DELAY;

ELSE

state <= SET2;

END IF ;

WHEN ENTRY_DELAY =>

led1state <= '1';

IF arm = '0' THEN

state <= DISARMED;

ElSIF arm = '1' THEN

ElSIF clk = '1' THEN

IF (count >= 5) THEN

count := 0;

ELSE

count := count + 1;

END IF;

ELSE

state <= ENTRY_DELAY;

END IF;

WHEN SET2 =>

ledstate <= '1';

IF arm = '0' THEN

state <= DISARMED;

ELSE
 state <= SET2;

END IF;

END CASE ;

END PROCESS ;

led <= ledstate;

led1 <= led1state;

END behv ;

This is the code which I tried to do. I could compile it successfully but there is a
basic mistake so I am not able to simulate it at all. In the whole design all other
bits and pieces have been given by the tutor. Just MAIN, this is controller we
have to design it.

We have been given the FSM and ASM for the same system to design the
controller.

The reason the clock has been changed is because –

The crystal on the hardware is 25 MHz which gives 40ns time period but for the
KEYPAD scanning we require 10 to 20 ms scanning period. We are using simpad
to do simulation using keyad.

Hence the clock frequency comes down to 200Hz that gives time period of 5ms.

So for simulating we can give pin value over 7 to 8 clock cycles to read the scan
and know the pin.

Now for 10 seconds delay what I thought the counter is the best thing to
consider.

But I couldn’t merge it properly.

The code will give you some idea and I am sending the brief having FSM and ASM
for the projects.

I am using ALTERA QAURTUS II design software.

We add all the files in project and then create symbols and attach them to get
the whole circuit.

Thanking you in anticipation.

 s im p a d

s im in [ 3 . . 0 ] IN P U T s i m i n [ r3o . w. 0s ] [ 3 . . 0 ]
VC C
c o ls [ 2 . .0 ]

c o ls [ 2 . .0 ] O U TPU T

in s t 6
O U T PU T k ey w r

O U T P U T c lk o u t

fsm 3a
key pad3
k e y w rP I N O K O U T P U T P IN O K
c lo c k g e n L F c lk g e n
r o w s [ 3k .e. y0 ]v a l [ 3 . . 0 ] d a ta [3 ..0 ]
c lk in IN P U T c l k c i nl k o u t c l k _ ci nl k 2 0 0 c lk 2 0 0 key wr
VC C
c o ls [ 2 . . 0 ]
in s t 2
in s t 3
in s t in s t 4

m a in

c lk le d O U T P U T le d

zo n e [3 ..0 ] IN P U T z o n e [ 3l e . d. 01 ] O U T P U T le d 1
VC C
a rm

in s t 7

This is normal block diagram for the Intermediate level alarm system.