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V.S.B.

COLLEGE OF ENGINEERING TECHNICAL CAMPUS,


COIMBATORE
Department of Ee!tron"!# an$ Comm%n"!at"on En&"neer"n&
A!a$em"! 'ear( )*+,-)*+. /ODD Seme#ter0
LESSON PLAN
Class: III Semester B.E. ECE
Name of Subject: EC 2203-Digital Electronics
Name of Facult member: S.Suguna
!ecture
No.
Date
"lanne#
$o"ic%s& to be co'ere# $eac(ing )i#s
UNIT I MINIMI1ATION TECHNI2UES 3 LOGIC GATES
* 0+.0,.*
3
Intro#uction- Boolean .ostulates / !a0s- De-
1organ2s $(eorem
Blac3boar#4!CD
2 0+.0,.*
3
.rinci"le of Dualit- Boolean E5"ression-
1inimi6ation of Boolean E5"ression.
Blac3boar#4!CD
3 *0.0,.*
3
1interm- 1a5term- S7.- .7S. Blac3boar#4!CD
8 *2.0,.*
3
9-1a" 1inimi6ation- Don2t Care Con#itions-
:uine-1cClus3e 1et(o# of 1inimi6ation.
Blac3boar#4!CD
; *3.0,.*
3
!ogic <ates- Im"lementation of !ogic Functions
using <ates.
Blac3boar#4!CD
= *=.0,.*
3
N)ND-N7> Im"lementations. Blac3boar#4!CD
, *,.0,.*
3
1ulti !e'el <ate Im"lementations- 1ulti 7ut"ut
<ate Im"lementations.
Blac3boar#4!CD
? *?.0,.*
3
$$! !ogic. Blac3boar#4!CD
+ *+.0,.*
3
C17S !ogic- $ristate <ates. Blac3boar#4!CD
*0 23.0,.*
3
>e'ision Blac3boar#4!CD
UNIT II COMBINATIONAL CIRCUITS
** 28.0,.*
3
Intro#uction- Design .roce#ure- @alf )##er- Full
)##er.
Blac3boar#4!CD
*2 30.0,.*
3
@alf Subtractor- Full Subtractor- .arallel binar
)##er / Subtractor.
Blac3boar#4!CD
*3 3*.0,.*
3
Fast )##er- Carr !oo3-) @ea# )##er. Blac3boar#4!CD
*8 03.0?.*
3
Serial )##er4Subtractor- BCD )##er. Blac3boar#4!CD
*; 0=.0?.*
3
Binar 1ulti"lier4 Di'i#er. Blac3boar#4!CD
*= 0=.0?.*
3
1ulti"le5er4Demulti"le5er. Blac3boar#4!CD
*, 0?.0?.*
3
Deco#er- Enco#er. Blac3boar#4!CD
*? *3.0?.* .arit C(ec3er- .arit <enerator. Blac3boar#4!CD
Form No. AC 05a Rev.No. 00 Effective Date: 08/07/2013
3
*+ *3.0?.*
3
Co#e Con'erters. Blac3boar#4!CD
20 *=.0?.*
3
1agnitu#e Com"arator- >e'ision Blac3boar#4!CD
UNIT III SE2UENTIAL CIRCUITS
2* 20.0?.*
3
Intro#uction- !atc(es- Fli"-Flo"s. Blac3boar#4!CD
22 2*.0?.*
3
1aster Sla'e- C(aracteristic $able /EAuation
)""lication $able.
Blac3boar#4!CD
23 22.0?.*
3
E#ge $riggering- !e'el $riggering. Blac3boar#4!CD
28 28.0?.*
3
>eali6ation of 7ne Fli" Flo" using ot(er Fli" Flo"s. Blac3boar#4!CD
2; 2,.0?.*
3
Serial )##er4Subtractor- )snc(ronous >i""le
Counter- )snc(ronous B"4Do0n Counter.
Blac3boar#4!CD
2= 2,.0?.*
3
Snc(ronous Counters- Snc(ronous B"4Do0n
Counter- .rogrammable Counters.
Blac3boar#4!CD
2, 30.0?.*
3
Design of Snc(ronous Counters %State Diagram-
State $able- State 1inimi6ation- State )ssignment-
E5citation $able- 1a"s Circuit Im"lementation&.
Blac3boar#4!CD
2? 3*.0?.*
3
1o#ulo-n Counter- >egisters- S(ift >egisters-
Bni'ersal S(ift >egisters.
Blac3boar#4!CD
2+ 03.0+.*
3
S(ift >egister Counters- >ing Counter- S(ift
Counter.
Blac3boar#4!CD
30 0;.0+.*
3
SeAuence <enerators- >e'ision. Blac3boar#4!CD
UNIT IV MEMOR' DEVICES
3* *0.0+.*
3
Intro#uction- Classification of 1emories. Blac3boar#4!CD
32 **.0+.*
3
>71- >71 7rgani6ation. Blac3boar#4!CD
33 *2.0+.*
3
.>71- E.>71- EE.>71- E).>71. Blac3boar#4!CD
38 *8.0+.*
3
>)1- >)1 7rgani6ation- Crite->ea# 7"eration. Blac3boar#4!CD
3; *,.0+.*
3
1emor Ccle- $iming Ca'eforms. Blac3boar#4!CD
3= *,.0+.*
3
1emor Deco#ing- 1emor E5"ansion. Blac3boar#4!CD
3, *+.0+.*
3
Static- Bi"olar- 17SFE$- Dnamic >)1 Cell. Blac3boar#4!CD
3? 20.0+.*
3
.!D- .!)- .)!. Blac3boar#4!CD
3+ 2*.0+.*
3
F.<)- Im"lementation of Combinational !ogic
Circuits using >71- .!)- .)!.
Blac3boar#4!CD
Form No. AC 05a Rev.No. 00 Effective Date: 08/07/2013
80 28.0+.*
3
>e'ision Blac3boar#4!CD
UNIT V S'NCHRONOUS 3 AS'NCHRONOUS SE2UENTIAL CIRCUITS
8* 2,.0+.*
3
Intro#uction- Snc(ronous SeAuential Circuit
%<eneral 1o#el- Classification&.
Blac3boar#4!CD
82 2?.0+.*
3
Design of Snc(ronous SeAuential Circuit. Blac3boar#4!CD
83 0*.*0.*
3
Bse of )lgorit(mic State 1ac(ine. Blac3boar#4!CD
88 03.*0.*
3
)nalsis of Snc(ronous SeAuential Circuits. Blac3boar#4!CD
8; 08.*0.*
3
)snc(ronous SeAuential Circuit D Design of
Fun#amental 1o#e- .ulse 1o#e Circuits.
Blac3boar#4!CD
8= 0;.*0.*
3
Incom"letel S"ecifie# State 1ac(ines. Blac3boar#4!CD
8, 0?.*0.*
3
.roblems in )snc(ronous Circuit. Blac3boar#4!CD
8? 0+.*0.*
3
Design of @a6ar# Free S0itc(ing Circuits. Blac3boar#4!CD
8+ **.*0.*
3
Design of Combinational / SeAuential Circuits
using Eerilog.
Blac3boar#4!CD
;0 *2.*0.*
3
>e'ision. Blac3boar#4!CD
TE4T BOO5S(
*. 1.1orris 1ano- Digital Design- 3
r#
E#ition- .rentice @all of In#ia- .earson E#ucation-
2003 .
2. S.Sali'a(anan an# S. )ri'a6(agan- Digital Circuts an# Design-3
r#
E#ition- Ei3as
.ublis(ing @ouse-200=.
REFERENCES(
*. Fo(n F.Ca3erl- Digital Design- 8
t(
E#ition- .earson 200=.
2. Cilliam @. <ot(mann- Digital Electronics- 2
n#
E#ition- .@I-*+?2.
.re"are# b: S.Suguna )""ro'e# b: >.Sun#ararajan
Date: Date:
Form No. AC 05a Rev.No. 00 Effective Date: 08/07/2013