FPGA Climatic

Oana Valentina Rusu

Advisor: Lecturer eng. Adrian-Vasile Duka PhD

Petru Maior niversit! o"
#irgu Mures$ Ro%ania
Contents
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'ntroduction
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Pro(ect overvie)
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*DL Design
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+o"t)are Design
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,onclusions
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De%o
Introduction
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't is a cli%ate control -lat"or% .ased on /P0A.
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Re-laces the t)o devices used to control the
heating and cooling s!ste% 1 the ther%ostat and
the A, re%ote control 2
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All availa.le co%%ands and %enus are sho)n
on a screen.
Why this project?
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Learn so%ething ne).
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Discover the usage and ca-a.ilities o" an /P0A
starting "ro% si%-le to co%-le3 -ro(ects.
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Designing an use"ul -lat"or% "or ever!da! use.
System Specification
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Allo)s to read te%-erature4
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,urrent te%-erature is dis-la!ed on a 5seg%ent
dis-la!4
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Allo)s to control the heating and cooling
s!ste%s4
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't has an i%-roved user inter"ace 1 it dis-la!s an
interactive %enu on the screen 24
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,o%%ands are sent through a re%ote control4
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#he controlling algorith%s and the %enu design
)ere i%-le%ented on an integrated so"t core4
Project overview
Project overview
#his -ro(ect is divided in t)o -arts:
HDL Design
System architecture:
AHB_Lite_SoC - the SoC based on the AHB-Lite protocol (implements the control logic, user
interface etc.
IRReceiver - decodes the remote control signal and encodes the desired !eys"
PmodTMP - con#erts and reads the temperature from the temperature sensor"
temp_7seg_display - displays the temperature on a $ segment display"
PWM % generates the &'( control signal"
PmodTP modu!e
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6-)ire digital ther%o%eter and
ther%ostat4
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78 .it resolution
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'n our case : dis-la!s -ositive
te%-eratures$ )ith one deci%al -art 4
PmodTP timing diagrams
PodTmp State achine
I" "eceiver odu!e
& Reads the signal "ro% a #+OP9:6: 6: k*; 'R receiver4
& Decodes the re%ote control signals 1 <=, "or%at 2 and assigns the%
a 9-.i! ke!4
Key ame Address Code !ata Code "al#e Assig$ed
)n*)ff ++++,+++,,,,+,,, ,,,++,++ $ (,+++
A ++++,+++,,,,+,,, ,,,+++++ + (,,,+
B ++++,+++,,,,+,,, ,,,++++, - (,,+,
C ++++,+++,,,,+,,, ,,,++,+, . (,,++
) ++++,+++,,,,+,,, ,,,,,+,, / (,+,+
0p ++++,+++,,,,+,,, ,,,,,+,+ 1 (,++,
2o3n ++++,+++,,,,+,,, ,,,,,,,, 4 (,+,,
Left ++++,+++,,,,+,,, ,,,,+,,, 5 (+,,,
6ight ++++,+++,,,,+,,, ,,,,,,,+ 7 (+,,+
I" "eceiver State achine
PW odu!e
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generates a P>M signal "or the cooling
s!ste%4
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dut! c!cle de-ends on the value received
"ro% the P'D controller 1 e.g. 68 -?@A
dut! c!cle $ B6 C 7@@A dut! -c!cle24
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7 %s -eriod4
Temp#$seg#disp!ay modu!e
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+ho)s the current te%-erature on a 5seg%ent
dis-la!4
%in&'cd !ogic
(H%) Lite Protoco!
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't is used in +o, designs as the on-chi- .us.
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't is a su.set o" A*D -rotocol de"ined in the
AMDA 6 standard4
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't si%-li"ies the design "or a .us )ith a single
%aster4
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Main co%-onents: %aster co%-onent $ slave
co%-onents $ address decoder $ %ulti-le3or4
The (H%)Lite SoC
(H%)Lite aster* Corte+ , Design Start
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Dased on a si%-li"ied version o" the ARM ,orte3
M@ -rocessor4
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't has a <V', 'nterru-t controller )ith 7B
'nterru-t lines4
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+u--orts 7B and 68 .it instructions4
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Microcontroller-oriented -rocessor "or M, and
+o, a--lications4
(H%)Lite S!aves - (H%&CT"L
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AHB2CTRL - slave %odule )hich receives data
"ro% the %aster %odule :
always @(posedge HCLK or negedge HRESETn)
begin
if(!HRESETn)
rCTRL <= 8b!!!!"!!!!#
else if(rHSEL $ rH%R&TE $ rHTR'(S)*+)
rCTRL <= H%,'T')-.!+#
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and assigns it to the out-ut )ires:
assign CTRL = rCTRL#
(H%)Lite S!aves ) (H%I.P/T
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AHBINPUTS - slave %odule )hich reads data "ro%
in-uts :
always @(posedge HCLK/ negedge HRESETn)
begin
if(!HRESETn)
inp01"da1a <= *23!!!!#
else
inp01"da1a <= &(45TS&(#
end
& and it sends to the %aster:
assign HR,'T')*6.!+=inp01"da1a#
& 'n-ut data:

irEFre%ote C irE signal$

re%oteFcodeG6:@H - data$

te%-eratureG5:@H
(H%)Lite S!aves - 01( Contro!!er
Modi"ications:
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'nvisi.le cursor4
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,usto% cursor re-ositioning C "or
clearFscreen12 "unction4
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Modi"!ing screen tiles and color te3t4
c!ear#screen23 function
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>hen the 76
th
A+,'' character is dis-la!ed -I cursor
re-ositioned to initial -osition 1@$@24
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#he vga %e%or! )ill .e re)ritten )ith e%-t!
characters4
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,ursor re-ositioning a"ter dis-la!ing again the 76
th

character4
8oid 9lear"s9reen():
prin1f(;<9;/*=)#
for(i=!#i<8#i>>)
prin1f(;


;)#
prin1f(;<9;/*=)#
?
Software Design
#he so"t)are co%-onent is )ritten in A<+' , and ARM
Asse%.l!.
#he -ro(ect itsel" contains 9 "iles:
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,M@-D+.h C contains the -eri-heral %e%or! %a- 4
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retarget.c C contains the i%-le%entation o" "unctions
used to dis-la! the te3t4
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c%@dsas%.s C contains instructions )hich handle the
interru-t vector4
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M!Progra%.c - contains the code used "or %enu dis-la!
and control algorith%s4
Interrupt Contro!!er 243
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<V', 1 <ested Vector 'nterru-t ,ontroller 2
)hich is tightl! cou-led )ith -rocessor core4
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7B -rioriti;ed interru-ts su--orted4
Interrupt Contro!!er 2&3
,orte3 M@ Design +tart su--orts seven e3ce-tion
t!-es:
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Reset C Processor reset in-ut is asserted4
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*ard/ault e3ce-tion C can .e an! t!-e o" "ault
occurred 1e.g. .us "ault or unde"ined instruction24
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<M' C <on-Maska.le 'nterru-t occurred4
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'RJ C 'RJ 'nterru-ts occurred4
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Pend+V C +o"t)are 0enerated interru-t4
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+V,all C e3ecution o" a +V, instruction4
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+!s#ick C internal s!ste% ti%er caused interru-t4
0ector Ta'!e
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#he vector ta.le contains the *andler vector
addresses and initial value o" the Main +tack
Pointer 1M+P2. 'n the case o" an e3ce-tion the
core )ill read the vector handler address "or the
e3ce-tion "ro% the vector ta.le and .ranches to
the handler.
Interrupt Hand!ing
& 'n our -ro(ect design )e use the 'RJ received "ro% the re%ote
control .! -ressing the O<KO// .utton 1 '<P#+F'RJ 24
& se"ul to initiali;e and turn onKo"" the control s!ste%4
& 'n the Vector #a.le its handler has address @39:4
& >e have to )rite a handler and an '+R 1interru-t service routine2 in
, "or this interru-t line4
Assembly :
&np01"Handler 4R@C
EA4@RT &np01"Handler
&B4@RT &(45T"&SR
45SH :R!/LR?
CL &(45T"&SR
4@4 :R!/4C?
E(,4
C :
8oid &(45T"&SR():D?
Heating (!gorithm
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#hree +tates:

Active heating C turns the heating s!ste% on i"

current te%-erature is lo)er than the set-oint4

Pause heating C turns the heating s!ste% o"" and

(u%-s to active state i" current te%-erature is lo)er
)ith 3 degrees than the set-oint4

=3it heating C returns to %ain %enu4

Heating (!gorithm
Coo!ing (!gorithm
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#hree +tates:

Active coolingC turns the cooling s!ste% on i"

current te%-erature is higher than the set-oint4

Pause heating C turns the cooling s!ste% o"" and

(u%-s to active state i" current te%-erature is higher
)ith 3 degrees than the set-oint4

=3it heating C returns to %ain %enu4

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#he cooling algorith% includes a P'D controller.
Coo!ing a!gorithm
PID Contro!!er
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a control loo- "eed.ack %echanis% )idel! used
in industrial control s!ste%s4
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used to control "an s-eed 4
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P'D coe""icients )ere deter%ined e3-eri%entall!
1 %anual tuning 24
Wiring scheme
Conc!usions 243
#he "ollo)ing goals have .een achieved:
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Learning Verilog .asics4
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'ntegrate ARM ,orte3 M@ Design +tart 'P core
and creating a custo% A*D-Lite +o, s!ste%
)ith -eri-herals4
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Develo-ing other Verilog s-eci"ic %odules 1 "or
te%-erature %easuring and dis-la!$ 'R decode$
P>M signal generation24
Conc!usions 2&3
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Develo-ing clearFscreen12 "unction "or ,
so"t)are4
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,reating the coolingKheating algorith%s in ,4
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*andling re%ote control 'RJ in Verilog and
Asse%.l!4
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Develo-ing interactive user inter"ace in ,4
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*ard)are co%-onent design and asse%.ling 4
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Other i%-rove%ents 4
5uture considerations
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,ontrolling the -lat"or% "ro% distance using an
internet connection 1 )e )ill use a ras-.err! -i
as a )e. server$ it )ould .e %ore e""icient 24
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=3tend the design to 'ntelligent *ouse Pro(ect.
Demo
Than6 you for your interest7