04 Combinational 6up PDF

13/03/15
1
COMBINATIONAL LOGIC
13/03/14 1 TUD/EE ET4293 digic - 12/13 - NvdM - 04 Combinational
Combi nat i onal Logi c - Out l i ne
Conventional Static CMOS basic principles
Complementary static CMOS
Complex Logic Gates
VTC, Delay and Sizing
Ratioed logic
Pass transistor logic
Dynamic CMOS gates
Combi nat i onal vs. Sequent i al Logi c
Logic
Circuit
Out In
Logic
Circuit
Out
In
(a) Combinational
Output = f (In)
(b) Sequential
Output = f (In, History)
State
(flipflops)
6.2
Complex Logic Gates
Compl ement ar y St at i c CMOS
B
A
example
PUN
V
DD
In1
In2
In3
F = G
In
1
PMOS Only
generic
Pull-Down
Network
Pull-Up
Network
Conduction of PDN and PUN must be mutually
exclusive (Why?)
Pull-up network (PUN) and pull-down network (PDN)
are dual
A B PDN
V
SS
1
In
2
In
3
NMOS Only
6.2.1
2-i nput Nand/Nor
B A
B
A
Y = A AND B
Y A OR B
A
B
A B
Y A AND B
Y = A OR B
13/03/15
2
Mut ual Ex c l usi ve PDN and PUN
V
DD
A
C
B
C B A
P
D
N
P
U
N Out
0 0 0 ? 1 1
0 0 1 ? 1 1
0 1 0 ? 1 1
0 1 1 0 ? 0
Out = (AB + C)
PDN Off
PUN On
V
SS
Out
A
C
B
0 1 1 0 ? 0
1 0 0 0 ? 0
1 0 1 0 ? 0
1 1 0 0 ? 0
1 1 1 0 ? 0
PUN Off
PDN On
For all Complementary Static CMOS Gates, either
the PUN or the PDN is conducting, but never both.
Compl ement ar y St at i c CMOS (2)
Conduction of PUN and PDN must be mutually
exclusive
PUN is dual (complement) network of PDN
series parallel
nmos pmos
Complementary gate is inverting
No static power dissipation
Very robust
Wide noise margin
Need 2N transistors for N-input gate
pull-up
NMOS vs. PMOS, pul l -dow n vs. pul l -up
Out = V
DD
Out = ? V
DD
V
Tn
PMOS is better pull-up
NMOS is better pull-down
pull-down
Out = 0
Out = ?
|V
Tp
|
Bad I dea
IN OUT
Exercise: Determine logic function
Determine V
out
for V
in
= V
DD
and V
in
= V
SS
Why is this a bad circuit?
Highest output voltage of NMOS is
V
GS
- V
Tn
= V
DD
- V
Tn
An 1 on NMOS gate can produce a strong 0 at the drain, but not a
strong 1
Lowest output voltage of PMOS is
V
DD
+ V
GS
- V
Tp
= |V
Tp
|
(with V
GS
V < 0 for PMOS)
CMOS Gat e i s I nver t i ng
Assume full-swing inputs (high = V
DD
, low = V
SS
)
(with V
GS
, V
Tp
< 0 for PMOS)
An 0 on PMOS gate can produce a strong 1 at the drain, but not a
strong 0
Need NMOS for pull-down, PMOS for pull-up
A 1 at input can pull-down, 0 at input can pull-up
Inverting behavior
For a non-inverting Complementary CMOS
Gate, you can only use 2 inverting gates
How van we construct an arbitrary combinational
logic network in general, using NMOS and PMOS
transistors (using Complementary static CMOS)?
Y (A BC)D E l
I mpl ement at i on of
Combi nat i onal Logi c
Remember: only inverting gates available
Y = (A + BC)D Example:
Ex. 6.2
13/03/15
3
Example:
Remember: only inverting gates available
Logic depth: number of gates in longest path DELAY
I mpl ement at i on of
Combi nat i onal Logi c
Y = (A + BC)D
C
B
&
& Y
> 1
{TPS}: Can this be improved? If so, how?
# transistors ? logic depth ? 16 5
A
D
I mpr oved Gat e Level I mpl ement at i on
Using DeMorgan BC A BC A . = +
Y = (A + BC)D
C
B
&
A
&
D
Y
> 1
BC
{TPS}: Can this be further improved?
# transistors
Logic depth
?
?
14
3
B
&
&
& A
C
D
FY
BC A.
B C
Compl ex CMOS Logi c Gat es
Easy to synthesize complex gates
Restriction to basic NAND, NOR etc.
not necessary
A
D
D
B
A
C
Y = (A + BC)D
# transistors: 8
Logic depth: 1
Using tree representation of
Boolean function
Operator with branches for
operands
How t o Synt hesi ze Compl ex Gat es
A i ll l t k
( )D BC A F + = Y = (A + BC)D
F
AND
Y
As a series-parallel network
PUN PDN
Parallel
Parallel Series
OR
AND
Series
OR
AND A
B C
D
Y = (A + BC)D
Compl ex Gat e Synt hesi s Ex ampl e
B C
OR
A
Y = (A + (BC))D
D
Y
AND
D
PUN PDN
Parallel
Parallel Series
OR
AND
Series
AND
B C
B
C
A
A
D Recipe
Write Y = f(inputs)
Decompose f in
tree form
Realize tree
branches
according to table
at bottom-left
Use inverted inputs
if necessary
And-Or -I nver t Gat e
Dual PMOS
pull-up network
V
out
V
DD
C
B
2
B
1
A
3
A
2
A
1
&
&
>
1
C
3
C
2
C
1
B
2
B
1
A
3
A
2
A
1
C
3
C
2
C
1
&
13/03/15
4
And-Or -I nver t Ex ampl e
A
B
C
C
Y
A
B
A B C Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
ABC
From a Truth-Table: take 0-outputs
A
C
B
C
A
B
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
ABC
ABC
Y = ABC + ABC
A, B to be created with extra
inverters (or by restructuring
previous circuits)
And-Or -I nver t I mpr ovement
C C
A
B
C
C
Y
A
B
C
A
B C
Y
A
B
A
B
A
B
Y = ABC + ABC
A
B
A
B
Y = (AB + AB)C
12 transistors 10 transistors
2-level logic minimization: boolean algebra technique
CMOS Compl ex Gat e Si zi ng
A
D
B C
D
Y = (A + BC)D
Function of gate
independent of
transistor sizes: ratio-
less
But current-drive
capability (timing)
B
A
C
capability (timing)
depends on transistor
sizes
Worst-case current-
drive depends on
number of transistors
in series
3 trans. in
series
2 trans. in
series
CMOS Compl ex Gat e Si zi ng
Assume all transistors will have mininum length L
Determine W
n
for PDN transistor of inverter that
would give the desired drive strength
For each transistor in PDN of complex gate do the
following:
following:
Determine the length l of the longest PDN chain in
which it participates
Set W = l W
n
Repeat this procedure for PUN, using W
p
for PUN
transistor of inverter.
Gat e Si zi ng
2
1
A
B
B
A
2
2
2
2
2
W/L ratios
what are the W/L of 2-input NAND for the
same drive strength?
0-th order calculation
Gat e Si zi ng
Y = A (B+C)+D
A
B
C 6
6
3
A
B
4
4
13/03/14 24
A
D
B
D
C
1
2
2 2
6
B
A
1
1
24 TUD/EE ET4293 digic - 12/13 - NvdM - 04 Combinational
13/03/15
5
Ex er c i se
C
C
2
C
1
B
2
B
1
A
3
A
2
A
1
Dual PMOS
pull-up network
V
out
V
DD
C
3
C
2
C
1
B
2
B
1
A
3
A
2
A
1
&
&
&
>
1
(a)
C
3
A
3
Perform gate sizing of (a) for nominal drive strength equal to
that of min size inverter, assume PU/PD = 3
Determine PUN of (b)
Perform gate sizing of (b) for same drive strength (same
PU/PD)
Compare sum of gate areas in (a) and (b). Note: area ~ width
Exercise:
(b)
Avoi d Lar ge Fan-I n
N
C linear in N
C
R linear in N
Delay RC quadratic in N
T i t Si i
13/03/14 26 TUD/EE ET4293 digic - 1011 - NvdM - 04 Combinational
N
C
R
Empirical
Delay = a
1
FI + a
2
FI
2
+ a
3
FO
-Transistor Sizing
-Progressive Transistor Sizing
-Input Re-Ordering
-Logic Restructuring
Dat a-Dependent Ti mi ng
L
C
t
PHL
= 0.69R
N
C
L
t
PLH
= 0.69R
P
C
L
You should be able to
identify the transistor paths
that charge or discharge C
L
,
and calculate resulting RC
delay model, including
effects of wires and fan-out
L
C
t
PHL
= 0.69(R
N
2)C
L
Series connection
t
PLH
= 0.69R
p
C
L
One input goes low
t
PLH
= 0.69(R
p
/2)C
L
Two inputs go low,
parallel connection
2
nd
Or der Ef f ec t s
Much more to say about performance of static
gates
Simulator can give accurate answer
Understanding needed to make design decisions
13/03/14
Data-dependent VTC
Data-dependent Timing
Dat a-dependent VTC: 2nd or der ef f ec t s
Cases II
Case I
Charge at int
Body effect in M
2
Short-circuit currents
{TPS}:
Explain VTC difference between I and II
Dat a-dependent Ti mi ng
A=1, B=: need to charge int
A=, B=1: int does not need to be charged
A=, B=: twice the pull-up strength
{TPS}:
Explain differences in t
pLH
13/03/15
6
13/03/14
LOGI CAL EFFORT
Combi nat i onal Pat h Si zi ng f or Ti mi ng
Given: C
L
, S
1
Given: C
L
, S
1
Determine S
2
, S
3
, S
4
to minimize delay
We know how to optimally size string of inverters:
make equal stage delays
{TPS}: What is different in comparison to string of inverters?
Answer:
- Delay of unloaded gate differs from delay of unloaded inverter
- For same transistor sizes, amount of output current differs
Rec ap: I nver t er Del ay
S
+
-
V
s
delay
S: relative size of inverter
S
2S
+
V
s
C
ext
C
t
S: relative size of inverter
C
g
S C
g
S C
ext
R
0
/S
V
s
-
s
R
0
, C
g
, C
g
: output res, input cap and output cap of min size inverter
C
ext
Rec ap: I nver t er Del ay
C
g
S C
g
S C
ext
R
0
/S
V
s
R
0
, C
g
, C
g
: output res, input cap and output cap of min size inverter
( )
in
ext
g po po
g in
in
ext
po
g
ext
g
ext g p
C
C
f C R t with
f
t
SC C with
C
C
t
SC
C
C R
C S C
S
R
t
= = |
.
|
\
|
+ =
=
|
|
.
|
\
|
+ =
|
|
.
|
\
|
+ =
+ =
0
0
0
1
1 1
t
p0
: Delay of unloaded inverter, independent of sizing
I nver t er Del ay Summar y
R
0
Equivalent output resistance of min size inverter
( )
in
ext
g po po ext g p
C
C
f C R t with
f
t C S C
S
R
t = = |
.
|
\
|
+ = + = , 1
0
0

f d + = 1
In units of t
p0
R
0
Equivalent output resistance of min size inverter
C
g
Input cap of min size inverter
C
0
=C
g
Drain (and Miller) cap of min size inverter
S Size of inverter (relative to min inverter)
f electrical effort ratio between C
load
and C
in
ratio of drain cap to gate cap
t
p0
intrinsic delay - delay of unloaded inverter
t
p0
~ 20 ps for a 250 nm process, t
p0
~ 5 ps for a 45 nm process
d normalized delay = t
p
/t
po
S
1
S
2
+
-
V
s
delay
S
i
: relative sizes of inverters
C
load
S
3
S
4
Path delay is minimized if all stage delays are equal
For string of inverters:
when ratio of load cap over input cap is identical for each stage
If C
g
= input cap of inverter with size 1 (minimum size):
inv
load
g
g
in
g
C S
C
S
S
S
S
S
S
C S
C S
C
C S
4 3
4
2
3
1
2
1
2 2
= = = = =
13/03/15
7
Logi c al Ef f or t Met hodol ogy
f d
inv
+ = 1
Inverter delay:
Gate delay:
Logical Effort Methodology Definitions:
p parasitic delay
ratio of intrinsic delay compared to inverter
h p gf p d
gate
+ = + =
In units of t
p0
ratio of output cap for same drive strength
g logical effort
how much more load the gate creates
ratio of input cap for same drive strength
h gate effort, h = gf
[Logical Effort Designing Fast CMOS Circuits, Sutherland, Sproul, Harris]
Beware: compared to most texts, incl. Sutherland,
Rabaey swaps definition of f and h
I nt r i nsi c , Par asi t i c Del ay
p parasitic delay - ratio of
intrinsic delay
compared to inverter
p is ratio of output
capacitances if gate is
sized for identical drive
strength
VDD
A B
A
F
VDD
A
A
F
1
2 2 2
2
strength
p
nand
is (2+2+2)/(2+1) = 2
p=1 p=2
B 2
Inverter 2-inputNAND
gf p d
gate
+ =
Logi c al Ef f or t
g logical effort: how
much load a gate
provides relative to
inverter for same drive
strength
g ratio of input cap (per
pin) if gate is sized for
VDD
A B
A
F
VDD
A
A
F
1
2 2 2
2
pin) if gate is sized for
identical drive strength
g
nand
is (2+2)/(2+1) = 4/3
g=1 g=4/3
B 2
Inverter 2-inputNAND
gf p d
gate
+ =
Logi c al Ef f or t
B
A
A B
F
V
DD
V
DD
A B
A
F
V
DD
A
A
F
1
2 2 2
2
1 1
4
4
B 2
1 1
Inverter 2-input NAND 2-input NOR
p=1, g=1 p=2, g=4/3 p=?, g=?
p ratio of intrinsic delay compared to inverter
g logical effort ratio of inp. cap for same strength
p, g independent of sizing, only topology of gate
p=2, g=5/3
Del ay vs Fan-Out
N
o
r
m
a
l
i
z
e
d

d
e
l
a
y

(
d
)
g = 1
p = 1
d = 1+f/
g = 4/3
p = 2
d = 2+(4/3)f/
effort delay
inverter
2-nand
&
gf p d
gate
+ =
Fan-out (f)
1 2 3 4 5 6 7
&
&
&
d
nand
f
Mul t i st age Net w or k s
Stage effort: h
i
= g
i
f
i
( )
=
+ =
N
i
i i i
f g p Delay
1
Normalized w.r.t. unit delay,
assume = 1
Path electrical effort: F = f
1
f
2
f
N
= C
out
/C
in
Path logical effort: G = g
1
g
2
g
N
Path effort: H = GF
Path delay D = Ed
i
= Ep
i
+ Eh
i
13/03/15
8
Opt i mum Ef f or t per St age
H h
N
=
-
When each stage bears the same effort, optimal effort h
*
:
N
H h =
-
larger fanout for simpler stages
( ) P NH p f g D
N
i i i
+ = + =
/ 1
Minimum path delay

Effective fanout of each stage:
i i
g h f
-
=
Stage efforts: g
1
f
1
= g
2
f
2
= = g
N
f
N
= h
S
1
= 1, C
L
= 36.45
g
1
=1 g
2
=4/3 g
3
=5/3 g
4
=1 G = Hg
i
= 20/9
f = S f =S /S f =S /S f =36 45/S F = Hf = 36 45
f
1
= S
2
f
2
=S
3
/S
2
f
3
=S
4
/S
3
f
4
=36.45/S
4
F = Hf
i
= 36.45
H = FG = 81
f
1
g
1
=3 S
2
= 3
f
2
g
2
= 3 S
3
= 27/4 = 6.75
f
3
g
3
= 3 S
4
= 12.15
3 81
4
= = =
-
N
H h
S
1
= 1, C
L
= 36.45
f
1
g
1
=3 S
2
=3 f
2
g
2
= 3 S
3
= 27/4 = 6.75 f
3
g
3
= 3 S
4
= 12.15
INV NAND NOR INV
Width of N: 1 3x3/2 = 4.5 3x6.75/5 = 4.05 3x12.15/3=12.15
Width of P: 2 3x3/2 = 4.5 3x4x6.75/5 = 16.2 3x2x12.15/3 = 24.3
Nrmlzd C
in
1 9 / 3 = 3 20.25 / 3 = 6.75 36.45 / 3 = 12.15
f
1
= 3 f
2
= 3/g
2
f
3
= 3/g
3
f
4
= 3
C
L
=
36.45 C
in
Logi c al Ef f or t - Summar y
Numerical logical effort characterizes gates
Inverters and NAND2 best for driving large caps
NANDs are faster than NORs in CMOS
Extension needed (see book) for branching
Simplistic delay model
Neglects input rise time effects
Interconnect
Iteration required in designs with wire
Maximum speed only
Not minimum area/power for constrained delay
13/03/14
DYNAMI C POWER
DI SSI PATI ON
Dynami c Pow er Di ssi pat i on
Power = Energy/transition Transition rate
= C
L
V
DD
2
f
01
= C
L
V
DD
2
f p
01
= C
switched
V
DD
2
f
-Transistor Sizing
- Physical capacitance
-Input and output rise/fall times
- Short-circuit power
-Threshold and temperature
13/03/14
Power dissipation is data dependent
depends on the switching probability p
01
Switched capacitance C
switched
= p
01
C
L
= o C
L
(o is called the switching activity)
p
- Leakage power
-Switching activity
13/03/15
9
Tr ansi t i on Pr obabi l i t y
p
A=1
= p
A
: given probability of value of signal A being 1 in any clock cycle
p
A=0
= p
A
: given probability of value of signal A being 0 in any clock cycle
Note the prime (for inversion of signal)
Transition probability:
Probability of 1 to 0 or 0 to 1 transition at clock edge: o = p
A
(1-p
A
) = p
A
p
A
I mpac t of Logi c Func t i on
A B Out
0 0 1
0 1 1
Example: Static 2-input NAND gate
Assume signal probabilities
p
A=1
= 1/2
p
B=1
= 1/2
Then transition probability
13/03/14
1 0 1
1 1 0
o = p
01
= p
Out=0
x p
Out=1
= 1/4 x 3/4 = 3/16
o
NAND
= 3/16
If inputs switch every cycle
NOR gate yields similar result
I mpac t of Logi c Func t i on
A B Out
0 0 0
0 1 1
Example: Static 2-input XOR Gate
Assume signal probabilities
p
A=1
= 1/2
p
B=1
= 1/2
Th t iti b bilit
13/03/14
1 0 1
1 1 0
p
01
= p
Out=0
x p
Out=1
= 1/2 x 1/2 = 1/4
P
01
= 1/4
If inputs switch in every cycle
Si gnal and Tr ansi t i on Pr obabi l i t i es
OR Gat e
0 1
0 1 0 1
A
B
0 1 1 1 A OR B
p
A
: Probability of A being 1
p
B
: Probability of B being 1
Probability of Output being 0: (1-p
A
)(1-p
B
)
Probability of Output being 1: (1-(1-p
A
)(1-p
B
))
Transition probability: o=(1-p
A
)(1-p
B
)(1-(1-p
A
)(1-p
B
))
Si gnal and Tr ansi t i on Pr obabi l i t i es
AND Gat e
0 1
0 1 0 1
A
B
0 0 0 1 A AND B
p
A
: Probability of A being 1
p
B
: Probability of B being 1
Probability of Output being 0: (1-p
A
)(1-p
B
)
Probability of Output being 1: p
A
p
B
Transition probability: o= (1-p
A
)(1-p
B
)p
A
p
B
)
Tr ansi t i on Pr obabi l i t i es f or Basi c
Gat es
A = p
01
AND (1 - p
A
p
B
)p
A
p
B
As a function of the input probabilities
13/03/14
OR (1 - p
A
)(1 - p
B
)(1 - (1 - p
A
)(1 - p
B
))
XOR (1 - (p
A
+p
B
2p
A
p
B
))(p
A
+ p
B
2p
A
p
B
)
Activity for static CMOS gates: o = p
0
p
1
Because of symmetry: AND NAND, OR NOR
13/03/15
10
Eval uat i ng Pow er Di ssi pat i on of Compl ex
Logi c
Simple idea: start from inputs and propagate
signal probabilities to outputs
0.1
0.5
0.9
0.1
0.045
0.99 0.989
p
in1
p
y
= 0.9 x 0.5 x 0.1= 0.045
o=0.045x(1-0.045) = 0.043
y
13/03/14
But:
Reconvergent fanout
Feedback and temporal/spatial correlations
0.1
0.5
0.5
0.25
o=0.0099
Rec onver gent Fanout (Spat i al
Cor r el at i on)
Inputs to gate can be interdependent (correlated)
no reconvergence reconvergent
reconvergence
13/03/14
p
Z
= 1- p
A
. p(X|A) = 1
Becomes complex and intractable real fast
p
Z
= 1-p
x
p
B
=1-(1-p
A
)p
B
p
Z
= 1-(1-p
A
)p
A
?
NO!
p
Z
= 1
Must use conditional probabilities
probability that X=1 given that A=1
Gl i t c hi ng i n St at i c CMOS
ABC 101 000
Analysis so far did not include timing effects
13/03/14
X
Z
Gate Delay
The result is correct,
but extra power is dissipated
Glitch
Also known as dynamic hazards:
A single input change causing
multiple changes in the output
Ex ampl e: Chai n of NAND Gat es
1
Out
1
Out
2
Out
3
Out
4
Out
5
3.0
Out
2
Out
6
13/03/14
0 200 400 600
0.0
1.0
2.0
Time (ps)
Out
8
Out
6
2
Out
1
Out
3
Out
7
Out
5
V
o
l
t
a
g
e

(
V
)
What Causes Gl i t c hes?
A,B
A
B
D
C
X
Z
Y
A,B
13/03/14
C,D
X
Y
Z
C,D
X
Y
Z
Uneven arrival times of input signals of gate due to
unbalanced delay paths
Solution: balancing delay paths!
Compl i ment ar y CMOS Gat es - Summar y
Full rail-to-rail swing; high noise margins
Logic levels not dependent upon the relative device
sizes; ratioless
Always a path to Vdd or Gnd in steady state; low
output impedance
output impedance
Extremely high input resistance; nearly zero steady-
state input current
No direct path steady state between power and
ground; no static power dissipation
Need 2N transistors for N-input gate
13/03/15
11
13/03/14
RATI OED LOGI C
Reduced area
Reduced capacitances
Increased V
OL
Reduced noise margins
Static dissipation
Pseudo NMOS Rat i oed Logi c
Static dissipation
6.2.2
PDN
Rat i oed Logi c V
OL
Comput at i on
I
Dn
(linear) = I
Dp
(saturation)
( ) ( )
|
|
.
|
\
|
=
|
|
.
|
\
|

2 2
2 2
DSAT
DSAT Tp DD p
OL
OL Tn DD n
V
V V V k
V
V V V k
Ignore quadratic terms (they are relatively small)
Exercise: verify these
assumptions/steps
Ignore quadratic terms (they are relatively small)
( ) ( )
DSAT Tp DD p OL Tn DD n
V V V k V V V k ~
Ignore, because approximately equal
DSAT
n n
p p
DSAT
n
p
OL
V
W
W
V
k
k
V
~ ~
Size V
OL
[V] Power [W] t
pLH
[ps]
4 0.693 564 14
2 0.273 298 56
1 0.133 160 123
Performance of a pseudo-NMOS inverter
0.5 0.064 80 268
0.25 0.031 41 569
M1 M2
Differential Cascode Voltage Switch Logic (DCVSL)
Rail-to-rail swing
No static dissipation
Rationed
V
SS
PDN
Out Out
A
A
B
PDN1
V
SS
PDN
PDN2
B
Cross-over currents
Wiring
65 TUD/EE ET4293 digic - 12/13 - NvdM - 04 Combinational 13/03/14
PASS TRANSI STOR LOGI C
PASS GATE LOGI C
13/03/15
12
Pass Tr ansi st or Logi c
Save area, capacitances
Need complementary inputs
(extra inverters)
AB F =
A
B
B
0
But remember:
5 combinational 12 TUD/EE ET1205 EC/GS 0506 - NvdM 09-May-06
PMOS is better pull-up
pull-up
NMOS vs. PMOS, pul l -down vs. pul l -up
NMOS is better pull-down
pull-down
6.2.3
Save area, capacitances
Need complementary inputs
(might mean extra inverters)
Reduced V
OH
, noise margins
( ) ( ) ( )
f OH f T DD OH
V V V V | | 2 2 + + =
AB F =
A
B
B
0
Static dissipation in subsequent static
inverter/buffer
( ) ( ) ( )
f OH f Tno DD OH
V V V V | | 2 2 + + =
{TPS}: Why is there static dissipation in

next conventional gate?
Disadvantages (and advantages) may be reduced by
complementary pass gates (NMOS + PMOS parallel)
Out
VDD
In
x
3.0
In
Out
VDD
In
x
Level restoring circuit
13/03/14 TUD/EE ET4293 digic - 12/13 - NvdM - 04 Combinational 69
0 0.5 1 1.5 2
0.0
1.0
2.0
Time [ns]
V
o
lt
a
g
e
[
V
]
x
Out
In
Out
VSS Level restoring circuit
Rail-to-rail swing
Rationed use with care
Increased capacitance
69
Ex er c i se
Discuss what happens when you connect the output
of a single pass-transistor (not a pass-gate) to the
input of another pass-transistor stage (i.e. the gate
of another pass-transistor). Why should you never
use such a circuit?
B
A
B
C
Pass Gat es (Tr ansmi ssi on Gat es)
use an N-MOS and a P-MOS in parallel
A
B
B'
0
F=AB
A
B
B'
0
F=AB
Pass gates eliminate some of the disadvantages of simple
pass-transistors
Eliminates reduced noise margins & static power consumption
Disadvantages of pass gate:
Requires both NMOS and PMOS in different wells, both true and
complemented polarities of the control signal needed, increases
node capacitance
Design remains a trade-off!
0
( 1)
( ) 0.69 0.69
2
n
p n eq eq
k
n n
t V kCR CR
=
+
= =
Propagation delay is proportional to n

2
!
Insert buffers
In current technologies, m
opt
is typically 3 or 4
1.7
pbuf
eq
opt
t
CR
m =
13/03/15
13
Most typical use: for multiplexing, or path selecting
Assume in circuit below it is required to either connect A or
B to Y, under control by S
Y = AS + BS (S is easier notation for S-bar = S-inverse = S)
Y = ((AS) (BS)) allows realization with 3 NAND-2 and 1 INV:
14 transistors
Pass gate needs only 6 (or 8) transistors
B
&
&
&
A
S
Y
B
A
S
Y
73
Dynamic CMOS gates
St at i c vs. Dynami c CMOS Ci r c ui t s
Static
At every point in time (except during the switching
transients) each gate output is connected to either VDD or Vss
via a low-resistive path.
The outputs of the gates assume at all times the value of the
Boolean function, implemented by the circuit (except during
switching periods)
Require 2N transistors for N inputs (fan-in of N)
Dynamic
Output not permanently connected to Vdd or Vss
Output value partly relies on storage of signal values on the
capacitance of high impedance circuit nodes.
Input only active when clock is active
Requires N+2 transistors for N inputs
Dynami c Gat e
PDN
CLK
M
p
C
L
Out
M
E
CLK
In
1
In
2
In
3
1
CLK
A
B
C
Out
on
off
Mp
(A&B)|C
1
F(In
1
, In
2
, In
3
)
Precharge
Transistor M
p
Evaluate
M
E
Two phase operation
CLK
Me
off
on
Precharge (CLK = 0)
Evaluate (CLK = 1)
Transistor M
e
Only look at output after
evaluation phase
On rhythm of global clock
Example: use edge-triggered FF
with trigger on 10 transition of
clock to sample logical value
6.3
Condi t i ons on Out put
Only one output transition per
clock cycle, after CLK 01. It
cannot be charged again until
the next precharge operation
Inputs to the gate can make at
most one transition during
CLK
M
evaluation
Output can be in the high
impedance state during and
after evaluation (PDN off), state
is stored on C
L
PDN
M
p
C
L
Out
M
E
CLK
In
1
In
2
In
3
Pr oper t i es of Dynami c Gat es (1)
Logic function is implemented
by the PDN only
Number of transistors is N + 2
(versus 2N for static
complementary CMOS)
Full swing outputs (V
OL
= V
SS
CLK
M
g p (
OL SS
and V
OH
= V
DD
)
Nonratioed sizing of the
devices is not important for
proper functioning
PDN
M
p
C
L
Out
M
E
CLK
In
1
In
2
In
3
13/03/15
14
Faster switching speeds
reduced capacitive load to
predecessor (only PDN)
reduced internal capacitance
(drain cap. of only one pull-
up) CLK
M
p)
Low noise margin (NM
L
)
PDN starts to work as soon
as the input signals exceed
v
TN
V
M
and V
IL
equal to V
TN
PDN
M
p
C
L
Out
M
E
CLK
In
1
In
2
In
3
Needs a precharge clock
{TPS} compare power of dynamic vs
static CMOS: higher or lower
Overall power dissipation usually
significantly higher than static CMOS
Reduced capacitance
no static current path ever exists
PDN
CLK
M
p
C
L
Out
In
1
In
2
In
3
no static current path ever exists
between V
DD
and GND (including P
sc
)
no glitching
higher transition probabilities
extra load on CLK
M
E
CLK
I ssues i n Dynami c Desi gn (1)
Charge leakage via reversed-biased
diffusion diodes and subthreshold leakage
CLK
MP
CL
Out
A=0
M1
V
Out
Precharge
Evaluate
ME
CLK
CLK
MP
CL
Out
ME
CLK
A=0
M1
Static bleeders
Same approach as
level restorer for
pass-transistor logic
81
Charge redistribution
CLK
MP
CL
Out
A
M1
Charge stored originally on C
L
is redistributed
(shared) over C
L
and C
A
leading to reduced
robustness
X
If then V
out
and V
x
reach the same
out Tn
V > V
ME
CLK
B=0
M2
X out x
value
out Tn
A
a
out DD
a L
C
V =- V
C + C
Ca
Cb
Target is to keep since output may
drive a static gate
out Tp
V < V
82
Solution to charge redistribution
Pre-charge internal nodes using a
clock-driven PMOS transistor (at the
cost of increased area and power)
CLK
MP
Out
A
M1
CLK
MkP
ME
CLK
B
M2
83
Backgate Coupling
C
L1
Clk
A=0
Out1
M
p
Out2: 10
C
L2
In
=1
M1
Clk
B=0
M
e
Dynamic NAND Static NAND
84
This node drops
below VDD,
potentially leading
to partial turn-on of
M1
13/03/15
15
Backgate Coupling
2
3
Out1
-1
0
1
0 2 4 6
Time, ns
Clk
In
Out2
85
Clock Feedthrough
Coupling between V
Out
and Clk
in
of the
pre-charge device due to the C
GD
May forward bias the junction and inject
electrons into substrate
V
Out
can rise above V
DD
The fast rising (and falling edges) of the
clock couple to Out
C
L
Clk
A
Out
M
p
clock couple to Out
Clk
B
M
e
-0,5
0,5
1,5
2,5
0 0,5 1
In &
Clk
Out
Time, ns
Clock feedthrough
86
Cascading Dynamic Gates
Clk
Out1
M
p
M
p
Clk
Out2
V
Clk
In
Clk
In
M
e
M
e
Clk
t
Out1
Out2
AV
V
Tn
Only 0 1 transitions allowed at inputs!
Problem when input of 2
nd
gate not being 0 during precharge
87
Del ayed Cl oc k s
In
1
In PDN
M
p Clk
Out1
In
4
PDN
M
p
Clk
Out2
M
kp
1 1
1 0
0 0
0 1
PDN
PDN
In
2
PDN
In
3
M
e Clk
In
4
PDN
In
5
M
e
PDN
PDN
88
Evaluation starts when Out1 is stable
Domi no Logi c
In
1
In PDN
M
p Clk
Out1
In
4
PDN
M
p Clk
Out2
M
kp
1 1
1 0
0 0
0 1
PDN
PDN
Ensures all inputs to the Domino gate is set to 0 during precharge period
In
2
PDN
In
3
M
e Clk
In
4
PDN
In
5
M
e Clk
PDN
PDN
Very high-speed
Input capacitance reduced
High dynamic dissipation
Only non-inverting logic
89
NP Logi c , ak a NORA Logi c
In
1
In PDN
M
p1 Clk
Out1
In
4
PDN
PDN
PUN
M
e2 Clk
In
2
PDN
In
3
M
e1 Clk
In
5
M
p2
PDN
90
Clk
Out2
To other
N blocks
N block P block
To other
P blocks
13/03/15
16
Di f f er ent i al (Dual Rai l ) Domi no Logi c
A
M
p Clk
Out = AB
!A !B
M
kp
Clk
Out = AB
M
kp
M
p
1 0 1 0
on off
B
M
e Clk
!A !B
Solves the problem of non-inverting logic
91
Summar y
Conventional Static CMOS basic principles
Complex Logic Gates
Ratioed logic
Pass transistor logic
Dynamic CMOS gates

04 Combinational 6up PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

04 Combinational 6up PDF

Uploaded by

Copyright:

Available Formats

13/03/15

Minimum path delay

{TPS}: Why is there static dissipation in

Propagation delay is proportional to n

You might also like