Chapter 2 : Operating Principles of MOS Transistors

2.1 Introduction
Chapter 1 introduced the MOS transistor as a switch. The present chapter first develops the fundamental physical
characteristics of the MOS transistor, in which the electrical currents and voltages are the most important quantities.
The link etween physical design and logic networks can e estalished. !igure ".1 depicts various symols used
for the MOS transistors. The symol shown in !igure ".1#a$ is used to indicate only switch logic, while that in
!igure ".1#$ shows the sustrate connection.
Figure 2.1 Various sy!ols for MOS transistors
This chapter first discusses aout the asic electrical and physical properties of the Metal O%ide Semiconductor
#MOS$ transistors. The structure and operation of the nMOS and pMOS transistors are addressed, following which
the concepts of threshold voltage and ody effect are e%plained. The current&voltage equation of a MOS device for
different regions of operation is ne%t estalished.
't is ased on considering the effects of e%ternal ias conditions on charge distriution in MOS system and on
conductance of free carriers on one hand, and the fact that the current flow depends only on the ma(ority carrier
flow etween the two device terminals. )arious second&order effects oserved in MOS!*Ts are ne%t dealt with.
Susequently, the complementary MOS #CMOS$ inverter is taken up. 'ts +C characteristics, noise margin and the
small&signal characteristics are discussed. )arious load configurations of MOS inverters including passive
resistance as well as transistors are presented. The differential inverter involving doule&ended inputs and outputs
are discussed. The complementary switch or the transmission gate, the tristate inverter and the ipolar devices are
riefly dealt with.
2.1.1 nMOS and pMOS "nhanceent Transistors
!igure "." depicts a simplified view of the asic structure of an n&channel enhancement mode transistor, which is
formed on a p&type sustrate of moderate doping level. ,s shown in the figure, the source and the drain regions
made of two isolated islands of n
-
&type diffusion. These two diffusion regions are connected via metal to the
e%ternal conductors. The depletion regions are mainly formed in the more lightly doped p&region. Thus, the source
and the drain are separated from each other y two diodes, as shown in !igure ".". , useful device can, however,
e made only e maintaining a current etween the source and the drain. The region etween the two diffused
islands under the o%ide layer is called the channel region. The channel provides a path for the ma(ority carriers
#electrons for e%ample, in the n&channel device$ to flow etween the source and the drain.
The channel is covered y a thin insulating layer of silicon dio%ide #SiO"$. The gate electrode, made of
polycrystalline silicon #polysilicon or poly in short$ stands over this o%ide. ,s the o%ide layer is an insulator, the
+C current from the gate to the channel is .ero. The source and the drain regions are indistinguishale due to the
physical symmetry of the structure. The current carriers enter the device through the source terminal while they
leave the device y the drain.
The switching ehaviour of a MOS device is characteri.ed y an important parameter called the threshold voltage
#Vth$, which is defined as the minimum voltage, that must e estalished etween the gate and the source #or
!igure in the previous slide/ !igure ".0 Typical current&voltage characteristics for #a$ enhancement mode and #$
depletion mode nMOS transistors
2.2.2 Second Order "ffects
The current&voltage equations in the previous section however are ideal in nature. These have een derived keeping
various secondary effects out of consideration.
Threshold #oltage and !ody effect/ as has een discussed at length in Sec. ".1.1, the threshold voltage Vth does
vary with the voltage difference V
sb
etween the source and the ody #sustrate$. Thus including this difference, the
generali.ed e%pression for the threshold voltage is reiterated as
..................................... #".12$
in which the parameter , known as the substrate-bias #or body-effect $ coefficient is given y
.Typical values of range from 2.3 to 1.". 't may also e written as
*%ample ".4/
Then, at Vsb 5 ".6 volts
,s is clear, the threshold voltage increases y almost half a volt for the aove process parameters when the source
is higher than the sustrate y ".6 volts.
$rain punch%through/ 'n a MOS!*T device with improperly scaled small channel length and too low channel
doping, undesired electrostatic interaction can take place etween the source and the drain known as drain-induced
barrier lowering #+'78$ takes place. This leads to punch&through leakage or reakdown etween the source and
the drain, and loss of gate control. One should consider the surface potential along the channel to understand the
punch&through phenomenon. ,s the drain ias increases, the conduction and edge #which represents the electron
energies$ in the drain is pulled down, leading to an increase in the drain&channel depletion width.
'n a long&channel device, the drain ias does not influence the source&to&channel potential arrier, and it depends on
the increase of gate ias to cause the drain current to flow. 9owever, in a short&channel device, as a result of
increase in drain ias and pull&down of the conduction and edge, the source&channel potential arrier is lowered
due to +'78. This in turn causes drain current to flow regardless of the gate voltage #that is, even if it is elow the
threshold voltage )th$. More simply, the advent of +'78 may e e%plained y the e%pansion of drain depletion