GLOBAL SIGNALS

HCLK:
All inputs are sampled on rising edge of HCLK.
All outputs are driven after rising edge of HCLK.
HRESET_n
RESET is the only active-low signal
RESET can be asserted asynchronously.
RESET is de-asserted synchronously with posedge on clk.
During RESET,
o All address and control signals should be at valid levels.
o HTRANS should be IDLE.

DATA SIGNALS
HWDATA:
Protocol supports max of 32 bits.
Master drives data bus during write transfer.
For transfer that are narrower than bus width, the master only have to drive appropriate
byte lanes.
HRDATA
Protocol supports max of 32 bits.
Appropriate slave drives data bus during read transfer.
If slave extends the transfer holding HREADY low, than slave only needs to provide
valid data on final cycle.
For transfer that are narrower than bus width, the slave only have to drive appropriate
byte lanes.
CONTROL SIGNALS:
HADDR:

Address is 32 bit signal.
Address is driven by master, and sampled by slaves and decoder.
Decoder takes HADDR has input and generates HSEL_xx to select slave.
The minimum address same allocated to individual slave is 1KB.
Slave must only sample the HSEL_x, address, and control signals when HREADY is
HIGH indicating current transfer is completing.
If the system design does not contain completely filled memory map, then you must
include Default Slave.
Default Slave generates error response for NON-SEQ, SEQ transfers on non-existent
address.
Default Slave generates OKAY response for IDLE or BUSY transfers.
HWRITE:
HWRITE is high, indicates write transfer.
HWRITE is low, indicates read transfer.
During write transfer, data should be stable throughout extended cycles.
During read transfer, data is valid only one last cycle of extended cycles.
HSIZE:
This is 3-bit signal.

It indicates the size of the data transfer. (i.e., number of bits transferred in single beat).
For 32-bit data bus, the HSIZE is less than or equal to 3b010
HSIZE has exactly same timing as HADDR, but it should remain constant throughout
BURST Transfer.
HBURST:
This is 3-bit signal.
This indicates type of burst and number of beats in the bus.
It supports Incrementing and Wrapping burst.

Master should not attempt to start an incrementing burst that crosses a 1KB address
boundary.
Bus Termination after BUSY transfer
o Master uses BUSY transfer if it requires more time before continuing with next
transfer in the burst.
o During Undefined length burst INCR, master might insert BUSY transfer and
then decide that no more data transfers is required. Under this circumstances,
master inserts BUSY or IDLE transfer and then terminates the transfer.
o Fixed length Burst (incremental or wrapped) must terminate with SEQ transfer.
o BUSY transfer is not permitted after SINGLE burst.
o SINGLE burst must be followed by IDLE or NON-SEQ
Early Bus Termination:
o Slave Error Response:
Master can terminate burst transfer on ERROR response from slave.
However, this is not strict requirement.
If master does not complete the burst, their no requirement for master to
rebuild the burst on its next transfer to the same slave.
o Multi-layer interconnect termination
In multi master system, if one master terminates, the slave must terminates
the burst from original master and respond to other master immediately.
HTRANS:
It is 2-bit signal.
IDLE:
o Indicates that no data transfer is required.
o Master inserts IDLE transfer when it does not want to perform a data transfer.
o Recommended to terminate locked transfer with an IDLE transfer.
o Slave must always provide a zero wait state OKAY response to IDLE transfer.
BUSY
o Allows master to insert wait cycles in middle of a burst.
o When a master uses a BUSY transfer type, address and control signals must
reflect next transfer in the burst.
o Only INCR can have BUSY transfer type as last cycle.
o Slave must always provide zero wait state OKAY response to BUSY transfers.
NON-SEQ
o Indicates single transfer or the first transfer of a burst.
o The address and control signals are unrelated to the previous transfer.
SEQ
o Remaining transfers in a burst are SEQ, and the address is related to the previous
transfer.
o The control information is identical to the previous transfer.
HPROT:
This is 4-bit signal.
This signal indicates if the transfer is op-code fetch or data access, privileged mode or
user mode access.

Bufferable means, interconnect can delay the transaction reaching its final destination.
Cacheable means, the transaction at final destination does not have to match the
characteristics of the original transaction.
Default value is 4b0011
HPROT signal have exact same timing as HADDRS.
HPROT remains constant throughout a burst transfer.
HMASTLOCK:
HMASTLOCK is asserted when Master needs locked access.
For example, swap instruction needs read and write, which should be executed without
gap.
After locked transfer, it is recommended to insert IDLE cycle.
SLAVE SIGNALS:
HREADY:
Multiplexor takes all HREADY signals from all slaves and selects one based on
HADDR.
HREADY is high when transfer is complete
HREADY is low, transfer is pending.
It is recommended slave do not insert more than 16 wait states.
During waited transfers, the master is restricted to what changes it can make to the
transfer type and address
Transfer type changes during wait states
o IDLE Transfer
During waited transfer, master is allowed to change transfer type from
IDLE to NON-SEQ.
o BUSY Transfer, fixed length burst
During waited transfer, master is allowed to change transfer type from
BUSY to SEQ.
o BUSY Transfer, Undefined length burst
During waited transfer, master is allowed to change transfer type from
BUSY to any other transfer type.
Transfer continues, if it changes from BUSY to SEQ
Transfer terminates, if it changes from BUSY to IDLE or NON-SEQ
Address Changes during wait states.
o During IDLE transfer
Address can change during IDLE transfer waited states.
o After an error response from slave.
Master can change address when slave responded with ERROR response
and HREADY is low.
HRESP: