IEEE Trans. on Electron Devices, Vol.52, pp.

1568-1575, July 2005

Two-Dimensional Analytical Threshold Voltage

Model of Nanoscale Fully Depleted SOI
MOSFET with Electrically Induced Source/Drain
Extensions

M. Jagadesh Kumar1 and Ali A. Orouji

Department of Electrical Engineering,
Indian Institute of Technology, Delhi,
Hauz Khas, New Delhi – 110 016, INDIA.
Email: mamidala@ieee.org Fax: 91-11-2658 1264

1
Corresponding author
Abstract- A new analytical model for the surface potential and the threshold voltage of a

SOI MOSFET with electrically induced shallow source/drain junctions is presented to

investigate the short-channel effects (SCEs). Dividing the SOI MOSFET’s silicon thin

film into three zones, the surface potential is obtained by solving the two-dimensional (2-

D) Poisson’s equation. Our model includes the effects of the body doping concentration,

the lengths of the side and main gates and their work functions, applied drain and

substrate biases, the thickness of the gate and buried oxide and also the silicon thin film.

Our model results reaffirm that the application of induced source/drain extensions to the

SOI MOSFET will successfully control the SCEs for channel lengths even less than 50

nm. Two-dimensional simulation results are used to verify the validity of this model, and

quite good agreements are obtained for various cases.

Index Terms- Device scaling, insulated gate field effect transistor, short-channel effects

(SCEs), silicon-on-insulator (SOI) MOSFET, threshold voltage, two-dimensional (2-D)

modeling
I. INTRODUCTION

As device feature sizes move into deep-sub-micrometer regime for realizing better

device performance and higher integration densities [1], the characteristics of a MOSFET

degrade. When the channel length shrinks, we observe the short-channel effects such as

steep threshold voltage roll-off due to charge-sharing between drain/source and channel

and increased off-state leakage current due to sensitivity of the source/channel barrier to

the drain potential or drain-induced barrier lowering (DIBL). Therefore, the study of

short-channel effects (SCEs) has assumed a significant role because both they pose a

serious challenge to the efforts for down-scaling the MOS technology.

While there are a number of methods available to control SCEs [2], an ultra

shallow extended source/drain is a very effective method to control SCEs. But, it is very

difficult to form shallow junctions by conventional fabrication techniques. Furthermore, a

low channel doping level is desirable for large mobility [3] and small threshold voltage

fluctuation from random effects [4]. It has been reported that SCEs can be suppressed by

using an inversion layer as an ultra shallow extended S/D in the sub-50 nm regime [5]-

[11].

In this paper, we discuss the short-channel effects of SOI MOSFETs whose

extended source and drain junctions are extremely shallow. This extreme shallowness can

be realized in SOI MOSFETs with a triple-gate structure consisting of one main gate and

two side gates. The two side gates are biased independently of the main gate, and induce

the inversion layers that work as the virtual source or drain. This structure is known as

the Electrically Induced Source/Drain Junction SOI MOSFET (EJ SOI MOSFET). There

have already been many reports concerning EJ-MOSFETs [5]-[11]. However, to the best
of our knowledge, the analytical modeling of EJ-SOI MOSFETs has not yet been

reported in literature.

In this work, we report for the first time, an analytical model for a fully depleted

EJ SOI MOSFET by solving the 2-D Poisson equation. The model is used to calculate the

surface potential distribution in the SOI thin film under the main gate and the two side

gates and to explain the unique attributes of the EJ-SOI MOSFET structure in

suppressing the SCEs. This model thus provides an efficient tool for design and

characterization of the novel EJ-SOI MOSFETs. The effects of varying the device

parameters can easily be investigated using the simple models presented in this paper.

The model results are verified by comparing them with the 2-D simulation results from

MEDICI [12].

II. TWO-DIMENTIONAL MODEL FOR SURFACE POTENTIAL

A schematic cross-sectional view of a fully depleted EJ-SOI MOSFET is shown

in Fig. 1 with a main gate MM and two side gates M1S and M2S of lengths LM and LS,

respectively. Silicon dioxide is adopted as a diffusion barrier between the main gate and

the side gate. The thickness of these diffusion barriers (td) is about 3 nm [6], and is

significantly smaller than the main and the side gate lengths. Therefore, we have

neglected these regions in our model. In some structures of EJ-SOI MOSFETs with

floating side gates (FSG) [6], the potential on the FSG is determined by capacitive

coupling from the main gate and S/D. In these structures, if the potential on the side gates

is larger than the “effective” threshold voltage of the side gate region, an inversion layer

is induced under the FSG. Therefore, we can choose the work function of the side gates
for choosing the threshold voltage of side gates. Based on experimental results on FSG

[6], it has been shown that the voltage of the main gate and induced voltage on the side

gate are almost linearly coupled. Therefore, our model can be easily implemented for the

FSG structure using a linear coupling ratio between the main gate and the side gate

voltages.

The relations among the surface potential, charge, and electric field are derived by

solving Poisson’s equation in the silicon thin film. Assuming that the influence of hole

charge carriers and positive fixed charges on the electrostatics of the p-type channel can

be neglected, the potential distribution in the silicon thin film in each of the side regions

and the main region, can be written as [13]

∂ 2 φ ( x, y ) ∂ 2 φ ( x, y ) q
+ = ( N A + n S ( x, y )) (1)
∂x 2
∂y 2
ε Si

n 2i
n S ( x.y) = exp(qϕ( x , y) / KT) (2)
NA

where NA is the silicon film doping concentration, nS(x,y) is electron charge carrier

density, εSi is the dielectric permittivity of the silicon, K is Boltzmann’s constant, T is the

absolute temperature, and φ(x,y) is the electrostatic potential in the thin film region.

To a first-order approximation, the potential distribution in the silicon film is assumed to

have the following form [14]:

φ ( x, y ) = a0 + a1 y + a 2 y 2 (3)

where the a’s are a function of x and can be determined by the boundary conditions. The

boundary conditions at the silicon-oxide interface and the depletion edges are given as

φ ( x,0) = φ S ( x) (4)
φ ( x, t Si ) = φ B ( x) (5)

dφ ( x , y ) Cf
y =0 = [φ S ( x) − VGS + VFB , f ] ( 6)
dy ε Si
dφ ( x , y ) Cb
y =t Si = [φ B ( x) − Veff + VFB ,b ] (7)
dy ε Si

where VGS is the gate bias, φS(x) and φB(x) are the surface potentials along the front side

and the backside oxide-silicon interface respectively; Cf=εox / tf , and Cb=εox /tb are the

front gate and back gate oxide capacitances per unit area respectively; tf and tb are the

thicknesses of front gate oxide and buried layer, respectively; εox is the dielectric

permittivity of the silicon dioxide, VFB,f and VFB,b are the front and the back channel flat

band voltages, respectively; and Veff is the effective substrate voltage to account for the

nonlinearity of potential variation inside the buried oxide [15]-[17].

From (1)-(6), we can obtain

d 2φ S ( x )
− k 2φ S ( x ) = β (8)
dx 2

⎛ Cf Cf ⎞ ⎛ 2 C ⎞
where k 2 = 2⎜⎜1 + + ⎟ ⎜⎜ t Si (1 + 2 Si ) ⎟⎟ and
⎝ C b C Si ⎟⎠ ⎝ Cb ⎠

q ( N A + n S ( x)) ⎛Cf Cf ⎞ ⎛ 2 C ⎞ ⎛ C ⎞
β= − 2 (VGS − VFB , f ) ⎜⎜ + ⎟⎟ ⎜⎜ t Si (1 + 2 Si ) ⎟⎟ − 2 (Veff − VFB ,b ) ⎜⎜ t Si2 (1 + 2 Si ) ⎟⎟
ε Si ⎝ C b C Si ⎠ ⎝ Cb ⎠ ⎝ Cb ⎠
where nS(x) is the surface electron charge density in the silicon thin layer, CSi=εSi /tSi and

tSi are the capacitance per unit area and the thickness of the silicon thin layer,

respectively.

In a conventional SOI MOSFET, the gate is made of only one material, but in the EJ

structure, we have two gates with different work functions and doping density under

them. Applying (8) to this device, we have

d 2φ LS ( x)
2
− k L2φ LS ( x) = β L for 0 ≤ x ≤ L S (9)
dx
d 2φ MS ( x)
2
− k M2 φ MS ( x) = β M for LS ≤ x ≤ LS + LM (10)
dx
d 2φ RS ( x)
− k R2φ RS ( x) = β R for LS + LM ≤ x ≤ 2 LS + LM (11)
dx 2

where φLS(x) ,φRS(x) ,and φMS(x) are the surface potentials under the left/right side gates

and the main gate, respectively. Also k and β correspond to the respective regions. The

above equations are nonlinear second-order differential equations. A rigorous way to

solve the above equations is by using an infinite series solution method as described in

[18]. Since applying this method is difficult even for a simple MOSFET, extracting a

threshold voltage model from this solution is doubly complex for the EJ-MOSFET. For

presenting a simple model, therefore, we consider that the main gate region works in

weak inversion regime [13] and nS≅0 for under the main gate region. Also, we consider

that the side gate regions work in moderate inversion regime and that the minimum

surface mobile charge is equal to NA. The inversion layer charge is exponentially related

to the surface potential. However, to make the solving of the above equations simpler

and meaningful, we have taken the dependence of the surface mobile charge on the

surface potential as follows:

n S ( x) = N A + γ ϕ S ( x) (12)

where γ is a fitting parameter in (V.cm3)-1. By solving (9)-(11), we obtain the solution for

the surface potential for each section (see Appendix I) as:

αL
φ LS ( x) = Ae k x + Be − k x −
L L
for 0 ≤ x ≤ LS (13)
k L2
αM
φ MS ( x) = Ce k M ( x − LS )
+ De − kM ( x − LS ) − for LS ≤ x ≤ LS + LM (14)
k2
 αR
φ RS ( x) = Ee k R ( x − LS − LM )
+ Fe − k R ( x − LS − LM ) − for LS + L M ≤ x ≤ 2 LS + L M (15)
k2

where αL=βL(nS=NA), αM=βM(nS=0), αR=βR(nS=NA), and kR2=kL2=k2+qγ/εSi, and kM2=k2,

and A, B, C, D, E, and F are represented in Appendix I. The above expression for surface

potential can be reduced to the form presented for a single material gate (SMG) structure

[14] and for a double material gate (DMG) [19] upon substituting αL=αM=αR= -αf ,

LM+2LS=L, nS=0, and αM=αR , LS=L1 , LM+LS=L2 , nS=0, respectively.

The minimum potential of the front-channel under the main gate can be calculated from

(14) as

αM
φ S min = 2 CD − (16)
k M2

The minimum occurs at

1 ⎛D⎞
x min = ln⎜ ⎟ + LS (17)
2k M ⎝ C ⎠

The electric field distribution along the channel determines the electron transport velocity

through the channel. The electric field component in the x-direction, under the main and

side gates are given as

dφ LS ( x)
E L ( x) = = A k L exp(k L x) − B k L exp(−k L x) (18)
dx
dφ ( x )
E M ( x) = MS = C k M exp(k M ( x − LS )) − D k M exp(− k M ( x − LS )) (19)
dx
dφ ( x)
E R ( x) = RS = E k R exp(k R ( x − LS − LM )) − F k R exp(−k R ( x − LS − LM )) (20)
dx
The above equations are useful in examining how the drain side electric field is modified

by the presence of the induced source/drain regions in the EJ SOI MOSFET.

To simplify the mathematical model, we have assumed that the gate oxide

thicknesses under the side gates and the main gate are identical. But, in some structures
of EJ- MOSFET [5], the thicknesses of the side/main gates are not same. In the later case,

the gate oxide capacitances are different in each region due to the difference in oxide

thicknesses. However, our model can be used for the above case using different Cf for the

side and main gates in (9)-(11).

III. TWO-DIMENSIONAL THRESHOLD VOLTAGE MODEL

The threshold voltage is that value of the gate voltage at which a conducting channel is

induced at the surface of SOI MOSFET. In a fully depleted thin film SOI, it is desirable

that the front channel turns on before the back channel. Therefore, the threshold voltage

is taken to be that value of gate source voltage for which φS,min=2φF, where φF is the

difference between the extrinsic Fermi level in the bulk region and the intrinsic Fermi

level. In the case of EJ structure, due to the existence of the inversion layer under the side

gates (normally threshold voltage of side gates is very low), the minimum surface

potential is solely determined by the main gate. So the threshold voltage is defined as the

value of the main gate voltage VMGS at which the minimum surface potential φS,min equals

2φF. Hence, we can determine the value of threshold voltage as the value of VMGS by

solving (16).

If Cb<<Cf and CSi, we can obtain an expression for the threshold voltage (see

Appendix II) as:

− Vφ 1 + Vφ21 − 4ξVφ 2
VTH = (21)
2ξ

where ξ, Vφ1 and Vφ2 are constant coefficients as discussed in Appendix II.

A significant result of this formulation is that the threshold voltage of the device can be
controlled by adjusting the workfunctions of the side gates and the main gate. Due to the

dependence of the threshold voltage on the difference between the gate material work

functions of the side gates and the main gate, we have another degree of freedom for the

SOI transistor design, with extended ultra-shallow source/drain regions.

IV. RESULTS AND DISCUSSION

For verifying the proposed analytical model, the 2-D device simulator MEDICI [12]

was used to simulate the surface potential distribution within the silicon thin film. A

fully depleted (FD) n-channel EJ SOI structure is implemented in MEDICI having

uniformly doped source/drain and body regions with a doping density of 5×1019cm-3 and

6×1016cm-3, respectively. The other parameters used in our simulation are: buried oxide

thickness tb = 500 nm, thin film layer tSi = 50 nm, gate oxide thickness tf = 5 nm, and

thickness of the diffusion barrier between the main and the side gates td = 5 nm. The

fitting parameter γ in (12) is chosen to be 2.6×1015 (V.cm3)-1. The work functions of the

side and the main gates are chosen as 4.7 eV and 4.9 eV, respectively. In this case, the

threshold voltage of the side gate and the main gates are 0.17 and 0.58 volts, respectively.

The gate work function of the Single Gate (SG) structure is chosen as 4.9 eV. All the

device parameters of EJ and SG structure are equivalent unless otherwise stated.

For the structure under consideration, the effective substrate voltages for the side and

main gate regions are derived from the simulation results suggested by Joachim et al. [15]

and can be expressed by the simple empirical relations as given below:

VeffL = VSUB + V DS ( −1.25VSGS − 0.118VMGS + 0.959) ( 22)

VeffM = V SUB + V DS (0.212V SGS − 1.55V MGS + 1.702) ( 23)

VeffR = VSUB + V DS ( −0.642VSGS + 0.643VMGS + 1.126) ( 24)

where VeffL, VeffR, and VeffM are the effective substrate voltages for the left/right side and

main gate regions, respectively and VSGS, and VMGS are the side and main gate voltages,

respectively.

In Fig. 2, the calculated and simulated values of surface potential are plotted against the

horizontal distance x in the channel for the main channel length of 100 nm and the side

channel length of 50 nm. It can be seen from the figure that due to the presence of the EJ,

there is no significant change in the potential under the main gate as the drain bias is

increased even for drain voltages up to 1.5 V. Hence, the channel region under the main

gate is “screened” from the changes in the drain potential, i.e. the drain voltage is not

absorbed under the main gate. As a consequence, VDS has only a very small influence on

drain current after saturation and the drain conductance is reduced. Therefore, the side

gates (i.e. ultra-shallow source/drain) effectively suppress the short channel effects and

consequently minimize the threshold voltage roll-off, in the sub-50 nm regime.

Fig. 3 shows the surface potential under the main channel for different side gate

lengths. We note that when the side gate length is long, the variation in the surface

potential is the lowest among all the three cases. This is very effective for suppressing

SCEs. But a long side gate length will increase the sheet resistance of the induced

source/drain (virtual source/drain) regions affecting the current driving capability of the

device. However, it is important to point out that when the side gate length is 50 nm, the

variation of surface potential is still small and the shift in the point of the minimum

potential is almost zero even when VDS = 1.5 V which is the worst case. It is worth noting

that the use of the inversion layer as a virtual source/drain is very effective in reducing
both the SCEs and the parasitic source/drain resistances when a sub-15 nm source/drain

is needed for future scaled CMOS [6].

Changes in the subthreshold characteristics reflect changes in the surface potential.

Fig. 4 shows the dependence of surface potential on side gate bias, calculated with

MEDICI and the model. The main gate voltage is set at 0.58 V. When the side gate

voltage is less than 0.17V, the surface-potential in the virtual drain is low, and there are

not enough carriers to form the inversion layer in the virtual drain or source. However,

when the side gate bias is more than 0.17 V, the potential in the virtual drain will increase

and the carrier concentration in the virtual source and drain are sufficient to form the

inversion layers to function as the virtual source and drain. It should be noted that the

potential edge in the virtual drain moves slightly toward the channel as the side gate bias

increases above 0.17 V making the channel length depend slightly on the side gate bias.

In Fig. 5, the electric field distribution along the channel near the drain is shown for the

single gate (SG) and the EJ SOI MOSFETs with a channel length L=100 nm. It is evident

from the figure that the presence of an induced drain under the side gate reduces the peak

electric field considerably. We also note that, the results from the analytical model are in

close proximity with the simulation results.

The variation of the front-channel minimum surface potential as a function of the main

channel length LM of a fully depleted EJ SOI MOSFET for two different silicon thin-film

thicknesses is shown in Fig. 6. In the EJ SOI MOSFETs, the dependence of minimum

front-channel potential on the thin-film thickness can be more effectively reduced by

decreasing t Si as compared to single gate SOI MOSFETs. This is due to the existence of

the ultra-shallow virtual source/drain regions under the side gates.

 Fig. 7 shows the calculated and simulated values of threshold voltage as a function of

main channel length. It is seen from the figure that the threshold voltage obtained from

the analytical model is close to the simulation results. The small discrepancy (about 6.5

percent in the worst case) between analytical and simulated threshold voltage values is

due to the difference in the definitions of threshold voltage used in our model and the

MEDICI simulator. In MEDICI, the threshold voltage of the device is extracted from the

commonly used maximum transconductance method. But, in our model we used φS = 2φF

as is commonly done in literature. The model results when compared to the simulation

data, however, justify the validity of the model for the main channel lengths well below

100 nm and closely track the MEDICI simulation results.

V. CONCLUSION

Based on the simplified 2-D Poisson’s equation, new analytical surface potential and

threshold voltage models for a fully depleted SOI MOSFET with electrically shallow

junction as source/drain are derived. The SOI MOSFET device is divided into three zones

each represented by second-order differential equation. Applying the constraint of

potential and electric field continuity to solve these equations, combined with the

boundary conditions in the source and drain boundaries, the surface potential model is

obtained. By setting, the minimum surface potential equal to 2φ F to define the threshold

voltage, the analytical threshold voltage model is then derived. The calculated values of

the surface potential in the silicon thin film obtained from the proposed model agree well

with the simulation results. Our results establish that the EJ structure, exhibits subdued

SCEs due to a very thin inversion layer in the induced source and drain extensions. Also,
the variation of the minimum channel potential with decreasing thin-film thickness can be

more effectively reduced in the EJ structure at shallow thin-film thicknesses. Further, it is

clearly seen that the EJ structure gives rise to the desirable threshold voltage “roll-up”

with decreasing channel lengths. Thus, the introduction of the EJ structure opens up a

new avenue to improve the short-channel behavior of the SOI MOSFETs over their

single-gate SOI and the bulk counterparts.

APPENDIX I

Surface Potential Model

The constant coefficients (A, B, C, D, E, and F) in (13)-(15) are found using the

following boundary conditions:

1) Surface potential at the interface of each of the two dissimilar gates is continuous

φ L ( LS ,0) = φ M ( LS ,0) ( A − 1)

φ M ( LS + LM ,0) = φ R ( LS + LM ,0) ( A − 2)

where φL (x,y), φR (x,y), and φM (x,y) are the electrostatics potential in the left/right side,

and main gates, respectively.

2) Electric flux at the interface of each of the two dissimilar gates is continuous

dφ L ( x, y ) dφ M ( x, y )
x = LS = x = LS ( A − 3)
dx dx
dφ M ( x, y ) dφ R ( x, y )
x = LS + LM = x = LS + LM ( A − 4)
dx dx

3) The potential at the source end is

4) φ L (0,0) = φ LS (0) = Vbi ( A − 5)

where Vbi=(Eg/2)+VT ln(NA/ni) is the built-in potential across the body-source junction,
Eg is the band gap of silicon, VT is the thermal voltage, and ni is the intrinsic carrier

density of silicon.

5) The potential at the drain end is

φ R (2 LS + LM ,0) = φ RS (2 LS + LM ) = Vbi + V DS ( A − 6)

Now using the boundary conditions (A-1)-(A-6) to solve for A, B, C, D, E, and F, we

obtain

⎧⎪ 2k k (V + VDS − σ R ) − (Vbi − σ L )[(k M

2
− k L2 ) sinh( k M LM ) − 0.5(k M − k L ) 2 exp(−2k L LS + k M LM ) + 0.5( k M + k L ) 2 .
A = ⎨ L M bi
⎪⎩ (k M + k L ) 2 sinh(k M LM + 2k S LS ) − (k M − k L ) 2 sinh( 2k S LS − k M LM ) − 2(k M
2
− k L2 ) sinh( k M LM )
exp(−(2k L LS + k M LM )] − k M (σ L − σ M )[(k L + k M ) cosh(k L LS + k M LM ) + (k L − k M ) cosh(k L LL − k M LM )] − 2k L k M (σ M − σ R ) cosh(k L LS )] ⎫
⎬
⎭
( A − 7)

B = Vbi − A − σ L ( A − 8)

A(k M + k L ) B(k M − k L ) (σ − σ M )
C= exp(k L LS ) + exp(−k L LS ) + L ( A − 9)
2k M 2k M 2

A(k M − k L ) B(k M + k L ) (σ − σ M )
D= exp(k L LS ) + exp(− k L LS ) + L ( A − 10)
2k M 2k M 2

C (k L + k M ) D (k L − k M ) (σ − σ R )
E= exp( k M LM ) + exp( − k M LM ) + M ( A − 11)
2k L 2k L 2

C (k L − k M ) D(k L + k M ) (σ − σ R )
F= exp(k M LM ) + exp(− k M LM ) + M ( A − 12)
2k L 2k L 2

where σ i = −
αi , i = L, M , R
k i2
 APPENDIX II

Threshold Voltage Model

Using the definition of β in (8), when C b << C f and C Si , we can approximate σM as

Cb qN A t Si
σM ≈ (VeffM − VFB ,b ) − + VMGS − VFB ,MF ( A − 13)
Cf Cf

where VFB,MF is the front-channel flatband voltage for the main gate. Solving (16), we

obtain threshold voltage model for the EJ-SOI MOSFET as given by (21) where the

constant coefficients ξ, Vφ1, and Vφ2 are expressed as

ξ = Z 1 R 2 − Z 3 R + Z 2 R 2 + Z 4 R − 2(k M2 + k L2 ) R 2 + Q 2 k M2 − Q 2 ( A − 14)

Vφ 1 = 2 PRZ 1 + Z 3 ( XR − P) + Z 2 [−2Q(Vbi − σ L ) R + 2 RP] − Z 4 [ RX − P + Q(Vbi − σ L )]

− 2(k M2 + k L2 )[ PR − PQ(Vbi − σ L )] − 2Q 2 k M2 X + 2(2 ϕ F + X − σ L )Q 2 ( A − 15)

Vφ 2 = Z 1 P 2 + Z 3 XP + Z 2 [Q 2 (Vbi − σ L ) 2 + P 2 − 2QP(Vbi − σ L )] + 16 XQ 2 k M2
Z 4 X [(Vbi − σ L )Q − P] + Q 2 k M2 X 2 − Q 2 (2ϕ F + X − σ L ) 2 ( A − 16)

Z 1 = (k M + k L )(k M − k L ) exp(2k L LS ) ( A − 17)

Z 2 = (k M + k L )(k M − k L ) exp(−2k L LS ) ( A − 18)

Z 3 = 2Qk M2 exp(k L LS ) ( A − 19)

Z 4 = 2Qk M2 exp(− k L Ls ) ( A − 20)

Cb qN A t Si
X =σL − (VeffM − V FB ,b ) + + VFB , MF ( A − 21)
Cf Cf
P = 2k M k L (Vbi + V DS − σ R ) − (Vbi − σ L )[(k M2 − k L2 ) sinh(k M L M ) + 0.5(k M − k L ) 2 ⋅
exp(−2k L L S + k M L M ) + 0.5(k M + k L ) 2 exp(−2k L L S − k M L M )] − XR ( A − 22)

Q = (k M + k L ) 2 sinh( k M L M + 2k S L S ) − (k M − k L ) 2 sinh( 2k S L S − k M L M )
− 2(k M2 − k L2 ) sinh( k M L M ) ( A − 23)

R = k M [(k L − k M ) cosh(k L LS − k M LM ) + (k L + k M ) cosh(k M LM + k L LS ) − 2k L cosh(k L LS )]

( A − 24)
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Figure Captions

Figure 1 Cross-sectional view of an N-channel fully depleted EJ SOI MOSFET

Figure 2 Surface potential profiles in the channel of a fully depleted EJ SOI

MOSFET obtained from the analytical model and MEDICI simulation

for different drain biases.

Figure 3 Surface potential in the main channel for different side gates lengths.

Figure 4 Changes in the surface potential caused by varying the side gate bias.

Figure 5 Longitudinal electric field along the channel toward the drain end

obtained from the analytical model and MEDICI simulation with 50 nm

and 100 nm side and main gates lengths, respectively.

Figure 6 Variation of the front-channel minimum potential versus main gate

length for the fully depleted EJ SOI MOSFET at different silicon thin-

film thicknesses.

Figure 7 Threshold voltage versus main channel length for channel lengths up to

40 nm with VDS= 50 mV.

 Side Gates

Main Gate
Source Drain
LS LM LS
td td tf

n+ n+
NA tSi

Buried Oxide (BOX) tb

x
P Substrate
y

Fig. 1.
 2.6 16 -3
NA=6x10 cm VDS=1.5V
2.4 LS=50nm
LM=100nm
2.2
VSGS=0.2V VDS=1V
2.0 VMSG=0.1V
Surface Potential (volts)

1.8
1.6 VDS=0.5V
1.4
1.2
1.0
0.8
0.6
0.4 MEDICI
0.2 MODEL

0 50 100 150 200 250

Position in channel (nm)

Fig. 2.
 0.8
VDS=1.5V
0.7 VSGS=0.2V
VMGS=0.1V
0.6 LM=100nm
Surface Potential (volts)

φM=4.7eV
0.5 φS=4.9eV

0.4

0.3
MEDICI (LS=50nm)
MEDICI (LS=75nm)
0.2 MEDICI (LS=100nm)
MODEL (LS=50nm)
0.1 MODEL(LS=75nm)
MODEL(Ls=100nm)
0.0
-25 0 25 50 75 100 125

Position in Main channel (nm)

Fig.3
 2.6
LS=50nm MEDICI (VSGS=0V)
2.4 LM=100nm MODEL (VSGS=0V)
VMGS=0.58V MEDICI (VSGS=0.1V)
2.2 MODEL (VSGS=0.1V)
VDS=1.5V
Surface Potential (volts)

2.0 MEDICI (VSGS=0.4V)

MODEL (VSGS=0.4V)
1.8

1.6
LM
1.4

1.2

1.0

0.8

0.6

0.4
0 50 100 150 200 250

Position in channel (nm)

Fig. 4.
 1000
EJ-SOI VDS=1.5V SG-SOI VDS=1.5V
900 VMGS=0.1V VGS=0.1V
VSGS=0.2V L=100nm
800
LS=50nm φM=4.9eV
Electric Field (kV/cm)

700 LM=100nm
φM=4.9eV
600 φS=4.7eV
500

400 MEDICI (EJ)

MODEL (EJ)
300
MEDICI (SG)
200

100

0
50 60 70 80 90 100

Position in Main channel (nm)

Fig. 5.
 1.0
EJ-SOI SG-SOI
VDS=0.05V VDS=0.05V
VSGS=0.2V VGS=0.1V MODEL-EJ (tSi=50nm)
MEDICI-EJ (tSi=50nm)
Minimum Surface Potential (Volts)

0.8 VMGS=0.1V
LS=50nm MODEL-EJ (tSi=30nm)
MEDICI-EJ (tSi=30nm)
MEDICI-SG (tSi=50nm)
0.6 MEDICI-SG (tSi=30nm)

0.4

0.2

0.0
0 50 100 150 200 250 300 350 400 450
Main Channel Length (nm)

Fig. 6.
 0.8

Threshold Voltage (volts) 0.7

0.6

0.5

0.4

0.3 VDS=50mV EJ-SOI:φS=4.7V

VSGS=0.2V φM=4.9V
0.2 MEDICI(EJ)
LS=50nm SG-SOI:φM=4.9V
MODEL(EJ)
0.1 MEDICI(SG)

0.0
0 50 100 150 200 250 300 350 400 450

Main Channel Length (nm)

Fig. 7.