New Electronics Magazine - May 24th 2011-TV

Find out whats new! www.digikey.co.
uk/new
www.newelectronics.co.uk
visit www.newelectronics.co.uk/forum and join the discussion 24 May 2011
FAULT TOLERANT DESIGN MORE SCOPE FOR EMBEDDED TEST FPGAS TO GO OPTICAL?
Power to the people
Wireless data is set to be followed by wireless power, but whats the best way of delivering it?
P001_NELE_MAY24.qxp:Layout 1 18/5/11 12:50 Page 3
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Contents Vol 44 No 10
24 May 2011 3 www.newelectronics.co.uk
For the latest topics
being discussed by
your peers
Comment 5
It might look like
Intel is fighting ARM,
but the real battle is
how to design
transistors at ever
smaller scales
News 7
Research team
finds out more
about how the
memristor works
NXP looks to play a
role in internet of
things with the
creation of
technology that
enables web control
of light bulbs
SoC set to enable
the broader
implementation of
coherent 40Gbit/s
optical networking
Have you joined the
New Electronics
Forum yet? If you
havent, why not
take a look?
7
37
28
14
45
Cover Story 14
Power to the people
Wireless data is set to be followed by wireless power. But
whats going to be the best delivery method?
Expert Panel 19
Scrapheap challenge
Our experts discuss how fault tolerant design will allow
defective multicore chips to be used, rather than scrapped
Directives & Standards 33
Health checks
The Directives and standards which designers need to keep
in mind when developing devices for medical applications
Embedded Test 37
More scope for testing
As engineers needs develop, oscilloscope manufacturers are
providing more functionality in smaller packages for less
Programmable Platforms 41
Seeing the light
Interface speeds are increasing as the demand for data grows.
But will fpgas see the light through optical interconnect?
Displays 45
I can see clearly now!
A clear force sensing material is set to see touch screen
functionality included in much larger displays than today
Marketwatch 48
New Electronics monthly round up of component
pricing and availability
Optical opportunities 24
Chip makers are moving to the third dimension as they
create the successor to the multichip module
All about the numbers 28
The decision to base all datatypes on fixed 8bit chunks
was more to do with cost cutting than analysis
Technology Watch
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Company S MLC SSD
Company L MLC SSD
Toshiba SSD (HD2)
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P004_NELE_MAY24 18/5/11 11:02 Page 1
Comment
A
RM processors were once used primarily in mobile phones. Intels processors,
meanwhile, powered pretty much every pc. Then the world changed; smartphones
appeared, tablet computers started to be developed and industry began to focus more
closely on energy efficiency. Users needed different kinds of processor.
ARMs low power credentials developed from working with mobile phone companies
served it well; particularly in the burgeoning portable device market. Intels
processors, meanwhile, remained relatively power hungry, although it has since
developed the lower power Atom family.
While Intel has never admitted openly that ARM is getting in its face, it is now
speeding up the Atom development process. And, if reports are to be believed, Intels ceo
Paul Otellini said this is because its processor road map was inadequate.
Intel has, famously, adopted the tick tock approach as a way of matching its
products to the demands of Moores Law. In the first year of a Moores Law cycle the
tick a new process technology is delivered. In the second the tock its
microarchitecture is upgraded.
A couple of years ago, observers wondered if Intels tick tock approach was slowing.
Today, it looks like a new battery has been put in the clock, because it wants to move
three process nodes ahead in just two years; Atom processors manufactured on a 14nm
technology are planned to be available in 2014.
But where does Intels tick tock go after 14nm? In fact, where does semiconductor
manufacturing go after 14nm? There is a substantial brick wall ahead; it is broadly
accepted that cmos wont scale beyond 10nm; even getting to 10nm might be too big a
challenge, bearing in mind lithography issues.
While ARM and Intel might, on the surface, appear to be battling each other, the real
fight is about how to create reliable transistors from a handful of atoms.
Graham Pitcher, Group Editor (gpitcher@findlay.co.uk)
Group Editor: Graham Pitcher
Web Editor: Chris Shaw
Online Editorial Assistant: Laura Hopperton
Contributing Editors:
David Boothroyd, Chris Edwards,
Louise Joselyn, Roy Rubenstein
Art Editor: Martin Cherry
Illustrator: Phil Holmes
Key Account Director: Tricia Bodsworth
Classified Sales: James Slade
Circulation Manager: Chris Jones
(circulation@findlay.co.uk)
Production Controller: Nicki McKenna
Publisher: Peter Ring
Executive Director: Ed Tranter
Represented in Japan by:
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New Electronics: Tel: 01322 221144
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email: ne@findlay.co.uk
ISSN 0047-9624
New Electronics, incorporating
Electronic Equipment News and Electronics
News, is published twice monthly by
Findlay Media Ltd,
Hawley Mill, Hawley Road,
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Copyright 2011 Findlay Media.
Annual subscription (22 issues)
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Moving on? If you change jobs or your
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receiving your free copy of New Electronics
.
24 May 2011 5
Pushing
forward
Intel decides its processor road map
is inadequate and looks at 14nm
www.newelectronics.co.uk/forum
Your electronics community
discussion board
P006_NELE_MAY24 18/5/11 11:03 Page 1
Memri stors News
More about memristors
Research team discovers more about the fourth circuit
design element. Graham Pitcherreports.
Researchers from HP Labs and the University of California, Santa Barbara,
have described how memristors work at the material level. Understanding
the physical processes within memristors is said to be essential if the
devices are to realise their potential as a future unified memory.
The memristor was first postulated in a paper published in 1971 by
Professor Leon Chua. He looked at the basics of circuit design and saw four
variables, but only three elements resistor, capacitor and inductor. His
view was that the fourth fundamental circuit element the memristor
would combine resistance and memory, properties that cannot be
duplicated by any combination of the other three elements. However, the
memristor remained theoretical until its discovery in 2008 by a team led by
Dr Stan Williams, pictured, of HP Labs.
The memristor is thought to enable more energy efficient computing systems, with memories that retain
information even after the power is off. The researchers also believe it may be possible to create systems
with some of the pattern matching abilities of the brain.
By using highly focused xrays, the team probed the memristor, discovering a 100nm region with
concentrated oxygen vacancies where memristive switching occurs. This region was surrounded by a newly
developed structural phase, which acted like a thermometer telling researchers where and how hot it became.
On track for new
testing facility
Test group TRaC is spending 2million to create a
new emc and environmental test facility in
Dorset. The site, set to open in September, will be
a UK centre of excellence for all aspects of emc
testing for the aerospace and defence industries.
TRaC South will offer a range of test facilities,
including: three emc chambers capable of testing
to a broad range of military/aerospace standards;
two CISPR 16-1-4 compliant chambers for
commercial testing; and a further chamber
dedicated to transient testing. An electromagnetic
shaker table with a 2tonne load capability will also
be installed.
For more on testing, see page 33
SiGe bought for
$210million
Skyworks Solutions has acquired rf chip specialist
SiGe Semiconductor for $210million in cash. The
move will allow Skyworks to offer wireless
networking products that support all key
operating frequencies and with flexibility to
address high growth applications. Sohail Khan,
SiGes president and ceo, believes the move is
good for the company. Together, we can develop
and deliver products of unprecedented integration
and improve our customers performance in the
increasingly connected wireless world.
Superior supercaps
Scientists at the US Brookhaven National
Laboratory have uncovered the nanoscale
structure of a form of carbon created by
researchers from the University of Texas, Austin
(UT). The UT team set out to create a more
porous form of carbon by modifying graphene
platelets. The result is a material which stores
electric charge like a super absorbent sponge.
Supercapacitors made from the material are said
to have an energy density approaching that of
lead acid batteries.
This new material combines the attributes of
[batteries and supercapacitors], said University
of Texas team leader Rodney Ruoff. We were
rather stunned by its exceptional performance.
Our studies revealed that the materials 3d
nanoscale structure consists of a network of
highly curved, single atom thick walls forming
tiny pores with widths ranging from 1 to 5nm.
Brookhaven material scientist Eric Stach
added: These properties make this new form of
carbon attractive for meeting electrical energy
storage needs that also require a quick release
of energy.
Synopsys and Rohde & Schwarz have entered a
strategic collaboration to provide technology that
accelerates the design and verification of
components for LTE and LTE Advanced based
communications systems.
As part of the agreement, Synopsys is
contributing its algorithm design and verification
solutions, while Rohde & Schwarz is contributing its
signal generation and test and measurement
expertise.
According to Dr Markus Willems, senior product
marketing manager, system level solutions, for
Synposys: Both companies have offerings in LTE,
but address different parts of the design process.
Synopsys is actively involved in the early stages of
design, including algorithm development, while
Rohde & Schwarz offers a range of general purpose
test equipment. While both companies target the
same companies, we talk with different teams. Our
objective is to remove the wall between the concept
and test phases; working in silos is not good.
The collaboration will allow Synopsys LTE library
to be verified against Rohde & Schwarzs test and
measurement solutions, increasing design
confidence. Meanwhile, Rohde & Schwarz test
equipment will be able to automatically derive its
configuration from the Synopsys simulation setup.
Since typical configurations consist of more than
100 parameters, this integration significantly
reduces the time it takes to achieve a correct setup
and reduces the risk of configuration
inconsistencies.
For more on test and measurement, see the
article on page 37
Collaboration aims to ease LTE design challenges
All lit up
Interactive Wear demonstrated a number of
applications for wearable electronics at the
recent Techtextil tradeshow in Frankfurt.
Amongst the examples were leather motorbike
clothing featuring the iLightX technology
platform. In this, 3mm micro leds were included
on the side seams of trousers and in the breast
and back areas of the jacket.
May 24 2011 7 www.newelectronics.co.uk
News Internet of Thi ngs
Internet enabled light bulbs
NXP set to give light bulbs IP addresses with energy
saving technology. Graham Pitcherreports.
NXP has unveiled technology that has to potential to provide every light bulb with its own IP address. In this
way, light bulbs could be controlled from any internet enabled device. The approach builds on its recent
acquisition of Jennic.
The technology, called GreenChip, is small enough to fit within the base of a regular energy efficient light
bulb. Two versions will be launched: GreenChip iCFL, for use with compact fluorescents (cfl); and GreenChip
iSSL, for use with leds. Both chipsets can act as dimmable drivers for smart lamps and are accompanied by:
a standby supply controller, with 10mW no load capability; a 2.4GHz IEEE802.15.4 compatible wireless
microcontroller; and wireless connectivity, enabled by the JenNet IP network layer software.
John Croteau, NXPs general manager, power lighting solutions and high performance RF, said: The
chipset has very low power consumption so it doesnt negate the benefits of energy efficient lighting. And
the cost structure is such that it can ship in consumer light bulbs.
NXP is partnering with TCP, a leading manufacturer of cfl and led lamps. TCP makes more than 1million
light bulbs a day, said Croteau, and will be launching consumer ready products. This is not a technology
demonstrator. A further partnership with GreenWave Reality will see an intelligent lighting control and
management solution becoming available.
NXP will also making the technology available under an open source licence and will establish a
consortium to oversee its development. There will not be an internet of things if technology is proprietary
or with royalties, Croteau noted, adding and if it only works with the iPhone, it wont be deployable.
NXP will be taking on ZigBee in the emerging wireless control sector, even though Croteau said this
wouldnt be the case. Its not about competing with ZigBee, Croteau claimed, its about delivering
something people want to buy.
Acquistion
addresses 100G
Xilinx has acquired silicon IP provider Sarance
Technologies as part of a move to establish an
industry leading communications portfolio for
100G and beyond line cards.
One of the three founders of the Interlaken
Alliance, Sarance provides a range of fpga
optimised chip to chip interconnect IP focused
on the Ethernet, Interlaken, and the network
search engine markets and is said to have the
only IP technology capable of scaling to
400Gbit/s for bridging in an fpga.
Analysers meet
demanding needs
The ZNB and ZNC from Rohde & Schwarz are said
to represent a new generation of vector network
analyser, set to meet demanding applications in
the production and development of rf
components.
With a dynamic range of up to 140dB and a
sweep time as low as 4ms, the devices cover
frequencies from 9kHz to 3GHz, 4.5GHz or
8.5GHz, depending on the model. Each has a
large touchscreen.
The ZNB, the more powerful device, is
available in two and four port options, while the
ZNC, with two test ports, is a cost reduced
version for those with less demanding dynamic
range and functional requirements.
Nujira boosts
funding
Nujira has secured a further 10million in
funding in its latest investment round. The cash
will be directed to a project that hopes to install
Nujiras Coolteq wideband Envelope Tracking
technology into 800million energy efficient 3G
and 4G devices by 2016.
Tim Haynes, Nujiras ceo, said: This funding
will allow the expansion of Nujiras handset
engineering team to support product
development and engagements with leading
vendors in the global handset market.
Briefs
Having determined the companys processor road
map is inadequate, Intels ceo Paul Otellini is
putting the pressure on his designers and
promising that Atom processors manufactured on
14nm technology will be available in 2014.
Addressing an analysts meeting last week,
Otellini said the move will allow devices with lower
power consumption to be developed. Intels current
processors have a target power of around 35W.
This will be reduced to 15W, with some Atom parts
consuming less than 5W.
This will see Intel moving through three process
nodes in two years; much quicker than it normally
would, based on its tick tock model.
Intel looks to speed its tick tock approach
Power semi packaging
breakthrough
Power semiconductor specialist Semikron has developed a new
packaging technology which is said to remove the need for bond wires,
solders and thermal paste. Called SKiN technology, the approach is
based on the use of a flexible foil and sintered connections. According
to the company, current density is doubled to 3A/cm^2 and converter
volume is reduced by 35%.
In addition to removing the need for wire bonding, a sinter layer is
used to replace solder thermal paste, said to be responsible for 30% of the total thermal resistance in a
system. This means thermal conductivity between chip and heat sink is improved, resulting in a 30%
increase in usable electric current. Alongside higher current carrying capacity, devices constructed
using this technology are said to have ten times the load cycle capability of wire bonded parts.
Semikron says wire bonding has been the main method of connecting the chips top side to a
direct bonded copper substrate for 25 years, but notes this method cannot meet support higher
current densities.
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24 May 2011 9
P009_NELE_MAY24 20/5/11 10:53 Page 9
FPGA prototyping improved
IC design software specialist SpringSoft has
announced the ProtoLink Probe Visualizer, said to
increase design visibility and simplify debug of
fpga based prototype boards.
Probe Visualizer uses patented interconnect
innovations and software automation to shorten
the verification cycle of off the shelf or custom
designed prototypes, maximising the return on
investment for early validation of SoC designs.
More companies are moving to an fpga
prototyping approach for system level validation,
claimed Yu-Chin Hsu, vp of verification technology.
But implementation complexity and debug
capabilities are still critical factors that get in the
way of prototype deployment. Probe Visualizer
addresses the verification burden this puts on
prototype developers and SoC teams.
Timing chip for
OTN applications
Silicon Laboratories has introduced integrated clock
ics designed to address the complex timing
requirements of high speed optical transport
networks (OTN).
The Si5374 and Si5375 devices are said to be
the first single chip timing parts to integrate four
independent plls. Each clock multiplier can be
configured to generate any frequency from 2kHz to
808MHz, simplifying the generation of high speed
PHY reference clocks and eliminating the need for
discrete vcxo based plls.
Meanwhile, the company has added more than
100 clock generation and clock distribution
products to its portfolio following the recent
acquisition of SpectraLinear.
News Opti cal Networki ng
Cutting fibre comms costs
SoC set to enable cost effective 40G coherent
networking. Graham Pitcherreports.
PMC-Sierra has unveiled what it calls the most advanced 40Gbit/s SoC solution for coherent (single
wavelength) optical networking. The PM6373 POLO 40G doubles line card density and reduces power
consumption by more than 50% when compared to 40G non coherent network deployments.
As the communications industry looks to boost fibre transmission rates beyond 10Gbit/s, POLO 40G is
said to lower capital costs by eliminating the need for dispersion compensation management, dispersion
compensated fibre and the cost of tuning and managing this equipment. Because POLO enabled line cards
require only a single slot, carriers will be able to double density and reduce power consumption. Jay Bennett,
product marketing manager for PMC-Sierras communication products division, said: POLO takes coherent
networking away from niche deployment, where it is only used on the most important routes, to something
that can be deployed broadly. It also enables the collapsing of two or three slots into a low power form factor.
The 40nm cmos SoC integrates high performance mixed signal technology, digital signal processing,
flash a/d converters, OTN framing and PMCs Swizzle forward error correction technology. Together, the
elements compensate for optical impairments and improve optical performance by more than 2dB, extend
fibre reach by 25%. Bennett said 40nm was key. This enables a low power solution that doesnt need
forced cooling. We want to enable existing networks to be upgraded while controlling costs.
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Inventory tracking
system implemented
Future Electronics has completed the introduction of a
worldwide inventory tracking and parts ordering software
system which, it claims, improves its ability to match its
available stock with expected market demand. The system
will allow the company to offer next day availability of the
100,000 most popular components to any customer on nearly every business day of the year.
The Inventory Management System (IMS) monitors shipments to customers and deliveries from
suppliers and provides a real time calculation of the number of days of stock for the 250,000 parts it
holds globally. The IMS also calculates the effect of variables such as swings in customer demand and
extensions or reductions in supplier lead times on stock requirements and issues purchasing
commands in order to maintain buffer stocks and to provide for sustained availability of parts. Future
says that IMS will allow stock profiles at its warehouses in Memphis, Leipzig (pictured) and Singapore to
reflect more closely actual customer demand.
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P011_NELE_MAY24 18/5/11 11:05 Page 1
News New Electroni cs Onli ne Forum
Forum pulls industry together
New Electronics has launched a Forum for design
engineers, and it is already creating a buzz within the
electronics community. Chris Shawreports.
In just a few years, social networking has evolved from a
medium to keep up to date with the activities of friends
and family, to a vital tool for industry. Forums, in
particular, provide a valuable resource for online users
to advise, ask questions or share opinions.
With this in mind, Findlay Media has announced the
launch of the New Electronics Forum
(www.newelectronics.co.uk/forum), a resource
designed to pull the industry together by enabling
electronics design engineers, SMEs and OEMs to interact.
The Forum is broken down into categories covering:
asic/soc/fpgas; eda and board level design; embedded software development; power; mcus; mixed signal
and analogue; test and measurement; and other technologies. An electronics legislation section allows
you to ask expert Gary Nevison, Premier Farnells head of legislation and compliance, for advice.
Because electronics is such a fast moving and ever changing industry, its vital that design engineers
keep up to date with the latest developments. The Forum not only affords the opportunity for engineers,
manufacturers and distributors to do so, but also provides a platform for them to discuss new
technologies and to extend their knowledge base.
Forum user Scott Thompson says he uses the site regularly to keep an eye on the latest developments.
I visit the Forum most days and have received really helpful advice from other designers, while I like to
think Ive been of some help to them too. The site has a good community feel and thats essential in the
electronics sector. I would highly recommend design engineers, manufacturers and distributors to join and
make the most of the resources. The more people that interact, the more useful the Forum becomes.
New Electronics group editor Graham Pitcher believes that, as social media gathers pace in electronics,
forums have become an important medium for industry to work together. Much has been made of social
networking and many of us take advantage of the features of the various sites, he said. But we tend to
use them as the name implies - outside of the office. Theres no reason, however, why we shouldnt be
networking as part of our jobs if you have a problem, someone may have the answer, saving you a lot of
development time. And thats why New Electronics has launched this online forum as part of a major
improvement to www.newelectronics.co.uk.
To register and become part of this fast growing community, go to www.newelectronics.co.uk/forum.
here are some live
forum topics. do
you have an answer?
ASIC/SoC/FPGA
Do Magma tools support the CCS model?
EDA/Board Level Design
Is it safe to build a pcb that has traces loaded
with 5A/250V ac?
Embedded Software Development
Can anyone recommend dev kits for ARM9?
Im thinking of using Linux
Legislation NEW SECTION ADDED
Whats the difference between a directive
and a regulation?
Micros
How comes 8bit micros have 16bit registers?
Mixed Signal & Analogue
How do I get more current for thermal fan control?
Power
How do I design a power supply for use in explosive
atmospheres?
Test & Measurement
Is it possible to capture quick measurement info
when saving on screen?
Other Technologies
How can I focus on the first 5Hz of an FFT?
www.newelectronics.co.uk/forum
Register now to attend the FREE Aerospace and
Defence Forum 2011. RAF Musuem, London,
9th June 2011: ni.com/uk/milaero
JOIN THE CONVERSATION: Follow us on Search niukie
>>
Buy online and explore the
range at ni.com/uk/lowcost
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ni.com/uk
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W
e may have seen a wireless revolution in the last decade, but it
has been all about wireless data. But when it comes to
transmitting power, cables are still vital. That could soon change,
however, with wireless power transmission on the agenda for a host of
electronic products.
Wireless power is a dream almost as old the generation of electricity
itself, going back to the early 20th Century, when Nikola Tesla planned to
use huge coils to transmit electrical energy through the atmosphere and
ground. In the 1960s, experiments saw mini helicopters powered wirelessly
from the ground using microwaves and lasers are being used in a similar
way today.
But it is the wireless powering of small, portable electronic products that
is seeing rapid advances and it looks certain that, within a few years, we
will not have to remember to regularly plug them into wall sockets. Wireless
power could become virtually ubiquitous.
The wireless power market consists of three main categories,
differentiated by range, power and the technology used. First is zero range,
low power, where induction is used to charge products like mobile phones. A
newer version, exploiting resonance, offers somewhat extended range. The
second, with a range of tens of feet, is based on the broadcasting of rf
energy. And the third, transmission of power using lasers, can cater for a
range of power and distance options.
One company taking the laser based approach is California based
PowerBeam, which fires laser beams at photovoltaic cells, which convert
them back to electrical energy. PowerBeam is involved with a major
electronics manufacturing company that, by Christmas 2012, will be
launching the first optical, wireless power consumer product.
Initially, both transmitter and receiver will be in a fixed location a
typical product would be a wall mounted led lamp, consuming 4 to 8W,
says David Graham, PowerBeams ceo and cofounder.
An important advance that PowerBeam is exploiting for its optical
wireless power systems is safety.
Power to
the people
Wireless data is set to be followed by
wireless power. But whats going to be the
best delivery method?
By David Boothroyd.
A decade ago, if you had suggested providing wireless power through a
laser and photovoltaic receiver combination, people would have said its
possible, but its not safe. The lasers that were available then were not eye
safe. Since then, longer wavelength lasers have become available, making
them thermal, rather than optical, devices. We realised that, by combining
such thermal lasers with some customised safety electronics, it is possible
to transfer useable amounts of power with reasonable efficiency.
Take a standard optical laser like a red laser pointer. The safe exposure
to that light is considered to be about 10W/m
2
. Operating where we are, in
the thermal wavelengths, it is about 1000W/m
2
. That is what makes laser
based wireless power feasible.
PowerBeam will initially target those products consuming less than 10W,
but as Graham says, today that power level includes many different product
areas.
There has been a remarkably consistent move towards this kind of
power requirement. For example, in illumination, incandescent bulbs have
been replaced by leds, which are 20 times more efficient. In audio,
amplifiers are far more efficient. In displays, lcds that were backlit by a
fluorescent tube are being replaced by leds and soon organic leds. This
trend makes the value of what we are doing better and better.
Going down the rf broadcasting route for wireless power is Powercast,
which is providing low levels of power using the unlicensed 915MHz ISM
band, similar to Europes 868MHz. There are several potential applications.
One is charging batteries over distance, another is to power battery free
systems, typically duty cycled devices where activity only occurs
periodically.
Large sensor networks are a key target market, because Powercasts rf
wireless power makes it feasible to create networks with thousands of
sensors. Benefits of this kind of wireless power include cutting operating
costs by eliminating wiring and the expense involved in changing batteries.
It also helps make systems more reliable because they can be sealed, and
potential user damage is eliminated. Placement flexibility is increased and
charging becomes automatic, taking place as soon as the device is in range.
Powercast has two commercially available components: its
Powerharvester receivers, designed for use by OEMs; and Powercaster
transmitters, which send rf power.
Our rf technique is inherently a one-to-many technology, with one
transmitter powering multiple receiving devices, says Harry Ostaffe,
Powercasts vp of marketing and business development.
We put ourselves into two categories: one being delivery of wireless
power; the other is micropower energy harvesting. The latter would compete
with energy harvesting techniques like solar, thermal and vibrational.
Micropower typically means less than 1W, usually milliwatts or microwatts.
In terms of range, Powercasts systems today reach to around 15m, but
Cover Story Wireless Power
Qualcomm is working on a number of ways
to supply power wirelessly, including
charging mats for homes and cars (above
right) and a charging accessory (left).
Far left: Qualcomm is also using near field
magnetic resonance to transfer energy over
5 or 6cm; in this instance, providing enough
power to operate a light bulb
the company has just released a new wireless sensor product that has a
range of 20m.
Our goal is to increase range by up to four times with every generation
of component. Its challenging because, as the distance grows, the available
power drops off with the inverse square you get a quarter of the power at
double the distance.
At the heart of Powercasts innovation is the rf sensitivity of the
conversion technology itself, which transforms the rf signal into dc.
We have developed an rf to dc technology that works over a fairly wide
frequency band and a wide range of input powers, and the secret to what
we have done lies in the topology of how we convert the rf into dc, which
enables us to maintain the efficiency of the conversion over a wide
operating range. Other approaches may achieve high efficiency but it is over
a narrow range of operating conditions. The benefit is that someone can
take one standard component and design it into a lot of different
applications, whether it is high or low power.
Ambient energy harvesting
Powercasts other approach to wireless power is ambient energy
harvesting, in which battery powered portable products like phones and
notebooks could supply wireless power to other devices near them.
We have demonstrated powering the sensor featured in our
development kit from an iPhone, Ostaffe says. A lot of phones today have
Wi-Fi and the 2G mode is in the high 800MHz band. That could easily be
shifted with an app to send out power at 915MHz, for example, or 868MHz.
Magnetic induction is arguably the most commercially advanced of the
wireless power technologies and is being used in objects like electric
toothbrushes and some mobile phones, with more devices planned.
Products like Powermat (from the firm of the same name), and eCoupled,
from Fulton Innovation, prove it works. Recently, Fulton demonstrated a
wireless powered kitchen blender, as well as packaging that can light up
and flash on a shelf without batteries. Fulton is a founder member of the
Wireless Power Consortium, which has developed the Qi standard for
interoperability of wireless devices powered through induction.
Induction exploits the fact that a fluctuating magnetic field from a coil
can induce an electric current in another coil placed very nearby. It works
well with close contact, but there is a drawback efficiency can fall to zero
at even a few millimetres from the transmitter.
One way to overcome this is to exploit resonance. In a system
developed at MIT, an inducting coil is connected to a capacitor and
the energy within this circuit oscillates rapidly between an electric
field in the capacitor and a magnetic field in the coil. If the oscillation
frequency in the transmitters circuit is different from the receivers,
they are non resonant, limiting the build up of energy inside the
receiver. But if they are made resonant, the oscillating fields of the
two coils would be synchronised, increasing the energy transferred.
By exploiting resonance, the MIT team transmitted 60W across
2m with an efficiency of 40%. The idea is being developed by a
company called WiTricity, which has powered a 50W tv located 0.5m
from the power supply, with 70% efficiency. In some cases, the
improvement in the efficiency due to resonance can be more than
100,000 times that of non resonant induction, MIT says. And, unlike
laser based line of sight energy transmission, a magnetic field is not
focused and so can pass around or through obstacles between the
transmitter and receiver.
A similar approach is being developed by Qualcomm, which calls it near
field magnetic resonance. Mark Hunsicker, senior director of product
management for Qualcomms wireless power solutions, explains. Our
technology provides a solution that allows a freedom of placement and
design, in that we can power through surfaces. The technology can be used
to provide hundreds of watts, if not more, but for our first commercial
offerings we are focusing on 20W or less devices such as tablet
computers, smartphones or remote controlled devices. It permits a varying
antenna size, which means our target devices can be of various sizes,
creating a zone based charging approach that could power phones, a tablet,
or Bluetooth headsets.
Alternative approaches require direct contact or to have a maximum of
a few millimetres between transmitter and receiver. We can charge over
distances of 50 or 60mm and antennae can be embedded in desktops,
furniture, vehicles, with no requirement to position devices in any
particular way.
Qualcomm moved into wireless power because we anticipated the
smartphone market would need not only low power semiconductors, but
also much better access to charging making it ubiquitous and natural. We
felt it was important users do not have to do something special to charge
their devices. They can just drop them on the charging mat, or get in the car
and drop them in the trinket tray and they can move around, there is no
need to fix them rigidly.
Initially, when we looked at the market, we felt you would have multiple
receivers per charging transmitter. Now, we are thinking of the converse;
multiple chargers per receiver your phone gets charged in the bedroom,
the bathroom, the car, the office, the conference room and so on.
As Powerbeams Graham says, power is now going down the same
wireless path that data has already trodden.
A lot of the technology base that has gone into data communication is
going into transferring power. For example, the class of lasers that we use
was used initially for pumping optical amplifiers so a signal could be
transmitted over a great distance. Power is about 25 years behind signals.
Clearly, we will obviously continue using wires for heavy power loads. But
elsewhere, when a wire becomes a constraint, it will go away, he
concluded.
Cover Story Wireless Power
Our technology provides a
solution that allows a
freedom of placement and
design, in that we can
power through surfaces.
Mark Hunsicker
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P018_NELE_MAY24 18/5/11 11:32 Page 1
Sector Focus Expert Panel
C
ircuit designers are rapidly coming to
terms with the idea that it is impossible to
build error free chips. The solution is fault
tolerant architectures, combined with
mechanisms for detecting and repairing errors,
or at least mitigating their impact. New
Electronics talked to three experts in the field to
find out how they are addressing the issues.
At the recent DATE 2011 conference in
Grenoble, fault tolerance was a recurring theme.
One popular tutorial was Architectures for
online error detection and recovery in multicore
processors. Organiser and moderator Dimitris
Gizopoulos, from the University of Athens, said
the move to nanometre geometries and the
complexity it brings is threatening the reliability
of future devices. He identified three causes for
this vulnerability.
First, there are environmental disturbances
that produce transient or soft errors, he said.
For some years, device manufacturers have
been aware that, with the shift to deep
submicron geometries, naturally occuring alpha
particle radiation can impact memory and logic
circuitry. The most common soft error is a bit
flip in memory devices, whereby a 0 becomes a
1 or vice versa. System crashes, data corruption
and system resets are a real risk.
The second factor is latent manufacturing
defects. Variability in advanced processes
causes heterogeneous operation of identical
components on the same chip, he explained.
Multicore microprocessors and memories are
manufactured using inherently unreliable
technologies. Process variation leads to
changes in circuit parameters which, if
undetected, can mean at best, unpredictable
behaviour, and at worst, component failure.
Inevitably, it leads to reduced yield, increased
cost and delays. Allied to this, aging
phenomena, more common as geometries
shrink, are increasingly producing permanent,
hard errors causing digital circuits to fail over
time.
Then there are verification inefficiencies
that allow significant design bugs to escape into
the system, Gizopoulos continued. Due to the
extreme complexity of multicore processors and
the pressure towards reduced time to market,
even after comprehensive presilicon verification
and post silicon validation, major design errors
or bugs may be missed.
While complex multicore devices are
regarded as part of the reliability problem, they
are also inspiring some innovative potential
solutions. Spare resources are inherent to
multicore designs and these are being exploited
successfully, together with the application of
evolving error detection, recovery and repair
schemes, to make faulty devices usable,
improve reliability and provide predictable
operation.
Salvage operations
Intels Arijit Biswas has been researching core
salvaging techniques, designed to reduce the
Scrapheap challenge
Fault tolerant design will allow defective multicore chips to be used,
rather than scrapped. By Louise Joselyn.
Sector Focus Expert Panel
scrapheap of devices with defective cores.
Multicore devices can be dominated by regular
memory structures, mainly caches, he
explained. Fortunately, caches can be
protected from manufacturing defects using
well tried and tested techniques.
CPU cores are the vulnerable area now, he
said. In the past, we had only one solution:
throw out all defective parts. But recent work
has shown that, properly managed, defects can
be tolerated. One obvious solution is to disable
defective cores, Biswas explained. Core
disabling reduces the sales price as a four core
part becomes a two core part, for example. Core
sparing a standby core is another option;
like redundancy, this consumes precious die
area, while providing no performance or
economic benefit in a non defective die.
A more desirable option is core salvaging,
which allows defective cores to continue
operation. Biswas said most modern cores
contain large amounts of redundant logic, which
could be used to compensate for the defective
logic. The key is to be able to detect the defect
to a finer granularity than just a core, he said.
Microarchitectural core salvaging techniques
disable defective execution pipelines or
schedule operations on alternate or spare
resources, thereby avoiding using the defective
area. By exploiting microarchitectural
redundancy, this technique relies on the cores
ability to execute the enire instruction set
architecture (ISA) correctly, even in the
presence of certain defects. Biswas research
team found, however, there are few
opportunities to use this approach, because
large portions of many redundant structures
comprise non redundant logic,
such as decoders, buffers and
interconnect. Further, the
technique requires a significant
overhead.
Architectural core salvaging,
by contrast, considers resources
outside the core and the fact that
a single core need not be ISA
compatible, providing the cpu, as
a whole, is. Crucially, if a defect
means that a core cannot execute
certain instructions, the core can
still be used if we can detect and
move the unexecutable
instructions to a different core.
Certain defects, such as the inability to execute
memory operations, will render a core useless.
Most ISAs contain numerous instructions which
are used infrequently, yet occupy significant
area SIMD instructions are a good example, he
added. In certain cases, it is
possible to trap such an
instruction and migrate the
thread to a good core.
The way to better exploit the
technique, says Biswas, is to
ensure better thread
scheduling and thread
swapping algorithms.
Architectural core salvaging
becomes compelling as the
number of cores on a device
increases. Beyond five cores,
Biswas maintains, the
performance drop from using
architectural core salvaging will
be less than 5%. And the technique is
orthogonal to core sparing, he concluded.
Growing old gracefully
Graceful chip degradation is the aim of the CRISP
(Cutting Edge Reconfigurable Ics for Stream
Processing) consortium. This EU funded project,
led by Dutch dsp IP specialist Recore Systems,
demonstrated a self testing, self repairing nine
core chip at DATE. Gerard Rauwerda, Recores
CTO, said the key to the CRISP technique is the
use of dynamically reconfigurable cores and
resource management at run time to exploit the
natural redundancy in multicore designs. A key
innovation is the Dependability Manager, a test
generation unit which accesses the built in self
test scan chain to effectively perform
production testing at run time. This determines
which cores are working correctly, he
explained.
To do this, the consortium has created an IP
wrapper around Recores reconfigurable dsp
core. The addition of multiplexers allows the
software to switch from functional mode to
diagnosis mode to detect faults. There are
some timing issues to consider, Rauwerda
explained, as the circuitry is running at, say,
200MHz online, instead of 25MHz offline.
Once the device has been analysed, the run
time resource manager reroutes tasks to error
free parts of the chip, effectively repairing it for
continuous operation.
For the demonstration, the CRISP software
was running on an ARM9 device, accessing a
matrix of dsp cores, but Rauwerda said the
technique could be applied to a variety of cores
in a truly heterogeneous SoC; even in 3d
stacked chip devices.
Currently, CRISPs approach will determine
unusable faulty cores and, if only the logic part
of the core is affected, whether the cores
memory might still be usable. In the future, the
aim is to diagnose to a deeper level, to see if we
can use more parts of a faulty core, Rauwerda
concluded. A fault tolerant interconnect is going
to be very important. We will need to insert test
structures into the network on chip
interconnect IP for better diagnosis.
Rauwerda: In the
future, the aim is
to diagnose to a
deeper level, to
see if we can use
more parts of a
faulty core.
Gizopolous:
Multicore
microprocessors
and memories are
manufactured
using inherently
unreliable
technologies.
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P022_NELE_MAY24 18/5/11 12:10 Page 1
Stacking the deck
Technology Watch Introduction
Scaling chips designs to follow
Moores Law has a finite life. As
a way around the roadblock,
companies are now looking to
build upwards, creating stacks
of interconnected dies.
Digi-Key is pleased to
partner with New Electronics
to highlight to UK electronics
designers the benefits of
stacked packages.
Mark Larson,
President, Digi-Key
W
hen you start thinking about how electronic devices can be
manufactured with feature sizes of 20nm, your head begins
to hurt. And with good reason. The engineers who developed
these processes have seemingly defied reason; making devices
operate using just a handful of atoms per transistor.
Obviously, scaling cant continue as it has over the last four
decades but that wont stop engineers trying. As it stands, it looks
like CMOS will shrink to the 10nm node using structures such as
finFETs; beyond that lies uncertainty. In fact, some academics doubt
that electronic devices as we know them today can be built with
features smaller than 10nm. Calling it intrinsic unmanufacturability,
Prof Mike Kelly of Cambridge University points to the effects of
variability. Once, this was just the random distribution of dopants; at
10nm, its the shape of features themselves.
The situation is complicated by the growing popularity of
systems on chip, or SoCs. Many of these include analogue circuitry,
which doesnt take well to being ported to smaller technology
nodes.
So what is an industry, whose very nature is to make smaller,
faster and less expensive devices, to do? The answer or one of the
answers is to go upwards, creating a new version of the multichip
module.
Stacking isnt new, of course. But if youre trying to stack a
number of very small dice, you run into interconnect problems the
perimeter of the chips simply isnt large enough. The solution is to
use vias copper columns drilled through the chips as the
interconnect.
But all this is expensive. Will companies be prepared to foot the
bill? Time will tell.
Graham Pitcher,
Editor, New Electronics
As an extension of its commitment to providing top quality product, Digi-Key is pleased to partner
with New Electronics to provide relevant, useful information to UK engineers.
M
oores Law has been in danger
for some years now, but claims
of its demise remain
exaggerated. Even with optical
lithography, manufacturers reckon there
is a reasonably clear path to 16nm and
evidence that structures such as finFETs
could be good down to 10nm. But, after
that, things get fuzzy.
More than six years ago, NEC
developed a transistor that was just 5nm
long. Its leakage was so high that it
basically switched from on to a little less
on. But it had a performance curve that
confirmed transistor behaviour,
demonstrating that a 5nm transistor could
be made, even if it might not demonstrate
desirable behaviour.
Professor Mike Kelly of the Centre for
Advanced Photonics and Electronics at
the University of Cambridge believes such
a device lies in an area of intrinsic
unmanufacturability, something that will
happen as we approach 7nm design rules.
volumes measured in tens or hundreds of
millions to achieve a worthwhile payback.
Variants for subtly different applications
are out of the question.
In 1998, Bob Payne, then strategic
technology vice president for VLSI
Technology, raised the prospect of
deconfigurable design as a way to fix the
so called design gap that appeared in that
decade. In an industry that strove to find
ways to squeeze more onto a chip, most
competitors thought the idea outlandish.
Yet platform based design, using IP blocks
picked from a widely applicable superset,
is now comparatively commonplace and
cited by people such as Synopsys CEO
Aart de Geus as the prime solution to
closing the design gap.
In platform based designs, unwanted
IP cores never make it onto the final
silicon. But if you have a market where
silicon built on the latest processes can
only be supported by massive markets, it
makes sense to use the available space to
build in everything you might need, along
with the kitchen sink.
All this assumes that circuits scale
linearly with process generations.
Analogue circuitry most definitely does
not: in fact, it can get bigger. Companies
generally work around this by shifting
more of the burden into digital [Digital
Takeover, NE, 22 November 2010].
However, if the analogue section forms a
significant fraction of the die, it provides
an argument for not shrinking the design .
The shrinkage of the digital section will
yield a smaller die, allowing more to be
packed on a single, fixed cost wafer. But
wafer processing costs increase with each
new generation and if you are not getting
a two fold density increase from a move to
a more advanced node, it can be hard to
justify the decision.
3D integration or
More than Moore, as it
is becoming known is
the successor to the
multichip modules
shown above. This
technology was
introduced more than
20 years ago
The big problem, according to Prof
Kelly, is variability already an issue in
chip manufacture. Today, it is largely
related to the way that dopants are
arranged in a crystal. At sub 50nm design
rules, random variations in dopant
concentrations can shift properties, such
as threshold voltage, to the point where
many transistors no longer switch.
At less than 10nm, the size and shape
of the core structures themselves become
problematic. In a dot that nominally
measure 3nm across, the variation
between neighbours is more than 10%,
making it very difficult to guarantee
correct operation without some form of
tuning which would take up extra space
and defeat the object of making the core
devices smaller.
On this basis, 2D silicon scaling has
around another 10 years if you can
justify the humungous cost of designing a
multibillion transistor chip and its
associated masks. It will take guaranteed
A new degree of freedom
The digital section could still benefit
from the shrink, if you have good, short
connections to an analogue section built
on an older, cheaper process. This is where
you can use the successor to the
multichip module, introduced more than
20 years ago. Now, it is known as 3d
integration or more than Moore, rather
than more Moore, as it is known by some
European research programmes.
3D integration is far from new. Demand
from the phone makers for denser
memories convinced packaging
companies to invest in equipment that
made it possible to stack chips on top of
each other. A dizzying array of stacked
chip techniques was developed, some
even stacking packaged chips. This
package on package (PoP) construction
made it easier to test devices fully before
they were assembled into the stack
overcoming one of the critical problems
faced by all types of 3d packaging: how do
you maintain a high yield?
If you assemble untested dice into a
multichip module, the probability of each
one causing the assembly to fail rises
dramatically. With a die yield of 90%, the
probability of a critical failure within the
stack rises to one third with four devices.
The industry responded by selling
known good die (KGD) unpackaged
chips that have passed wafer level tests
and a series of screening options. These
parts can be forwarded to regular single
die packaging as the cost of those failing
after test and burn in is much less.
Memory has one further advantage in
multichip modules: you can use
redundant bit and word lines to recover
parts that would fail if you needed the
memory cells to be 100% functional.
Because effective yields are relatively high
in volume memories, it makes sense to
stack them. The question then becomes
whether it is worth adding processors and
analogue devices to the stack. Good
reasons are appearing.
Todays memories are not designed
with many I/O pins. Instead, they use
heavily pipelined, high clock rate
interfaces that transfer multiple bits per
cycle. This comes at a cost: power
consumption.
At the 2007 Design Automation
Conference, Intels microprocessor
research director Shekhar Borkar painted
a stark picture of what would happen with
power consumption in future massively
multicore processors. Interprocessor
communication would dominate the
power equation but some 25W
significant, even in todays server
processors with a power envelope of
150W would come from powering the
memory bus I/O pins.
Most power is consumed by driving
relatively long, high capacitance PCB
traces. If memory is closer to the
processor, the parasitics are cut
dramatically. IBM has done this in its
current generation of mainframe
processors, using embedded DRAM
instead of SRAM. The smaller memory cell
makes it possible to double the amount of
cache memory local to each processor
core for the same die area. According to
IBM fellow Subramanian Iyer, the largest
computers save up to 1.5kW in power
from this larger cache as it reduces the
number of accesses to main memory.
The next step is to bring off chip
memory closer. You could take existing
memories and place them side by side on
a conventional chip package substrate
with a redistribution layer or stack them
using todays wirebonding technology. The
reduction in wire inductance from that
alone would bring substantial power
savings. But there is not enough space
along the chip edge to support higher
bandwidth.
Because driving signals
over long, high
capacitance PCB traces
consumes a lot of
power, it makes sense
to bring processors and
memories together in
the same package. But
the question of whether
the memory or the
processor should be on
top remains
Chip makers are moving to the third dimension as they create the
successor to the multichip module. Chris Edwards explores the options.
Technology watch: 3D Trends
Fig 1: A 3d stacked chip with the processor on top
Processor die
Die to die interconnect
approx 50m pitch
TSVs
Solder bumps
186m pitch
Thinned memory die with TSVs
Laminate
Heat sink
26 www.newelectronics.co.uk
One method might be to use the entire
top surface of the memory die for
processor I/O and flip it so it sits on top of
the processor. This provides an entire
DRAMs worth of additional tightly coupled
memory that can take advantage of more
I/O pins to run the memory interface more
slowly. There is a catch: processors run
much hotter than memories. DRAMs do
not cope that well with heat and the
arrangement would reduce the
effectiveness of the heatsink on top of the
processor-memory stack massively.
Borkar proposed an alternative: sit the
memory underneath the processor and
drill holes to take conductive vias through
the DRAM to support connections from the
system to the processor (see fig 1). Once
one set of holes has been drilled through a
die, you could go further and drill them
through multiple DRAMs, providing the
ability to stack a large amount of memory
in one package. This is where IBM is
looking to move its mainframe processors;
These place big roadblocks in the way of
the metal word and bit lines that wire up
the individual bits of a DRAM or flash
memory. You can work around this by
splitting the memory into smaller blocks
so they fit between the TSVs but, although
this helps reduce word- and bit-line
parasitics, it reduces memory density.
Iyer claims it is possible, with some
work, to reduce the die-area overhead to
around 5%, but this cost needs to be
factored into the overall price of the 3d
stack. On top of this, you have to factor in
the cost of processing wafers for TSVs so
they are ready for stacking. Estimates
vary, but the most optimistic place it at
around 5% of the cost of a fully processed
CMOS wafer, not including the cost of
testing something with a lot of hidden I/Os.
That, in turn, will place the burden of test
on built in self test (BIST) and more
advanced scan based algorithms.
Although companies such as Toshiba
have successfully demonstrated the
manufacturing viability of TSVs in image
sensors putting the processing
electronics directly underneath a CMOS
sensor via yield is a major concern.
Reactive ion, or dry, etching has proved
startlingly successful. It can bore deep
holes through a silicon wafer with very
little spreading at the top of the hole.
Unfortunately, it is not so easy to fill the
hole with a conductor. Although dry
etching can produce holes with extremely
high aspect ratios, filling those holes with
conducting materials means the wafer has
to be thinned, which makes handling more
difficult.
When the 130nm node was
introduced, improperly filled contact holes
quickly became one of the most likely
sources of chip failure. The response was
to double up on vias wherever possible
Above: There are three
basic approaches to
creating TSVs: via-first;
via-middle; and via-last
Intels future high end x86 devices may
follow.
Companies such as Samsung have
proposed using the same concept for
mobile phone processors. According to
Samsung, a shift to stacks that use
through silicon via (TSV) connections
could halve power consumption. As a
result, Jedec subcommittee JC-42.6 is
working on standards that will allow
memories made by different vendors to be
assembled in stacks, without demanding
custom designs for each one. The effort,
part of the DDR3 and DDR4 standards
initiatives, will lead to the use of much
wider I/O buses as you can, in principle,
get many more TSVs onto a die than
wirebonded connections. DDR4 is likely to
be the first memory interface standard
that supports 3d stacks from the start.
There is another catch: if you want to
maximise the die-area efficiency, the last
thing you want to do is drill 5m holes
through the chip at regular intervals.
24 May 2011
You could take existing memories and place them
side by side on a conventional chip package
substrate .. but there is not enough space along the
chip edge to support higher bandwidth.
Fig 2: TSV manufacturing options
TSV diameter <1m, aspect
ratio approx: 10:1
TSV diameter 1 to 10m,
aspect ratio less than: 10:1
Front end of line and
back end of line
Back end
of line
Front end
of line
Front end of
line and back
end of line
TSV diameter 10 to 100m,
aspect ratio less than: 5:1
Above: TSVs are large in
comparison to device
features and bring
routing problems
using statistics to fix a manufacturing
problem on the basis that two
neighbouring vias were unlikely to fail.
Redundancy is likely to be a major
concern for TSV based stacks, which will
further eat into die area efficiency.
How and when you create vias
presents the industry with a headache. It
is not just a matter of drilling holes, filling
them with copper and wiring them up. The
decision of when in the process the TSV is
created has a major impact.
There three basic approaches: via-first;
via-middle; and via-last (see fig 2). On
cursory inspection, via-first looks easiest
take a virgin wafer, drill holes in it, fill
them with metal, then go about making
the transistors that surround them.
Unfortunately, it is not that simple; CMOS
transistor fabrication involves very high
temperatures that will disrupt any metal
interconnect. In conventional chipmaking,
interconnect fabrication uses much lower
temperatures after the core transistor
structures are formed. So, instead of
copper, you have to use a material such as
polysilicon, which has lower conductivity.
The filled holes put additional stress on
the wafer, making it hard to keep it flat.
This, in turn, makes it hard to image
patterns on the wafer because the depth
of field of an optical stepper is so small
[Fractured Future, NE 10 May 2011].
The via-middle process works around
this by constructing the transistors first,
then forming TSVs before the metal
interconnect layers are laid down.
However, this means the foundry has to
deal with processes that are more familiar
to packaging houses.
The via-last option makes it possible to
have wafers made at a front end foundry,
then take them elsewhere for the TSVs to
be inserted as a final step before
packaging. Although it makes introducing
TSVs to an existing manufacturing flow
easier, the contacts can only be connected
to the top layer of metal so the via acts
as a 10m obstruction to any routing in
lower, much finer metal layers. This, again,
will reduce the effective density of any
device, particularly logic chips which are
often limited by routing congestion.
Although challenging, via-middle looks
to be the best compromise. Even then, you
have to take into account the effect of
implementing keep-out zones around the
TSVs to avoid stress changing the
properties of transistors. Work by IMEC
and Synopsys, amongst others, has
shown these zones can be quite large
and need to be much bigger for analogue
circuitry. Digital keep-out zones can be
from 5m to 20m around the TSV; the
analogue no mans land is up to 200m.
However, if analogue circuits are on older
processes, their relative die-area cost will
be much lower.
You then have the question of how 3d
stacks are formed. For maximum
throughput and, in principle, minimum
cost, assembly is done on a wafer by
wafer process. There are two main
objections to this. One is that you need the
dice to all be the same size this is not
going to work for standard memories
unless all chipmakers addressing the
mobile phone market suddenly agree on a
common die size for their processors.
The other obstacle is not being able to
screen out failed devices until the end of
the process. You are, once again, back to
the yield collapse that faces any stack that
does not use KGD. As a result, although
throughput is lower, die to die stacking is
likely to be the approach most commonly
used for all but the most cost sensitive
applications.
When you consider the extra costs all
those extra 5% costs soon add up 3d
integration has some big hurdles to
overcome.
[creating] vias presents the industry with a headache. It is not
just a matter of drilling holes, filling them with copper and wiring
them up. The decision of when in the process the TSV is created
has a major impact.
Fig 3: TSVs are large in comparison to device features
S
i
n
g
l
e

d
i
e
Landing pad
Liner
Device
Via first
TSV
Via last
TSV
Technology watch: 3D Trends
P
rior to the launch by IBM of its
System/360, there was no
consensus on what should be the
basic word-length of a computer.
According to Werner Buchholz credited
with coining the word byte with a y to
prevent accidental mutation to bit the
plan was to make what is now a basic
unit of computing much more flexible.
During the development of Stretch
System/360s predecessor a byte could
be any packet of bits from one to eight.
The Stretch architecture made it possible
to address memory down to the bit level.
But Stretch was expensive and IBM
needed a cheaper way to build a
mainframe. One of the casualties was the
programmable byte: the engineers settled
on 8bits as the best compromise. Since
then, we have constructed data types on a
byte-by-byte basis, not because they
were the best options, but because they
offered the greatest memory efficiency.
From that basic word, we obtained the
core datatypes of C, such as the short, int
and long, together with a not entirely
consistent interpretation of how they
should be implemented. Typically, an int
is the natural word-length of a processor:
for example, 4bytes on a 32bit machine.
However, this is not generally the case on
an 8bit microcontroller, as an int with a
maximum range of 256 values has
limited usefulness.
Instead, an int will often be defined to
be 2bytes long. This can lead to
performance problems if int variables are
used indiscriminately in a program,
because 2byte operations are often
much slower than native 8bit
instructions. For loop counters and
values known to have a small range, it
often makes sense to declare them as
char, but not short, variables. Somewhat
in unsigned form, if you assume the use
of byte-wide variables.
The data in an int does not have to be
an integer. The radix point can be
anywhere inside the variable the
programmer just needs to understand
where it is and scale values as needed.
The twos complement scheme still
works for these formats.
Despite its efficiency, the widespread
use of fixed-point twos complement
representations followed some years
after the development and use of its
main numeric counterpart: floating-point.
It was not until System/360 arrived that
twos complement began to spread
across the industry.
More than 20 years earlier, in the late
IBMs System/360
mainframe is
considered by many to
be one of the most
successful computers
in history. Apart from
influencing computer
design, it also
introduced the 8bit
word.
confusingly, short and int datatypes are
generally both 2byte.
A long is twice the size of an int. The
C99 standard also has the concept of the
long long: as you would expect, it has
double the bytes of a long.
Because of the ease with which you
can implement addition and subtraction
for signed numbers, twos complement is
the method generally used to encode
negative numerals. Generated by
inverting each bit position and then
adding one, the addition of a pair of twos
complement variables provides the same
bit pattern as the addition of two
unsigned numbers with equivalent bit
patterns. For example 1 plus -2 provides
the value -1 in twos complement, or 255
All about the numbers
1930s in Berlin, Konrad Zuse built the Z1,
a binary mechanical computer that used
floating-point arithmetic, a format that
splits the datatype into three parts to
allow a much wider range of numeric
values to be stored, albeit with less
overall precision at very high and low
values, the gap between numbers
becomes somewhat larger than a
equivalent, very long fixed-point
representation.
Of the three parts of a floating-point
number, the first typically a single bit
holds the sign bit. The second is reserved
for the exponent. In todays machines, a
single-precision, 32bit floating-point
number a float in C stores the
exponent as an unsigned 8bit value.
There also has to be a way of
representing negative exponents. Instead
of using a value based on complements,
the number is biased. In todays floating-
point formats, the exponent has to have
127 subtracted from the stored byte to
come up with the right value. So, a value
of 129 gives you an exponent of two. As a
result, positive exponents have a leading
1, rather than negative numbers in twos-
complement form.
The remaining 23bit of a single-
precision number is used for the fraction,
or mantissa, the number to be multiplied
by the exponent to give the actual
number. But there is a further
complication: numbers are normalised, so
they are always represented as 1.f, where
f is the fraction. This makes it possible to
leave out the leading one and, in effect,
store 24bit of data using a 23bit value.
Normalisation introduces an
overhead, although this is only apparent
in software-emulation libraries, as
hardware can perform the search for the
leading bit very quickly. Because of
normalisation, it is also necessary to
compare exponents as well as mantissas
to ensure the right result, even when the
two values are close to each other.
Although floating-point numbers are
stored differently to fixed-point, many
processors will convert them on the fly
so they can use twos complement
arithmetic to process them. Andrew
Donald Booth developed an efficient way
of multiplying numbers represented by
twos complement in 1951 (see fig 1).
Since then, many presentations at the
International Solid State Circuits
Conference and other seminars have
covered high-speed floating-point units
that use variants of Booths algorithm.
For years, computer makers developed
and used their own floating-point
representations, which made it difficult to
port code between architectures,
particularly as certain combinations of
mantissa and exponent are often used as
special numbers, such as infinity, and
error codes to flag up potential problems.
In the mid-1980s, while developing the
8087 coprocessor, Intel proposed the idea
of developing a standard for floating-point
numbers. This turned into IEEE754, which
is now used by practically all
microprocessor-based implementations.
The standard defines several precision
classes, such as the 32bit single-precision
and the 64bit double-precision formats, as
well as infinity, positive and negative zero
and the not-a-number (NaN) code. The
NaN can be used by programs to catch
errors using a simple trap handler in place
of more extensive checkup code.
In IEEE754, special numbers sit at
either end of the exponent scale. For
example, in a single-precision float, the
maximum exponent is limited to +127
using a bias value of +127 so that 128
can be used to encode infinity and NaN
codes. At the other end, -127 (encoded as
zero in the exponent field) is used to
denote zeroes and numbers that do not
have normalised mantissa values. These
subnormal or denormalised numbers
The decision to base all datatypes on fixed 8bit chunks was more to do
with cost cutting than analysis. Chris Edwards explores numerics.
Technology watch: Numerics Refresher
Fig 1: A 32bit multiply using Booths algorithm
Add multiplicand to
the left half of the
product and place
the result in the left
half of the product
register
Subtract multiplicand
from the left half of the
product and place
the result in the left
half of the product
register
Start
Done
Shift the product register right by 1
Test multiplier [i : i - 1]
= 32 rep
<32 rep
01 10
00 11
often called denormals by programmers
help to handle underflow.
Without denormals, you cannot
represent a number smaller than 1.0 x
2
127
. Any result smaller than that would
be converted to zero during the
normalisation stage used to keep the
significand in its 1.f form. Gradual
underflow loosens this restriction and
makes it possible to represent
significands in the form 0.f when the
exponent is zero.
There is a catch with gradual
underflow: most hardware floating-point
units do not support it directly. Instead,
they trap to much slower software
handlers. Even in architectures with
hardware support, gradual underflow can
be slow. Very often, denormals will be
seen during software profiling as sudden
dips in performance. As a result, they are
very unwelcome in most embedded-
control and signal-processing situations.
Because high-level software tools,
for custom datatypes. Low-energy
processors will also benefit from less
overhead in numeric processing.
At Imperial College, Dr George
Constantinides has been working on
numerical analysis to focus high precision
only where it is needed. Large savings in
die space can be made by operating in the
fixed-point space and tuning the word
width at each point in the algorithm to use
only as many bits as are necessary.
The downside is this puts the onus of
numerical analysis working out exactly
how much precision is needed on the
system developer. Given the trend is
towards automatically generated code
and floating-point formats are easier to
deal with as they do not need the radix
point to be adjusted manually in the way
that fixed-point formats do only
systems that need high die or energy
efficiency will go down this road.
However, more automated analysis of
numeric formats should be achievable. Dr
Constantinides has used linear system
theory to analyse the impact of datapath
error as noise and calculate the error that
is injected by quantising to different
levels of precision.
An alternative is to move into different
number systems, such as logarithms.
Code that needs a lot of sequential
multiplies will benefit from a move into
the log space, although errors introduced
by converting from linear to logs have to
be taken into account.
Despite the long history of standard,
byte-oriented formats, there is still plenty
of space to be explored in numeric
formats, particularly in embedded
sensor-based systems that have to take
energy and die cost into account, rather
than the design considerations of a 50-
year-old mainframe architecture.
Above left: While
developing the 8087
coprocessor in the mid-
1980s, Intel proposed
the idea of developing a
standard for floating-
point numbers. This
turned into IEEE754.
such as Matlab and Simulink, generate
code intended to run on IEEE754
compliant hardware, embedded
coprocessors [generally] implement
practically all of the standard.
However, NaN and underflow should
only arise as errors in control algorithms,
so it makes sense to perform bounds
checks on values in the loop, rather than
risk a trap to underflow handling that
may disrupt the systems performance.
Another trick is to use a denormal killer:
a constant that, when added and
subtracted from the mantissa will,
because of its limited resolution, leave it
set to zero if it has underflowed.
Custom processors provide the
opportunity to streamline the formats if
gates are scarce, even offering scope for
breaking with byte-oriented datatypes.
Because of its relatively poor density
circuits often take up 20 times more die
space than hardwired implementations
programmable logic is a good candidate
For years, computer makers developed and
used their own floating-point
representations, which made it difficult to
port code between architectures
Technology watch: Numerics Refresher
Fig 2: IEEE754 data formats
Mantissa Exp s Float
23 8 1 Bits
Mantissa Exp s Double
52 11 1 Bits
Mantissa Exp s Long double
112 15 1 Bits
Fig 3: Bias values for IEEE754
Double
+1023
Float
Bias
Long double
+16383 +127
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T
he interest in medical technology is growing
at an astonishing pace, probably even faster
than the technology itself is being
developed. Many medical devices, assisted living
products and monitoring devices are making
more and more use of radio technology to assist
in their operation, particularly in the transport of
data. This has resulted in many of the companies
driving these products looking to develop
protocols and standards to improve their
interoperability and to their ensure designs are of
the highest quality.
As well as the wide variety of technologies
covering both functionality and communication
which are available for the designer to support
their medical device platform, the market is also
seeing a number of innovative products which
contain multiple communication transports. This
convergence of technologies opens up endless
possibilities for enhancing the support and care
for patients.
It is already common for the consumer to have
their own devices at home for monitoring health
aspects, such as blood pressure or blood sugar
monitors, and these are readily available in many
high street stores. These are the simple
traditional home products which tend to have a
singular application without any means of
recording and forwarding the data.
However, the growth of wireless technology
has seen these products increasingly incorporate
such technology in their function. So how does
the inclusion of wireless technology assist the
patient and the health professional? In a simple
example, a patient could perform their own
assessment at home; for instance, taking a blood
pressure measurement, performing a glucose
test or simply weighing themselves. The data
would be obtained locally; in the example of blood
pressure, the patient would use a blood pressure
meter which incorporates a communication
transport such as ZigBee or Bluetooth wireless
technology. At the conclusion of the
measurement, the data would be sent to a base
hub situated in the users home which, in turn,
forwards this to a health professional via the
telephone network or via a broadband connection.
It is not difficult to see that the designers of
these products are playing an important part in
easing the burden on the patient and the health
services supporting this care. However, the design
of such a product is only one part of an intricate
process of getting the product to market.
In addition to the design, there are
certification and regulatory requirements which
usually have to be satisfied before the product
can be placed on the market. The regulatory
requirement is a legal requirement of the domain
in which the product is to be placed, whereas
certification is usually a (non legal) requirement
of the organisation which owns or manages the
intellectual property of the technology being
employed in the product.
The level of compliance which needs to be
applied is dependent on the functionality of the
product and the technology it employs. Take, for
example, the development for the European
market of the blood pressure monitor mentioned
above. In order to be placed on the European
market, this would have to satisfy the
requirements of the Medical Device Directive. This
Directive covers a multitude of medical products
Research & Development Directives & Standards
The Directives and standards which designers need to keep in mind when developing
devices for medical applications. By Joe Lomako.
Health checks
Research & Development Directives & Standards
and a common route for medical electronic
equipment is to test to the IEC/EN 60601-X-X suite
of standards. These standards address a number
of requirements such as safety, EMC and usability
and the specific standard to be applied depends
on the function of the device. A clinical evaluation
of the product may or may not apply; this again is
product and placement dependent and there are
professional bodies in existence which can offer
advice on which procedures apply.
This process is usually the first tier of the
compliance process. The blood pressure monitor
also contains an rf device, which introduces
another tier of compliance. Therefore, it must also
satisfy the requirements of the Radio and
Telecommunications Terminal Equipment (RTTE)
Directive, which has requirements for radio, EMC
and safety. One compliance route available is by
testing to harmonised standards, the applicability
of which is dependent on the radio technology
being used.
Although the basic function, safety and EMC
performance of such a device may be covered
under IEC/EN 60601-1-2 and IEC/EN 60601-1-1
respectively, the RTTE Directive also requires that
the safety and EMC performance of the radio
element is also satisfied; possibly by applying the
harmonised standards mentioned above. This
may seem like a duplication of work, but some
parts of the compliance testing process may be
performed simultaneously, minimising cost. A
good compliance professional would be able to
provide expert advice on a suitable route.
These are the two main Directives which apply
to the rf enabled blood pressure monitor in its
simplest form. However, compliance is by no
means limited to these two. Depending on
functionality of the product and the intended
operating environment, there are other Directives
which may be relevant for medical electronic
devices. For example, if the device was to be
operated in a potentially explosive atmosphere,
compliance with the Atmosphere Explosive
(ATEX) Directive would also have to be
considered. This introduces a further tier!
This basic example demonstrates the
importance of a designer or other person
intending to put a product on the market fully
exploring all possibilities of where the product is
to be used as early as possible in the
development phase. Doing so will help to
minimise cost, as retrospective compliance
assessment can be very expensive.
Furthermore, if a particular radio technology or
protocol is used, there may be certification issues
or membership requirements to be dealt with in
order to use the intellectual property. This may
have marketing benefits in that a certification
program for a given technology may be a process
of interoperability testing to demonstrate that the
product works with other similar products, but
from different manufacturers. Such programs tend
to have a logo based approach; once certification
has been completed and demonstrated to be
compliant, a logo may be attached to the product
so the consumer can be confident that it will
interoperate as intended in an rf environment
without any obstruction.
In summary, it can be seen that there could
be many levels to complete compliance for a
product before it is placed on the market. It can
be complicated, but it doesnt need to be so long
as adequate forethought is given to the process
at the early stage of development.
Author profile:
Joe Lomako is business development manager
with TRaC (www.tracglobal.com).
For further information on
any subject visit:
The level of compliance
which needs to be applied
is dependent on the
functionality of the
product and the
technology it employs.
P035_NELE_MAY24 18/5/11 12:32 Page 1
www.kemtron.co.uk
+44 (0) 1376 348115 info@kemtron.co.uk
Over 30 years experience
in providing solutions to
emc and environmental
sealing issues.
Manufacturers of
RFI/EMI gaskets,
components &
Environmental
seals.
P036_NELE_MAY24 20/5/11 12:33 Page 36
Embedded Design Embedded Test
More scope for testing
As engineers needs develop, oscilloscope manufacturers are providing
more functionality in smaller packages for less. By GrahamPitcher.
Y
ou might think that users at the lower end
of the oscilloscope market were not
interested in performance. But you would
be wrong and leading oscilloscope
manufacturers are bringing technology to bear in
an attempt to meet users demands.
Peter Kasenbacher, Agilents European
product line manager for oscilloscopes, noted:
Even in the general purpose market, new
technology is playing an important role. And the
new technology to which Kasenbacher refers is a
range of asics. ASICs bring better performance
to a new price point.
Agilents latest asic for oscilloscopes is
MegaVision IV, a 90nm design featuring 6million
gates and 40Mbit of embedded dram. The part,
capable of supporting 1m updates per second, is
performing tasks previously undertaken in
software. Software based processing is now
seen as something that slows performance.
Agilent is not alone in looking to advanced
technology to bring more functionality to its
products; both Tektronix and LeCroy have made
similar investments. Dave Ireland, European
marketing manager with Tektronix, said:
Developing asics for these applications requires
a substantial investment. Once that investment
has been made, it will migrate over time down
the product portfolio and allow us to get a return
over the longer term.
Why is this increase in functionality
needed? Bill Driver, product marketing
manager with LeCroy, noted: There is a
trend towards the use of analysis tools. A
general purpose scope will only go so far
to meeting their needs. Then, its a case of
what else we can offer. For example, he
continued, power supply designers need to
know about things that arent normally seen on a
scope. Theyre asking how do I solve problems
which arent easy to see, but which are there?.
Irelands view is: Its because customers are
having to take more work on board. Things like
serial buses. If you look at USB3, youre talking
about a high performance serial bus and that
level of performance requires more from the
scope, including an appropriate bandwidth.
Nevertheless, while you might have the ability in
the scope, the signal path is becoming the
limiting factor.
Driver said a combination of hardware and
software tools was helping to bring different views
of problems. Then, designers can focus on one
offs or rare events which cost time and money.
Our focus is on making designers lives easier.
Much like you can get your favourite burger
super sized, there is an emerging trend
towards the provision of super scopes. Driver
explained: We have had the situation where our
traditional 8bit products dont provide the
accuracy which designers need. This can cause
them to not carry on with their projects. But he
also contended that scopes mean different
things to different users. Some believe scopes
are good for dc measurement, he noted. That
requires good precision and that has driven
development of the WaveRunner HRO 6 Zi,
where we have tried to get accuracy down to
0.5% a factor of four improvement. Thats not
specmanship, thats a necessity and we want
our scopes to be as accurate as dmms and
dvms, but were not there yet.
Ireland had a similar view: Were giving
engineers the opportunity to access more
features at an affordable price and thats whats
behind the DPO5000 series; taking high end
technology and migrating it to a Windows based
platform.
Despite being super sized, scopes remain a
design tool and live, in general, on the bench. Its
a key piece of equipment, Driver accepted, but
scopes have traditionally been used with other
Embedded Design Embedded Test
devices. As bench space shrinks and budgets
decline, there is a move to one instrument and
thats generally a scope. The challenge for us is
to squeeze more into a smaller box.
Bandwidth is a figure of interest. WavePro
scopes now offer 3 to 6GHz, but are being used
in the same market space, said Driver.
Similarly, WaveRunner devices offer 2 to 4GHz.
He said that it is sometimes hard to believe
the speed with which scopes are now being
developed. For LeCroy, the challenge is turn
round time; integrating new ideas with the
existing architecture. Were finding things cant
always fit.
What has enabled WavePro scopes to run up
to 6GHz is a new chipset with a 40Gsample/s a/d
converter. That chip also allows WaveMaster
scopes to push up to 45GHz, said Driver. Were
sharing technologies between platforms, but it
takes a couple of years to develop products and
bring them to market.
But theres only so much shrinkage that can
be done. Wed like to scale WaveMaster down
and sell it as a lower end product, Driver
admitted, but you can only go so far before it
doesnt make economic sense.
The other way to approach that problem is to
offer users an upgrade path; an approach driven
by Agilent over the last few years. By offering
upgrades, Agilent believes its customers
investment is protected. Driver asserted:
Customers now demand this; they are more
comfortable with a product that can be
upgraded.
Agilents recently announced 2000 and 3000
series devices, in Kasenbachers opinion, bring
more scope to the user. They have the largest
screens in their class, they have the deepest
memory and the fastest waveform update rate.
Kasenbacher recognises the increasing
pressure on bench space. Designers dont have
enough bench space, he observed, so putting
things together makes sense. But the intrinsic
performance must be good.
He said those using mixed signal scopes
generally have only a few comms lines, so
providing 8 or 16 is fine. If they need more than
that, they really should be using a logic
analyser, he commented.
Yet even in a sector where products have been
developed over decades, there is still room for
innovation. In LeCroys case, its a pivoting
display. Driver thinks the ability to look at signals
in a portrait format will be important. Now, users
can look at up to 36 digital lines and see a lot
more detail. We dont see this as a gimmick.
Despite what a scope can do, how its
designed remains important, as recently retired
Agilent engineer John Campbell notes. In the
InfiniiVision X-Series, there are 26 different
models. These can be configured by combining
three final assemblies. These assemblies draw
from a total of 11 sub assemblies four front
panels, six acquisition and one rear end/supply
assembly. The internal structure and assembly
can represent real value to the end customer, but
the designer must primarily satisfy those who
have to produce the product.
Ireland said there was more to mid range
scopes than just providing the instrument itself.
We have to give support beyond the physical
level, such as protocol support. Engineers want to
use the scope to see whats going on. Trying to
look at a USB3 design without the coding attached
doesnt help very much; they need to know how
data packets get from A to B, he concluded.
Top: An exploded view of Agilents InfiniiVision X-Series oscilloscopes.
Below: LeCroys WaveRunner HRO 6 Zi range features a pivoting display
More Details
with 12-bit.
The New WaveRunner HRO 6 Zi features a pristine signal path that offers unmatched signal delity with
12-bits of vertical resolution and the lowest noise in the industry. This performance is augmented by a
huge offset and timebase delay adjustment to allow easy signal and amplier performance assessment and
zooming on vertical and horizontal signal characteristics. Designed for the automotive, power, medical, and
electro-mechanical markets, the WaveRunner HRO has higher resolution and much greater measurement
precision than 8-bit alternatives.
www.lecroy.co.uk
Tel: 01753 725371
Q 400 MHz 600 MHz
Q 12-bits of resolution, 15-bits with ERES
Q Up to 55 db SNR
Q 2 GS/s Sample Rate
Q Up to 256 Mpts/Ch Memory
Q Superior DC Accuracy
Q High-End Analysis Capabilities
WaveRunner 12-bit High-Resolution Oscilloscopes cilloscopes
P039_NELE_MAY24 19/5/11 12:53 Page 1
Company Profile Altera
T
he quality of a suit is only as
good as the material it is made
from. The same thing can be said of
FPGAs. For many generations FPGAs
have contained digital signal
processing (DSP) blocks enabling
them to deliver huge amounts of
processing power. The design of
these DSP blocks however has not
really changed significantly, limiting
the developer to implementations
based on the use of 18x18 or 18x25
bit fixed precision multipliers, this is
now changing.
Recently Altera has taken a
quantum leap forward with the new
high-performance, variable-
precision DSP Block contained in the
recently announced 28nm FPGA
families. This new feature enables
the architecture of the DSP Block to
be adapted to the particular
demands of the application that the
FPGA is being tasked with. For
example video surveillance system
typically work at 9 12 bit
resolution yet high-performance
computing and military radar need
very high precision or full double
precision floating point.
The variable-precision DSP Blocks
can support multiple modes of
operation and has many additional
features that enable it to offer full
support for many types of DSP
functions. Figure 1 shows the Stratix V
DSP Block configured in dual 18 x 18-
bit mode and high-precision 27 x 27-bit
mode. The Arria V and Cyclone V DSP
block supports dual 18 x 19 bit mode
and high-precision 27 x 27 bit mode.
If greater precision is needed the DSP
blocks can be concatenated to build
much wider functions. Table 1 shows
examples of DSP resource utilisation.
The variable-precision DSP Block
also includes several additional
features to support challenging
algorithms like FIR and FFT filters,
such as:
Pre-adder/subtractor to support
symmetrical FIR filter
implementations.
Post-adder/subtractor to support
systolic FIR filter implementations.
A 64-bit accumulator to support
incrementing, decrementing, and
pre-loading.
Coefficient storage within the DSP
block saving to boost performance.
A feedback register and multiplexer
to support time domain multiplexed
data such as the I/Q data of some
wireless applications within Arria V
and Cyclone V devices.
If a fixed-point DSP
implementation doesnt fit the
dynamic range of the application,
we should look to at a floating-
point implementation. The
variable-precision DSP Block is
specifically designed to support
floating-point operations. A single-
precision floating point multiplier
can be implemented using only one
variable-precision block configured
in the high-precision mode, double-
precision requires only two
variable precision blocks.
Minimising design time is a key
factor in reducing R&D costs.
Algorithm development can be
performed using floating point C
software or an algorithmic
evaluation environment such as
MATLAB Simulink. However, the
process of manually moving the
final algorithm into RTL for
implementation in a FPGA is typically
not an easy one; fortunately Altera
offers a tool called DSP Builder
Advanced Blockset that automates
this conversion process. DSP Builder
is an add-on to Simulink that
automatically generates HDL with
the appropriate level of pipelining
and time division multiplexing to
meet the required Fmax and latency
set at the system level in Simulink.
The tool also allows floating-point
and mixed paths to be entered and
generates a fused-datapath
implementation.
By developing an innovative,
variable-precision DSP Block that
can adapt to the required bit width
and powerful development tools with
a comprehensive range of DSP IP,
Altera has delivered the DSP system
architect a high quality FPGA made
with the right DSP material that can
deliver more powerful and efficient
DSP systems for the future.
Table 1. Popular precision modes supported by cascading Multiple Variable-
Precision Blocks
Multiplier Mode DSP Silicon Resources Application
Independent mode 9x9 3 per variable-precision block Low-precision fixed point
Sum mode 18x18 2 per variable-precision block Medium-precision fixed point
Independent mode 2 per variable-precision block Medium-precision fixed point
18x18 with 32-bit resolution
Independent mode 1 variable-precision block High-precision fixed point
18x25 or 18x36
Independent mode 27x27 1 variable-precision block High-precision fixed point or
single-precision floating point
Independent mode 36x36 2 variable-precision blocks Very-high-precision fixed point
Independent mode 54x54 2 variable-precision blocks Double-precision floating point
Complex multiply18x18 2 variable-precision blocks Resource-optimized FFTs
Complex multiply18x25 3 variable-precision blocks Accommodate bit growth
in FFTs
Complex multiply18x36 4 variable-precision blocks Full-precision large FFT stages
Complex multiply 27x27 4 variable-precision blocks Single-precision floating-point
FFTS
Bespoke DSP
Tailored to fit your Application
By Craig Davis, Altera Corporation
Figure 1. Stratix V DSP Block showing two different precision modes
Dual 18-bit precision mode 27-bit high precision mode
Communication Design Programmable Platforms
T
he advent of fpgas with optical interfaces
promises to simplify high speed interfacing
between and within systems. But not all
fpga vendors believe the optical enabled fpgas
time has come, arguing that cost and reliability
hurdles must be overcome before system
vendors will embrace the technology.
Altera announced in March that it is
developing fpgas with optical interfaces.
Claiming it will detail its technology
demonstrator later this year, Altera describes the
advent of optically enabled fpgas as a turning
point, driven by the speed-reach tradeoff of
electrical interfaces, coupled with the rising cost
of elaborate pcb materials needed for the highest
speed interfaces.
Interface speeds continue to rise, due to the
relentless growth in data and internet traffic. The
Interlaken interface has a channel rate of up to
6.375Gbit/s, the Gen 3.0 PCI-Express standard
uses 8Gbit/s lanes and 16 Gigabit Fibre Channel
standard operates at 14.1Gbit/s. New optical
modules using the CFP2 form factor for 100Gbit,
to be introduced in 2012, will use the four
channel electrical interface.
Increases in channel speed can be met using
copper interfaces, though at the expense of
reduced link distances. Craig Davis, senior
product marketing engineer at Altera, cites the
10GBASE-KR 10Gbit/s backplane standard as an
example of the bandwidth-reach fpgas can
achieve: 40in, including the losses of the two
connectors at each end.
There is also development work on very short
reach electrical interfaces at 28Gbit/s for line
cards and electrical backplanes. You are
basically talking about 4 to 6in of trace to a CFP2
module or a chip to chip interface, said Panch
Chandrasekaran, Xilinx senior product
marketing manager for high speed serial I/O.
Honestly, this is going to be a challenge, but we
usually figure out a way how to do things.
The faster the link, the more energy has to be
put into the signals and the more losses you
have on the board, said Davis. Signal integrity
aspects also get more
difficult and the costs go
up, as does the power
consumption.
According to Altera,
signal losses more than
triple when going from
10 to 30Gbit/s. To match
losses at 10Gbit/s when
operating at these
higher speeds, more complex pcb materials,
such as N4000-13 EP SI and Megtron 6, are
needed, rather than the traditional FR4. However,
the cost of designing and manufacturing such
pcbs can rise fivefold.
In contrast, optically enabled fpgas simplify
pcb design. For traditional chip to chip on a line
card, optics does have a benefit, because you
can trade off the number of layers on a pcb, said
Davis. Such an optical based design also offers
future proofing. Many of the applications we will
be looking to support are across backplanes and
between shelves, said Davis. An advantage of
using optics is that you havent got to throw your
backplanes away as [interface] speeds
increase.
FPGAs with optical interfaces also promise
new ways to design systems. Normally, line
cards talk to those on different shelves via a
switch card on each shelf. Using an fpga with an
optical interface, the cards can talk directly.
People are looking at this, said Davis. You
could take that to the extreme and go to the next
Seeing the light
As interface speeds increase, will fpgas see the light through
optical interconnect? By Roy Rubenstein.
Fig 1: A generic optical fpga application
Up to 1000m fpga with optical
interfaces
fpga with optical
interfaces
TOSA
xN
TOSA
xN
ROSA
xN
ROSA
xN
Communication Design Programmable Platforms
cabinet, which makes a much easier system
design.
Altera also notes vendor interest in optical
enabled fpgas for future storage systems. Here,
interlinked disk drives require multiple
connectors between boards. There is an
argument that it becomes a simpler system
design when one fpga talks directly to another or
one chip directly to another, says Davis The
more advanced R&D groups within certain
companies are investigating the best route
forward.
But while fpga companies agree that optical
interfaces will be needed, there is no consensus
on timing. Xilinx has been looking at this
technology for a while now, said
Chandrasekaran. There is a reason why we
havent announced it: we have a little while to go
before key ecosystem and technology questions
are answered.
The mechanical and reliability issues of
systems are stringent and the optical option
must prove that it can deliver what is needed,
said Chandrasekaran. It is possible to do at the
moment, but the cost and reliability equation
hasnt been fully solved. Xilinx also says that,
while it is discussing the technology with
customers, the requirement for such fpga based
optical interfaces is some way off. Our
interactions with customers are primarily for
products that are not going to see the light of day
for several years, said Chandrasekaran.
Customers are always excited to hear about
integration, said Gilles Garcia, director, wired
communications business unit at Xilinx. But,
ultimately, customers care less about the
technology as long as the price, power and board
real estate requirements are met. [optical
enabled fpga] technology is not answering the
requirements our large customers [have] for
their next generation systems, said Garcia
FPGA vendor Tabula also questions the near
term need for such technology. Alain Bismuth, vp
of marketing, points out that nearly all the ports
shipped today are at speeds of 10Gbit/s and
less. Even in 2014, the number of 40Gbit/s ports
forecast will only number 650,000, he said.
For Bismuth, two things must happen before
optically enabled fpgas become commonplace.
You must be able to build them in high volume,
reliably and with good yields, without incurring
higher costs than a discrete [fpga and optical
module] solution, said Bismuth. Second,
interesting volumes of networks at 100G and
beyond must emerge to justify the integration
effort. For him, such
networks are only
emerging fairly slowly.
Meanwhile Alteras
development work
continues apace. We
are working with
partners to develop the
system and we will be
demonstrating the
optics on a chip in Q4,
said Bob Blake,
corporate and product
marketing manager,
Altera Europe. Altera said its packaged fpga and
optical interface will support short reach links up
to 100m over multimode fibre.
While the technology will use a 10Gbit/s
optical interface, Altera has detailed that its
Stratix V fpga family supports electrical
transceivers at 28Gbit/s. The optical interface
can go higher than [10Gbit/s], so we can target
28Gbit/s and beyond, says Davis.
Optical component and transceiver firms,
such as Avago, Finisar and Reflex Photonics, all
have parallel optical devices dubbed optical
engines that support up to 12 channels at
10Gbit/s. Avagos MicroPod 12x10Gbit/s optical
engine measures 8x8mm, for example.
None of the optical vendors would comment
on being involved with Altera. Avago said it is
working to ensure its optical modules work with
fpga serdes blocks in line with Alteras
announcement, while Finisar confirmed it is
seeing leading vendors moving optics further
onto the board and deeper within systems.
Reflex Photonics said it has the technology
and products to realise optically enabled ics. We
are working with more than one company to
bring optically enabled ics to market, said
Robert Coenen, vp, sales and marketing. Due to
their penetration into niche markets, fpgas make
the most sense to create what will, ultimately, be
a huge market in optically enabled ics.
Fig 2: Projected high speed I/O data rate trend
1995
P
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Y

b
i
t
r
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e

(
G
b
i
t
/
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1000
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Sonet
DDR4/5
USB3
Ethernet
Fibre channel
2005 2010 2015 2020 2025
SATA
PCIe
OIF/CEI
SAS
25/40/100Gbit/s standards
Fig 3: The optical-electrical crossover threshold bandwidth-distance product
10cm
1m
10m
100m
1km
10km
100km
1000km
10 000km
10 000
1000
100
10
1

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$10
$30
$100
$300
$100
$3000
$10 000
1Mbps
1980 1985 1990 1995 2000 2005 2010 2015
10Mbps
100Mbps
1Gbps
10Gbps
100Gbps Link bandwidth
To the
package/chip
To the board
active cables
To the box/rack
Across central office,
data centres
Metro, access,
cross-campus
Cross-country
Trans-oceanic
Single mode,
WDM
1Tbps
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Multimode,
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DWDM
www.xilinx.com/7
Copyright 2011. Xilinx, Inc. XILINX, the Xilinx logo, Artix, ISE, Kintex, Virtex, and other designated brands included herein are trademarks of Xilinx in the United States and other countries.
All other trademarks are the property of their respective owners.
Twice the performance. Half the power.
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ISE
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P043_NELE_MAY24 18/5/11 12:20 Page 1
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P044_NELE_MAY24 20/5/11 10:56 Page 44
System Design Displays
T
ouch screens have proved
to be a phenomenal
success with smartphones
and tablets, such as the iPad,
changing the way that users
interact with devices. However,
mass market use of touch
screens has tended to be
confined to smaller devices;
there have only been a couple of
attempts to deploy touch
screens into larger devices, such
as desktop computers, because
the costs become prohibitive. However, touch
technology specialist Peratech has developed a
way of making touch screens that retains all the
benefits of existing touch screen technologies,
while overcoming their drawbacks. In particular,
the approach overcomes the constraints on larger
screen sizes.
Peratech has developed and patented a
material called Quantum Tunnelling Composite
(QTC). When a force is applied to this material, its
resistance decreases in direct proportion to the
force applied. This relationship makes the
material suitable for use in a wide range of
applications: from the replacement of switches to
the detection of the lightest of
touches.
The composite consists of a
polymer which includes spiky
nanoscale particles of metal
rather like a mediaeval mace.
When a force is applied to the
composite, the tips of the spikes
move closer together and a
quantum tunnelling effect occurs
that enables a current to flow (see
fig 1). When the force is removed,
the particles move back to their
original position, no current flows and the
materials resistance returns to its previous value
of almost infinity.
The force sensing ability of QTC can be used in
many applications, but it has created a large
amount of interest amongst mobile device
developers, who are excited by the potential of
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.
Fig 1: Quantum tunnelling allows more current to flow
Loose
Low Force conduction level High
Close Closer
Peratechs cto David Lussey with a
sheet of QTC Clear
System Design Displays
adding another dimension to Human Machine
Interaction pressure. Because the harder QTC is
pressed, the more current flows through it, the
result is a smooth, analogue third dimension of
input into the digital world of the mobile phone.
Thus, for example, pressing harder could make a
menu scroll faster, a line wider or an avatar jump
higher in computer games.
Unfortunately, as QTC is made from metal
particles in a polymer, it is opaque and this has
presented a problem in making pressure
sensitive screens for mobile phones. Peratechs
initial solution to this problem was screen
printing a series of QTC dots around the perimeter
of the screen. These dots detect the applied force
as they are compressed against the screens
mounting rather like a gasket.
Having determined there was a market
amongst mobile device developers for force
sensing devices, Peratech continued to
research into ways to create what was
required a clear version of QTC. And
this has been achieved in the form
of QTC Clear. This can be screen
printed to form a thin layer that
has minimal impact on
transparency, being similar
to that of a layer of indium
tin oxide (ITO).
Not only does QTC Clear
provide pressure
sensitive 3d input
with a
proportional response,
but it also breaks
through the barrier that
has until now kept
touch screens
restricted to small
screen applications.
Resistive touch
screens designs use a
sandwich design, with
a soft top layer and a
hard bottom layer
separated by small
spacer bumps. When
the soft top layer is
pressed, it deforms
and contact is made
between two thin films of conductive material
(ITO) on the inside of the two structural layers. The
drawbacks are that the top layer has to be soft
enough to deform easily when pressed, which
makes it vulnerable to damage by scratching, and
it cannot be used to provide the increasing
important multitouch functionality. No current
flows unless pressure is applied, there are no emi
issues and resistive touch screens can be used
with gloves and in any humidity conditions.
Crucially, however, as screen size increases, it
becomes harder to maintain the tension of the
top surface at the required level in order for the
touch screen to work correctly. This has
constrained its use to small screens.
Capacitive touch screens have overcome
many drawbacks of the resistive approach and
have therefore become more popular. They have a
robust, hard top surface and provide multitouch
abilities. However, the active matrix that provides
the touch detection has a relatively
high power consumption
and this also
constrains
screen size,
while creating
potential
interference issues whose solution requires
careful design. This makes large capacitive
screen solutions expensive. And the technology
cannot be used with gloves or in high humidity
environments.
Force sensitive touch screens
QTC based touch screens use the same sandwich
structure as resistive touch screens, with the
exception that the air gap and spacer bumps are
replaced by a screen printed, 6m thick layer of
QTC. By removing the air gap and replacing it with
QTC, a material with a similar refractive index, the
overall transparency is improved. The top layer
can be relatively hard, because QTC Clear can
detect deflections of as little as a couple of
microns from a force of as little as 5g. QTC based
screens can also detect multi touches.
QTCs properties mean that virtually no
current flows unless a force is applied, which
overcomes the drawbacks of capacitive designs
that constantly draw current and require emi
issues to be solved.
Importantly, there is no constraint on the size
of a QTC based touch screen, so Force Sensitive
touch screens can be made to any dimensions,
opening up the market for a wide range of uses
from desktop computers to automotive and from
in store displays to interactive control interfaces.
Manufacturers of resistive touch screens can
easily upgrade to QTC Clear using their existing
manufacturing procedures and equipment.
Capacitive touch screens can also benefit
from the addition of a QTC Clear layer, with a key
benefit being power saving. Because the matrix
needs to be active in order to detect a touch,
capacitive touch screens use power continually,
which drains the battery in portable devices. A
QTC Clear layer can act as a switch, activating the
capacitive matrix only when a touch is detected.
This provides a significant improvement in
battery life. Additional features that QTC provides
are pressure sensitive input, variable line widths
and more intuitive gaming interaction.
Peratech has already licensed QTC Clear to a
leading touch screen manufacturer and it
anticipates that Force Sensing touch screens will
be included in products being developed for the
Christmas 2011 market.
Author profile:
Chris Lussey is Peratechs joint chief executive
officer.
Peratechs Quantum Tunnelling Composite consists
of a polymer with spiky nanoscale particles of metal
46 www.newelectronics.co.uk
T: +44 (0)1959 563345
E: info@review-displays.co.uk
www.review-displays.co.uk
Review Display Systems Limited are rmly
established as the leading UK specialist supplier
of at screen displays and systems. With 25 years
experience we are privileged to represent some
of the worlds leading manufacturers of LCD, TFT,
Plasma and VF display technologies together with
market leading touch systems, industrial single
board computers and embedded systems.
Our ISO 9001 registration covers inhouse design
and production capabilities for bespoke systems.
Discover at panel
display technology
TM TM
For modern wall mount enclosures in a
huge range of sizes and styles visit:
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OKW ENCLOSURES LTD
Tel: 01489 583858
E-mail: sales@okw.co.uk
WALL MOUNT
ENCLOSURES
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Advanced designs for today's
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P047_NELE_MAY24 19/5/11 10:45 Page 47
Marketwatch Component Prices
Analysis
Aluminium electrolytic capacitors
The big three Japanese manufacturers
have been trying to restore production
at existing facilities and at facilities
outside of Japan.
The market was projected to be tight
before the earthquake, with insufficient
raw material in the channel. Aluminium
foil will continue to be in short supply
through the rest of 2011 and IHS iSuppli
predicts prices and lead times will
continue to increase.
Crystals, oscillators, emi filters
Japan is the worlds leading producer of
quartz crystals, crystal oscillators and
high end emi filters.
Two oscillator suppliers have confirmed
earthquake damage, as has one crystal
producer for oscillators. While IHS
iSuppli says it is too early to assess the
full impact, it believes that it is
reasonable to assume there will be an
impact on supply.
Key Japanese suppliers are expected to
push out oscillator, crystal and filter
product lead times by a further four to
six weeks. IHS iSuppli expects pricing on
selected crystal products to increase in
the short term.
CATEGORY DESCRIPTION FEB MAR APR
Analogue Monolithic Amplifiers and comparators 1.1 0.4 0.6
Analogue Monolithic Analogue interface ics 0.8 0.5 0.6
Analogue Monolithic Voltage regulators and references 1.1 0.5 0.6
Capacitors Aluminium 0.5 0.8 1.2
Capacitors Ceramic -0.6 0.8 1.1
Capacitors Tantalum -1.2 0.7 0.7
Connectors 0.1 0.1 0.3
Resistors SMD flat chips 0.2 0.2 0.3
Filters -0.6 0.5 0.9
Crystal kHz 0.4 0.2 1.1
Crystal MHz 0.5 0.5 1.5
Oscillator TCXO -0.1 0.2 0.7
Oscillator VCXO -0.2 0.2 1.6
Oscillator XO -0.1 0.2 0.8
Magnetics Ferrite beads -0.2 0.4 0.3
Magnetics Fixed inductors -0.2 0.4 0.4
Standard Logic General purpose cmos 1.1 1.0 0.9
Standard Logic General purpose bicmos 1.1 1.0 0.8
Standard Logic General purpose bipolar 1.2 1.0 0.8
Rectifier Schottky and ultrafast -0.3 0.5 0.5
Transistor Bipolar power 0.5 0.5 0.5
Transistor Power mosfet 0.4 0.5 0.6
Transistor Small signal 0.4 0.4 0.5
Memory Dram 1.3 -0.6 6.0
Memory Flash NAND 0 15.0 3.0
Memory Flash NOR -1.0 5.0 4.3
The IHS iSuppli mission is to reduce the
overall cost of acquisition for
electronic components, whilst
improving the continuity of supply and
simplifying supply chain processes for
ems, oem and supplier communities.
Market Intelligence Services provide
critical information designed to enrich
tactical decisions and strategic plans.
Visit www.isuppli.com
Data courtesy of iSuppli
Component prices were reset at zero in September 2007 and show percentage changes per month. Increasing prices are highlighted in red.
d D
d ^
UUUQGJGA?AMK?PKUMPIQFMNQ
Register today
Ior the
5ilica &
seminar on June 7th and 8th 2011 in 0ambridge at
P049_NELE_MAY24 20/5/11 10:54 Page 1
www.beeas.co.uk
Supporters of: Organised by: Headline sponsors: Sponsors:
British Engineering Excellence Awards 2011
Be part of
the best
compilation
of the year
Entries are now open!
Make sure your
design projects
gain the recognition
they deserve.
To enter visit
www.beeas.co.uk
or call Julie Knox
on 01322 221144
P050_NELE_MAY24 18/5/11 12:23 Page 1
Call James Slade on 01322 221144 Technology Update
@: pernickyj@avxeur.com
: +420 575 757 540
AVXs UQCL series capacitors provide
high current, high Q and low ESR
AVX Corporation, a leading manufacturer of advanced passive
components and interconnect solutions, has developed a
multilayer capacitor (MLC) chip series with new dielectric and
internal electrode materials in a 0402 size. These materials
allow for a much lower equivalent series resistance than in
previous versions of RF capacitors. Designated the UQCL Series, the chips are ideal for RF/microwave
applications ranging from 10MHz to 4.2GHz. This new series has a fine-grained, high density, high
purity dielectric material to keep out moisture, and includes an electrode system that has been
optimized for high frequency performance, said Larry Eisenberger, AVX product manager. This makes
the UQCL Series ideal for applications with high current carrying capabilities and high quality factors.
The capacitors also offer low ESR and high series resonance.
Capacitors
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@: bgreen@harwin.co.uk
: +44 (0)2392 314 545
Simple, cost-effective SMT coin cell holder
provides secure retention and saves
installation time
EZ Coin Cell Holder designed for auto assembly equipment
Portsmouth, UK, Harwin, the leading hi-rel connector and SMT
board hardware manufacturer, has expanded its range of EZ
BoardWare products with the introduction of a single piece surface mountable coin cell holder which
ensures coin cells are securely retained in place while cutting assembly time. EZ Coin Cell Holders can
accommodate 12.5mm diameter x 2.5mm thick BR1225 and CR1225 coin cells and are available in
Tape and Reel packaging making them ideally suited to automatic placement systems.
Low profile EZ Coin Cell Holders provide a cost effective solution to the problem of battery mounting.
Coin cells are securely held in place, yet they can be quickly and easily removed when they run down.
Coin Cell Holders
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c
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@: sales.uk@hitekpower.com
: 01903 712400
HiTek Powers MH100 offers
100W output power and high
reliability
The Series MH100 is a range of versatile high
voltage modules suitable for specification in
OEM equipment as component power supplies.
Applications include wide angle, high definition
CRTs, X-ray equipment, insulation and materials
testing, electron and ion beam acceleration and
projection.
Powered from 24V DC, these units allow full range control and monitoring of voltage and current and
internal potentiometers are provided for voltage and current control.
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Component Power Supply
@: drew.ehrlich@maxim-ic.com
: 408-331-4252
HDCP GMSL chipset enables secure
transmission of digital content
Maxims proprietary full-duplex control scheme handles all HDCP
protocol transactions, eliminating the need for a separate CAN or LIN
interface.
Maxim Integrated Products (NASDAQ: MXIM) introduces the latest members of its high-speed LVDS
serializer/deserializer (SerDes) family: the MAX9263/MAX9265 serializers and MAX9264 deserializer.
This gigabit multimedia serial link (GMSL) chipset features high-bandwidth digital content protection
(HDCP), and forms a complete, secure, bidirectional digital-video link (HDCP-GMSL*) for transmission
of digital video and audio over a single DC-balanced twisted-pair or differential line. The chipset
manages all HCDP protocol transactions, supports touch-screen communications, and eliminates the
CAN/LIN bus for diagnostics. The MAX9263/MAX9265 and MAX9264 HDCP-GMSL chipset is optimized
for automotive infotainment and rear-seat entertainment applications.
HDCP GMSL Chipsets
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@: info@mgpower.co.uk
: 01243 373551
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New300W1u Medical Grade Power Supply
designed for Fanless Operation
Photon Power Technology Ltd has introduced the new 300W
medical grade open frame power supply, the MPM-U300 series
from the highly successful Taiwanese manufacturer Magic Power.
The MPM-300U offers the user 300Wunder convection cooling
and 360Wwith forced air. Parallel operating is possible providing
up to 720Wwith leakage current under 300micro-amps, whilst
the active PFC meets class D and conducted EMC meets CISPR/FCC Class B.
Like many other Magic Power products, The MPM-U300 is designed for fanless operation offering the
OEMuser lower noise and higher reliability. It is RoHS compliant, and fits within 1U height constraints
with outline dimensions of 198(L) x 97(W) x 41(H) mm and has a convection cooled operating
temperature range from -20 to 50C with no de-rating.
Medical Power
@: tony.shoemaker@itt.com
: 508-618-1272
MKJ Trinity mini circular connectors
from ITT ICS now available on dynamic
online 3D web modeling site
Freely downloadable CAD drawings speed design process
for engineers.
Leading global connector manufacturer and supplier, ITT
Interconnect Solutions, has announced the immediate
availability of its Trinity MKJ series mini-circular connectors as downloadable 3D models on its
interactive 3D web modelling site. The 3D modelling function was launched in the second half of last
year and provides an invaluable resource for design engineers to try out different connector solutions
in prototype designs early in the design process. Engineers request a downloadable 3D CAD drawing
which they can then import into their own CAD systems, saving time and effort.
Mini Circular Connectors
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@: sales@gpegint.com
: 08704 931433
Optically Bonded Projective
Capacitive Touch (PCT) Screens deliver
enhanced readability to TFT displays.
Leading display innovator GPEG International has
developed Optical Bonding processes that eliminate the
problems associated with conventional PCT cover plates
while at the same time providing a number of readability
enhancements.
Optical Bonding has the following benefits:
Display designs are thinner and hence lighter Prevents fogging of the display as there is no air
gap Sunlight readability is greatly increased by up to 4x Scratch resistance increased by up to 3x
Resists moisture, dirt and dust Wide temperature operation without any change in performance
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PCT Screens
Benefit from a PCB layout team
to work wi th your engi neers
www.pcbportal.com
Allegro
Orcad
Cadstar
Altium
PADS
PCAD
PCB Portal have experienced IPC
CID certified PCB designers
email sales@pcbportal.com
telephone +44(0)1543 276769
We supply PCB prototypes and production runs. All technologies.
P051_NELE_MAY24 18/5/11 12:35 Page 1
Fast. Rugged. Flexible.

Controlled impedance Edge Rate contacts optimize signal integrity
by minimizing broadside coupling and crosstalk.
Robust when zippered during unmating.
Vertical and right angle connectors on 0,5mm and 0,8mm pitch.
High speed edge card connectors for rugged micro backplane applications.
Floating contact system compensates for tolerance build-up
and misalignment with float in x and y directions.
Edge Rate
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P052_NELE_MAY24 18/5/11 15:45 Page 1

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