This document describes a new current-controlled oscillator (ICO) circuit and its applications. The ICO consists of a CMOS latch, PMOS and NMOS switches, and operates by steering a control current between two nodes to alternately set and reset the latch. Simulations show the ICO can operate with control currents in the nanoampere range and has a frequency sensitivity of 700 MHz per picoampere. Potential applications include signal generation, frequency modulation, and analog to digital conversion where an input current is converted to a pulse train for digital processing.
This document describes a new current-controlled oscillator (ICO) circuit and its applications. The ICO consists of a CMOS latch, PMOS and NMOS switches, and operates by steering a control current between two nodes to alternately set and reset the latch. Simulations show the ICO can operate with control currents in the nanoampere range and has a frequency sensitivity of 700 MHz per picoampere. Potential applications include signal generation, frequency modulation, and analog to digital conversion where an input current is converted to a pulse train for digital processing.
This document describes a new current-controlled oscillator (ICO) circuit and its applications. The ICO consists of a CMOS latch, PMOS and NMOS switches, and operates by steering a control current between two nodes to alternately set and reset the latch. Simulations show the ICO can operate with control currents in the nanoampere range and has a frequency sensitivity of 700 MHz per picoampere. Potential applications include signal generation, frequency modulation, and analog to digital conversion where an input current is converted to a pulse train for digital processing.
Chunyan Wang, M. Omair Ahmad, Fellow, IEEE and M.N.S. Swamy, Fellow, IEEE Department of Electrical and Computer Engineering Concordia University, 1455 de Maisonneuve Blvd. West Montreal, Quebec, Canada H3G 1M8 E-mail: [ chunyan, omair, swamy ] @ece.concordia.ca ABSTRACT In this paper, we present the design of a new current- controlled oscillator (ICO). The control current of this I C0 is in a nano or sub-nano Ampere range and the sensitivity of the frequency of its output voltage to the control current is about 700 MHz per PA. The circuit can operate with a low supply voltage, e.g. VDU <1 V when it is implemented with a 0.18-pm technology. It requires no bias current, thus have very low power dissipation. The circuit can be easily implemented using a standard digital CMOS technology. Some applications of the proposed ICO, particularly those for AID conversion, are also described in the paper. 1. INTRODUCTION Current-controlled oscillators (KO) are important building blocks in the design of electronic signal generation, processing or data-conversion circuits. Many of the existing current-controlled oscillators are based on multi-vibrators or ring oscillators, in which multiple stages of delay elements are included. Logic gates and operational amplifiers (OpAmp) are often used as such delay elements. In the former, the current available to charge or discharge a capacitance of each of the gates is adjusted in order to change the frequency of oscillation[ 11. In the latter, the control current is used to adjust the circuit bias so that the gain of the OpAmps can he modified in order to adjust the frequency [Z] - [ 5] . In either case, a current variation of several nano-Amperes may not be large enough to result in a significant change of the frequency. In this paper, we propose the design of a current-controlled oscillator that is able to operate with a control current in a nA or sub-nA range. Some of the applications of the proposed circuit are also considered. 2. CIRCUIT DESCRIPTION As shown in Figure I , the proposed current-controlled oscillator consists of a CMOS latch (Invl and InvZ), a PMOS switch pair (PI and P2), and two NMOS switch pairs (NI and N,, N3 and N4). Voltages V, and V, are, respectively, the r e m and set signals of the latch, and V, and V, are the complementary output voltages of the circuit. Figure I Circuit diagram of the proposed current- controlled oscillator. The control current i, i s steered alternatively to thecapacitor at thenodeV, or Vb, resulting in an alternative set or reset of the latch. The frequency of the complementary output voltages, V, and V,, are controlled by the current i , . As Pi and P, are controlled by V, and V,, only one of them is turned on. The control current i, is thus switched to charge the gate capacitor of the transistor NI or Np , raising the respective voltage V, or V,. Then, the rising voltage becomes high enough to set (or reset) the state of the latch. 0-7803-7761-3/031$l7.00 02003 IEEE 1-793 After that the current i , will be switched to charge the other gate capacitor. Therefore, i, is switched alternatively to the two gate nodes of NI and N,, V, and Vb are raised to the high level alternatively, i.e. the latch is set, or reset, alternatively, and V, and V, change their levels periodically. Meanwhile, V, and V, are applied at the gates of the two transistors, Nj and N4, respectively, so that V, and Vb are pulled down to 0 V alternatively. The following points i n the circuit design should be noted. A differential PMOS switch pair, controlled by the output voltages of the circuit, is used to steer the control current i , alternatively to the two nodes V, and V b The cycle time, K of the pulse signals depends on the time required for V, or V, to be changed from zero to the level high enough to toggle the state of the latch. If the circuit structure are fixed and the device parameters are given, the frequency of the I C0 will depend on the voltage rate dVJdt =i/Ca and dVddt =i/Cb, where C, and cb are the capacitances at node V, and V,, respectively. As all the switches can be minimum-sized transistors, C, and Cb are usually small. A small current variation of the control current can make a significant change in the voltage variation rate. Thus, the frequency can be highly sensitive to the current variation. This feature also implies that the decrease of transistor feature size leads to a decrease in C, and C,, i.e., an increase in the sensitivity of the I C0 to the control current. A very weak control current may result i n a relatively long rise time of V, and Vb However, the rise or fall time of the output signals, V, and V,, depends mainly on the current driving capacity of the inverters and the regenerative process of the latch. Thus, the quality of the output pulses of the I C0 is not affected by the weak control current. Six MOS switches are used to switch the control current and discharging currents. All these switches are controlled by the voltage signals generated in the circuit. The circuit is, in fact, a switched-current circuit operating without any external control voltages, It should also be noted that the proposed I C0 operates with a supply voltage (VDD) lower than (Vt, +IV,& where V,, and Vtp are, respectively, the threshold voltages of the NMOS and PMOS transistors of the inverters. If VDD >(Vtn +lVtpl). the circuit may have an unstable equilibrium when V, and V, are both at the level of the threshold voltage of the inverters. In this case, all the MOS switches are turned on, and i, is divided by the two PMOS switches. Such a state may be terminated by some random excitations, such as heat agitation, and the duration of such a state i s thus undetermined. If VDD <(Vt, +lVtp'), the inverters have a voltage transfer characteristic with hysteresis as shown in Figure 2. In this case, the two transistors in each inverter will never be turned on simultaneously, and thus, the state of the unstable equilibrium is eliminated. Figure 2 Voltagetransfer characteristic of the inverters employed in the proposed KO. The supply voltage of the circuit is smaller than (Vtn +IV& the sumof the NMOS and PMOS threshold voltages. This kind of inverter is often used in electronic instrumentations. 3. SIMULATION RESULTS The I C0 (Figure I ) has been simulated using the transistor models of a 0.18-pm technology. All the transistors of this I C0 are minimum-sized. The waveforms of the signals, when the control current i, =2 nA and the supply voltage VDD =0.6 V, are shown in Figure 3. Figure 4 illustrates the frequency-versus-current characteristics of the circuit. Due to the limitation of appropriate use of the transistor models, the minimal value of i, is chosen as 2 nA in the simulation. However, we can be sure that. in practice, the control current can be much lower. The sensitivity of the IC0 is about 0.7 MHdnA. The power dissipation of the circuit depends on the frequency of the output voltage and it is 0.7 p W when the output frequency is about 140 MHz. 1-794 Tmnsient Response 0 ti me Figure 3 obtained when VDD =0.6 V and i, =2 nA Simulation waveforms of the proposed KO, Figure 4 Frequency-versus-current characteristics of theproposed ICO. The supply voltage Voo =0.6 V. 4. APPLICATIONS I C0 circuits, in general, can he used in signal processing and communication systems for example, in frequency modulation or signal generation. It can also he an important part in a PLL circuit. However, the proposed I C0 is particularly useful for optical signal sensing and processing. An incident light can he converted linearly into a current signal and then this current can be processed by the circuits involving the I C0 and other processing units. In this process, two features of the proposed I C0 need to he highlighted. First, the high sensitivity of the frequency of the proposed I C0 to theinput current makes the circuits capable of effectively responding to very weak currents converted from optical signals. Thus, the application of the I C0 can improve thecircuits capability of operating with weak optical signals. Second, the IC0 converts a current signal into a voltage one that carries the information through the duration of its cycle, instead of its magnitude. The dynamic range of the circuit is, therefore, not limited by the supply voltage, thus making the circuit to have a large dynamic range as well as a high sensitivity. Since the I C0 converts an analog current signal to a voltage pulse signal, it is obviously to he used for an A D conversion. Figure 5 shows such an example. The photocurrent ia converted from the incident signal is fed to the ICO. The number of the pulses of the output of the I C0 is then counted during a period of T that is related to the weakest input signal. At the end of the period, the counter will output a n-bit digital signal converted from the input current of the KO. - Figure 5 electrical conversion and AID conversion. Diagramof a circuit performing optical-to- As the I C0 outputs a voltage pulse signal, the information carried by its analog input can be processed digitally. The circuit shown in Figure 6 is such an example. This circuit has two optical incident signals, and its operation is controlled by a clock signal elk. During the first half of elk, the signal QINy is converted into a pulse train and the counter counts up. When elk starts the other half, the counter starts to count down with the number of the pulses related to ( J / ~ Hence, at the end of the elk cycle, the difference between $lNv - $IM( can be read at the digital output of the circuit. In this circuit, the two currents, idx and ialc are processed in the same ICO. Thus, there is no problem of the mismatch of the conversion gains. This circuit can also be used for a comparison of two optical signals. If the outputs of the two AND gates are applied, successively only to the up input of the counter, when elk =0 and elk =I , respectively, the result of qINY +$ , N~ will he obtained. The I C0 can also be used for data conversions along with other types of computations. An example is shown in Figure 7. In this circuit. the pulse width of the output 1-795 Figure 6 I down cl k Counter IelCl I Diagramof a circuit performing optical-to-electrical conversion. subtraction and AID conversion. signal of the I C0 is T,, and the cycle duration of the pulse train applied to the other input of the AND gate is Ty where Ty <<T,. The number of the pulses counted during each period of T, is then TJTy that is inversely proportional to the incident signal $lm If the pulse train is the output signal of another I C0 whose the input current is converted from another incident signal QINR the digital output signal will be the result of a division operation of QINY QIW Digital ourpv, I C0 Counter Figure 7 Diagram of a circuit of which the digital output is inversely proportional to the incident intensity @rm- 5. CONCLUSION In this paper, we have proposed a current-controlled oscillator (KO) circuit. The proposed I C0 is a CMOS- latch-based switched-current circuit. Compared to most of the existing I C0 circuits, the new circuit has a simpler structure, higher sensitivity, better ability to operate in nano-Ampere range or below with a very low supply voltage, and lower power dissipation. Moreover, the circuit does not need external control/bias signals and can be easily implemented using a standard digital CMOS technology. Some of the applications of the I C0 have been proposed. In particular, we have presented a very simple A/D convertor involving the proposed ICO, and, based on this AID converter, we have presented other simple circuits, each capable of performing optical-to-electrical conversion, arithmetical computations and A/D conversion simultaneously. Other applications of the I C0 can be in low-power signal generating circuits, signal processing and communication systems. 6. REFERENCES [l ] D. J eong et al., Design of PLL-based clock genera- tion circuits, IEEE J. Solid State Circuits, Vol. SC- 22, no. 2, April. 1987, pp. 255-261. D. Mijuskovic, Current-controlled oscillator with linear output frequency: US. Patent, No. 5,206,609, Apr. 27, 1993. [3] L. Tsai and H. Wallance, Dual adjust current-con- trolled phase locked loop, U.S. Patent, No. 5,691,669, Nov. 25, 1997. Y. Chang and E. W. Greeneich. A current-controlled oscillator coarse-steering acquisition-aid for high frequency SO1 CMOS PLL circuits, in Proc. IEEE International Symposium on Circuits and Systems, May-J une, 1999, pp. I1 561-564. H. Djahanshahi and A. Salama, Differential 0.35 pmCMOS circuits for 622 MHd933 MHz monolith- ic clock and data recovery applications, in Pmc. IEEE International Symposium on Circuits and Sys- t ems, May-J une, 1999, pp. I1 93-96. [21 [4] [51 1-796