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=
2
2
Vds
Vds Vt Vgs
L T
W
Ids
ox
ox
Ids = 0
ox
b a s ox
b fb t
qN T
V V
4
2 + + =
19
Dr. Navakanta Bhat
I-V characteristics
Ids
Vds
Vg1
Vg2
Vg3
Ids is constant and independent of Vdsin saturation
Vgs
Ids
Linear
Vds~0.1V
Saturation
Vds=Vdd
Output Characteristics Transfer Characteristics
Ids is zero in sub-threshold region
Both of these idealities are incorrect especially for
the sub-micron MOS transistor
20
Dr. Navakanta Bhat
Channel length modulation
p-substrate
n+drain
n+source
Vg >Vt Vd>Vg - Vt
electron channel
L
Effective channel length is Leff = L - L, where L=f(Vds)
Ids increases slightly in saturation region with increasing Vds
( )
2
2
Vt Vgs
L T
W
I
eff ox
ox
ds
=
This limits the AC output resistance for analog applications
Vds
Ids
Vds=Vgs-Vt
ds
ds
out
I
V
R
=
( )
( )
ds
ox
ox
ds
V
Vt Vgs
L T
W
I
= 1
2
2
is channel length modulation parameter in SPICE
21
Dr. Navakanta Bhat
Body effect
Vt increases due to body effect
= body effect factor ( = 0.3-0.7)
Vs
n+
Vbs
Vg
n+
Vd
ox
b a s ox
b fb t
qN T
V V
4
2
0
+ + =
( )
b b bs t t
V V V 2 2
0
+ + =
ox
a s ox
N q T
2
=
This results in a transconductanceterm
p-substrate
22
Dr. Navakanta Bhat
The Sub-micron MOS Transistor for
Analog Design
Sub-micron transistor theory, SCE, NWE, DIBL, Sub-threshold conduction,
Digital metrics, Analog metrics
23
Dr. Navakanta Bhat
Constant field scaling
Primary scaling factors:
Tox, L, W, Xj (all linear dimensions) 1/K
Na, Nd(doping concentration) K
Vdd(supply voltage) 1/K
Derived scaling behavior of transistor:
Electric field 1
Ids 1/K
Capacitance 1/K
Derived scaling behavior of circuit:
Delay (CV/I) 1/K
Power (VI) 1/K
2
Power-delay product 1/K
3
Circuit density ( 1/A) K
2
Technology scaling
Scaling factor K >1
SCALING IS DRIVEN BY DIGITAL CIRCUIT REQUIREMENTS
24
Dr. Navakanta Bhat
Short Channel Effect (SCE)
p-substrate
n+
n+
depletion
depletion
Fraction of the depletion charge (Qdin Vt equation) is supported
by the source and drain junctions and hence Vg need not support this
When L is very small (~1m) this charge becomes significant
fraction of the total depletion charge and can not be neglected
=> Vt decreases with decreasing L
L (m)
Vt
~1m
L
Vg
Impacts matching of transistors in analog applications
25
Dr. Navakanta Bhat
Reverse Short Channel Effect
Vt
L
ve
dL
dV
t
+ =
ve
dL
dV
t
=
Invariably exists in almost all the sub-micron technologies
The techniques used to suppress SCE are responsible for RSCE
Vt becomes very sensitive function of L
26
Dr. Navakanta Bhat
Drain Induced Barrier Lowering (DIBL)
Vds=Vdd
Vds=0.1V
L
Vt
Vs
n+
Vg
n+
Vd
Vt is also a function of drain voltage in sub-micron transistors
DIBL effect is negligible in the long channel regime
Potential barrier
Vds=Vdd
Vds=0.1V
27
Dr. Navakanta Bhat
Narrow Width Effect
W (m)
Vt
~1m
Additional depletion charge at the edge of source & drain should
be supported by the Vg before inverting the channel
When W is very small (~1m) this charge becomes significant
fraction of the total depletion charge and can not be neglected
=> Vt increases with decreasing W
p-substrate
n+
depletion
W
Vg
28
Dr. Navakanta Bhat
Sub threshold conduction
For Vg < Vt, current is non zero and is exponential function of Vg
Log Ids
Vgs
Vt
The inverse slope
of this line is S, the
sub threshold slope
(S~80-100mV/decade)
S = 2.3kT/q (1 + Csi/Cox) mV/decade
Csi=depletion capacitance in Si, Cox=oxide capacitance,kT/q=thermal voltage
MOSFET should be designed to have minimum possible S
Sub threshold analog circuits work below Vt
S
G
D
29
Dr. Navakanta Bhat
Velocity saturation
For velocity saturated transistor, the saturation drive current is
E
10
7
cm/sec at T=300
o
K
~10
4
V/cm
v
v = E valid only at low
electric fields (E)
Ids (Vgs-Vt)
2
Ids
Vds
Ids (Vgs-Vt)
Ids will be less than expected
due to velocity saturation
For L=0.1m transistor operating at Vd=1V:
E=10
5
V/cm => transistor is velocity saturated
Transconductancewill be independent of L
ox
sat t gs
T
v V V W
Ids
) (
=
30
Dr. Navakanta Bhat
Transistor design methodology for Digital Technology
Design parameters:
L, Vdd, Tox, N, Xj
S/D engineering
Channel engineering
Circuit characteristics:
Delay (Vt/Vdd)
Active power (Vdd)
Standby power (Vt)
Hot carrier reliability
Vdd, L, N
Gate oxide reliability
Vdd, Tox
System compatibility
Vdd
31
Dr. Navakanta Bhat
Vt-Vdddesign plane
Normalized delay
Vt/Vdd 0.4
Delay increases significantly for Vt/Vdd> 0.4
Pactive(Pac) = CV
dd
2
f
Pstandby(Psb) = WV
dd
I
off
Vt
Vdd
Psb
Pac
Delay
Delay and Power are the only trade-off points for digital design
32
Dr. Navakanta Bhat
Analog Circuit Performance Metrics
The Analog Octagon:
Multiple trade-offs involved in Analog Design make it very interesting
B. Razavi
NOISE
POWER
SPEED
GAIN
SUPPLY VOLTAGE
LINEARITY
VOLTAGE SWINGS
I/O IMPEDANCE
33
Dr. Navakanta Bhat
Summary
Scaling is driven by digital technology
Analog design is indispensable for interaction with physical world
Sub-micron transistors present unique challenges for analog design
Characterize the behaviour of the MOSFETsin any given
technology by doing simple I-V simulations and extracting
Vt, Rout etc. as a function of dimensions and bias points
The voltage swings in analog circuits will be limited by the
reliability constraints
While delay and power are the only two metrics for digital design,
analog design involves optimization and trade-off between
several conflicting metrics