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CONTENTS
1. Study of Simulation using tools.
2. Study of Synthesis tools.
3. Place and Root and Back annotation for FPGAs.
4. Basic logic gates
5. Half adder and full adder
6. Half Subtractor and full Subtractor, 4 bit multipliers, 4 bit
adder
7. Encoder and decoder
8. Multiplexer and demultiplexer
9. Flip-Flops, PRBS generators, accumulators
10. Counters
11. Registers
12. Design of a 10 bit number controlled oscillator
12. Traffic light controller
13. Realtime Clock(displays hrs ,mins,secs)
14. Serial adder
15. Parallel Pipelined adder/Subtractor
16. Parallel Pipeline adder
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Expt.No:
Date :
AIM:
To study the Simulation tools.
THEORY:
Creating a Test Bench for Simulation:
In this section, you will create a test bench waveform containing input
stimulus you can use to simulate the counter module. This test bench
waveform is a graphical view of a test bench. It is used with a simulator
to verify that the counter design meets both behavioral and timing design
requirements. You will use the Waveform Editor to create a test bench
waveform (TBW) file.
1. Select the counter HDL file in the Sources in Project window.
2. Create a new source by selecting Project _ New Source.
3. In the New Source window, select Test Bench Waveform as the
source type, and type test bench in the File Name field.
4. Click Next.
5. The Source File dialog box shows that you are associating the test
bench with the source file: counter. Click Next.
6. Click Finish. You need to set initial values for your test bench
waveform in the Initialize Timing dialog box before the test bench
waveform editing window opens.
7. Fill in the fields in the Initialize Timing dialog box using the
information below:
Clock Time High: 20 ns.
Clock Time Low: 20 ns.
Input Setup Time: 10 ns.
Output Valid Delay: 10 ns.
Initial Offset: 0 ns
Global Signals: GSR (FPGA)
Leave the remaining fields with their default values.
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8. Click OK to open the waveform editor. The blue shaded areas are
associated with each input signal and correspond to the Input Setup Time
in the Initialize Timing dialog box. In this tutorial, the input transitions
occur at the edge of the blue cells located under each rising edge of the
CLOCK input.
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9. In this design, the only stimulus that you will provide is on the
DIRECTION port. Make the transitions as shown below for the
DIRECTION port:
Click on the blue cell at approximately the 300 ns clock transition.
The signal switches to high at this point.
Click on the blue cell at approximately the 900 ns clock transition.
The signal switches back to low.
Click on the blue cell at approximately the 1400 ns clock
transition. The signal switches to high again.
10. Select File _ Save to save the waveform. In the Sources in Project
window, the TBW file is automatically added to your project.
11. Close the Waveform Editor window.
Adding Expected Results to the Test Bench Waveform:
In this step you will create a self-checking test bench with expected
outputs that correspond to your inputs. The input setup and output delay
numbers that were entered into the Initialize Timing dialog when you
started the waveform editor are evaluated against actual results when the
design is simulated. This can be useful in the Simulate Post- Place &
Route HDL Model process, to verify that the design behaves as expected
in the target device both in terms of functionality and timing.
To create a self-checking test bench, you can edit output transitions
manually, or you can run the Generate Expected Results process:
1. Select the testbench.tbw file in the Sources in Project window.
2. Double-click the Generate Expected Simulation Results process.
This process converts the TBW into HDL and then simulates it in a
background process.
3. The Expected Results dialog box will open. Select Yes to post the
results in the waveform editor.
4. Click the + to expand the COUNT_OUT bus and view the transitions
that correspond to the Output Valid Delay time (yellow cells) in the
Initialize Timing dialog box.
5. Select File _ Save to save the waveform.
6. Close the Waveform Editor.Now that you have a test bench, you are
ready to simulate your design.
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RESULT:
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Expt.No:
Date :
AIM:
To study the Synthesis tools.
THEORY:
Now that you have created the source files, verified the designs behavior
with simulation,and added constraints, you are ready to synthesize and
implement the design.
Implementing the Design:
1. Select the counter source file in the Sources in Project window.
2. In the Processes for Source window, click the + sign next to
Implement Design. The Translate, Map, and Place & Route processes
are displayed. Expand those processes as well by clicking on the + sign.
You can see that there are many sub-processes and options that can be
run during design implementation.
3. Double-click the top level Implement Design process.ISE determines
the current state of your design and runs the processes needed to pull your
design through implementation. In this case, ISE runs the Translate, Map
and PAR processes. Your design is now pulled through to a placed-androuted state. This feature is called the pull through model.
4. After the processes have finished running, notice the status markers in
the Processes for Source window. You should see green checkmarks next
to several of the processes, indicating that they ran successfully. If there
are any yellow exclamation points, check the warnings in the Console tab
or the Warnings tab within the Transcript window. If a red X appears next
to a process, you must locate and fix the error before you can continue.
Verification of Synthesis:
Your synthesized design can be viewed as a schematic in the Register
Transfer Level (RTL) Viewer. The schematic view shows gates and
elements independent of the targeted Xilinx device.
1. In the Processes for Source window, double-click View RTL
Schematic found in the Synthesize - XST process group. The top
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2. Right-click on the symbol and select Push Into the Selected Instance
to view the schematic in detail.
The Design tab appears in the Sources in Project window, enabling you to
view the design hierarchy. In the schematic, you can see the design
components you created in the HDL source, and you can push into
symbols to view increasing levels of detail.
3. Close the schematic window.
RESULT:
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AIM:
To study the Place and Root and Back annotation for FPGAs.
THEORY:
After implementation is complete, you can verify your design before
downloading it to a device.
Viewing Placement:
In this section, you will use the Floor planner to verify your pin outs and
placement. Floor planner is also very useful for creating area groups for
designs.
1. Select the counter source file in the Sources in Project window.
2. Click the + sign to expand the Place & Route group of processes.
3. Double-click the View/Edit Placed Design (Floorplanner) process.
The Floorplanner view opens.
4. Select View _ Zoom _ ToBox and then use the mouse to draw a box
around the counter instance, shown in green on the right side of the chip.
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5. This Fig 1 shows where the entire design was placed. Click on any of
the components listed in the Design Hierarchy window to see where each
component is placed.
6. Zoom in to the right side of the chip even more, and place your mouse
over the K13pad. You can see that your pinout constraint was applied the DIRECTION pin is placed at K13.
7. Close the Floorplanner without saving.
Viewing Resource Utilization in Reports:
Many ISE processes produce summary reports which enable you to check
information about your design after each process is run. Detailed reports
are available from the Processes for Source window. You can also view
summary information and access most often-utilized reports in the Design
Summary.
1. Click on the Design Summary tab at the bottom of the window. If you
closed the summary during this tutorial, you can reopen it by doubleclicking the View Design Summary process.
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18
In this section, you will use the FPGA Editor to view the design. You can
view your design on the FPGA device, as well as edit the placement and
routing with the FPGA Editor.
1. Double-click the View/Edit Routed Design (FPGA Editor) process
found in the Place & Route group of processes. Your implemented design
opens in the FPGA Editor.
2. Look in the List window to examine your design components.
3. Click on the COUNT_OUT K12 IOB in the List window to select the
row. This is one of the outputs in your design.
4. With the COUNT_OUT K12 row selected, select View _ Zoom
Selection. In the editor window, you can see the COUNT_OUT<0> IOB
highlighted in red.
5. Push into (double-click) the red-highlighted COUNT_OUT K12 IOB.
You should see Fig 4.
6. Enlarge the window and zoom in so you can see more detail. This view
shows the inside of an FPGA at the lowest viewable level. The blue line
shows the route that is used through the IOB. The red lines show the
routes that are available.
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20
3. To see your simulation results, zoom in on the transitions and view the
area between 300 ns and 900 ns to verify that the counter is counting up
and down as directed by the stimulus on the DIRECTION port.
4. Zoom in again to see the timing delay between a rising clock edge and
an output transition.
5. Click the Measure Marker button and then click near the 300 ns
mark. Drag the second marker to the point where the output becomes
stable to see the time delay between the clock edge and the transition.
6. Close the waveform view window.You have completed timing
simulation of your design using the ISE Simulator. Skip past the
ModelSim section below, and proceed to the Creating Configuration
Data section.
Timing Simulation (ModelSim):
If you have a ModelSim simulator installed, you can simulate your design
using theintegrated ModelSim flow. You can run processes from within
ISE which launches the installed ModelSim simulator.
1. To run the integrated simulation processes, select the test bench in the
Sources in Project window. You can see the ModelSim Simulator
processes in the Processes for Source window.
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RESULT:
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Expt.No:
Date :
AIM:
To implement basic logic gates using Verilog HDL.
APPARATUS REQUIRED:
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PROCEDURE:
AND Gate:
Output:
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AND Gate
-----------------------------------------------Input1
Input2
Output
-----------------------------------------------0
0
0
0
1
0
1
0
0
1
1
1
-------------------------------------------------
PROGRAM:
AND Gate:
// Module Name: Andgate
module Andgate(i1, i2, out);
input i1;
input i2;
output out;
and (out,i1,i2);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
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OR Gate:
Output:
#
#
#
#
#
#
OR Gate
-----------------------------------------------Input1
Input2
Output
-----------------------------------------------0
0
0
0
1
1
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1
0
1
1
1
1
------------------------------------------------
OR Gate:
// Module Name: Orgate
module Orgate(i1, i2, out);
input i1;
input i2;
output out;
or(out,i1,i2);
endmodule
// Module Name: Simulus.v
module Simulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Orgate uut (
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NAND Gate:
Output:
#
#
#
#
#
#
#
#
NAND Gate
-----------------------------------------------Input1
Input2
Output
-----------------------------------------------0
0
1
0
1
1
1
0
1
1
1
0
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------------------------------------------------
NAND Gate:
// Module Name: Nandgate
module Nandgate(i1, i2, out);
input i1;
input i2;
output out;
nand(out,i1,i2);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Nandgate uut (
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NOR Gate:
Output:
#
#
#
#
#
#
#
#
#
NOR Gate
-----------------------------------------------Input1
Input2
Output
-----------------------------------------------0
0
1
0
1
0
1
0
0
1
1
0
------------------------------------------------
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NOR Gate:
// Module Name: Norgate
module Norgate(i1, i2, out);
input i1;
input i2;
output out;
nor(out,i1,i2);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
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XOR Gate:
Output:
#
#
#
#
#
#
#
#
#
XOR Gate
-----------------------------------------------Input1
Input2
Output
-----------------------------------------------0
0
0
0
1
1
1
0
1
1
1
0
-------------------------------------------------
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XOR Gate:
// Module Name: Xorgate
module Xorgate(i1, i2, out);
input i1;
input i2;
output out;
xor(out,i1,i2);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
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XNOR Gate:
Output:
#
#
#
#
#
#
#
#
#
XNOR Gate
-----------------------------------------------Input1
Input2
Output
-----------------------------------------------0
0
1
0
1
0
1
0
0
1
1
1
------------------------------------------------
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XNOR Gate:
// Module Name: Xnorgate
module Xnorgate(i1, i2, out);
input i1;
input i2;
output out;
xnor(out,i1,i2);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
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Not Gate:
Output:
#
#
#
#
#
#
#
NOT Gate
--------------------------Input
Output
--------------------------0
1
1
0
---------------------------
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NOT Gate:
// Module Name: Notgate
module Notgate(in, out);
input in;
output out;
not(out,in);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg in;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
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Buffer:
Output:
#
#
#
#
#
#
#
BUFFER
--------------------------Input
Output
--------------------------0
0
1
1
---------------------------
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Buffer:
// Module Name: Buffer
module Buffer(in, out);
input in;
output out;
buf(out,in);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg in;
// Outputs
wire out;
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RESULT:
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43
Expt. No:
Date :
AIM:
To implement half adder and full adder using Verilog HDL.
APPARATUS REQUIRED:
PC with Windows XP
XILINX, ModelSim software.
FPGA kit
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RS 232 cable.
PROCEDURE:
Half Adder:
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Output:
#
#
#
#
#
#
#
#
#
Half Adder
-----------------------------------------------------------------Input1
Input2
Carry
Sum
-----------------------------------------------------------------0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
0
------------------------------------------------------------------
PROGRAM:
Half Adder:
// Module Name: HalfAddr
module HalfAddr(sum, c_out, i1, i2);
output sum;
output c_out;
input i1;
input i2;
xor(sum,i1,i2);
and(c_out,i1,i2);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
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Output:
#
#
#
#
#
#
#
#
#
#
#
#
Full Adder
-----------------------------------------------------------------------------------------------i1
i2
C_in
C_out
Sum
-----------------------------------------------------------------------------------------------0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
-------------------------------------------------------------------------------------------------
Full Adder:
// Module Name: FullAddr
module FullAddr(i1, i2, c_in, c_out, sum);
input i1;
input i2;
input c_in;
output c_out;
output sum;
wire s1,c1,c2;
xor n1(s1,i1,i2);
and n2(c1,i1,i2);
xor n3(sum,s1,c_in);
and n4(c2,s1,c_in);
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i1 = 0;i2 = 0;c_in = 0;
#1 i1 = 0;i2 = 0;c_in = 0;
#1 i1 = 0;i2 = 0;c_in = 1;
#1 i1 = 0;i2 = 1;c_in = 0;
#1 i1 = 0;i2 = 1;c_in = 1;
#1 i1 = 1;i2 = 0;c_in = 0;
#1 i1 = 1;i2 = 0;c_in = 1;
#1 i1 = 1;i2 = 1;c_in = 0;
#1 i1 = 1;i2 = 1;c_in = 1;
#2 $stop;
end
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RESULT:
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Expt. No:
HALF SUBTRACTOR & FULL SUBTRACTOR, 4
BIT MULTIPLIER, 8 BIT ADDER
Date :
AIM:
To implement half subtractor and full subtractor using Verilog HDL.
APPARATUS REQUIRED:
PC with Windows XP
XILINX, ModelSim software.
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FPGA kit
RS 232 cable.
PROCEDURE:
Half Subtractor:
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Output:
#
#
#
#
#
#
#
#
#
Half Subtractor
-----------------------------------------------------------------------Input1
Input2
Borrow
Difference
------------------------------------------------------------------------0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
------------------------------------------------------------------------
PROGRAM:
Half Subtractor:
// Module Name: HalfSub
module HalfSub(i0, i1, bor, dif);
input i0;
input i1;
output bor;
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Output:
#
#
#
#
#
#
#
#
#
#
#
#
#
Full Subtractor
-----------------------------------------------------------------------------------------------B_in
I1
i0
B_out
Difference
-----------------------------------------------------------------------------------------------0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
1
0
0
1
0
0
1
1
1
0
1
0
0
1
1
0
1
0
1
1
1
1
1
-------------------------------------------------------------------------------------------------
#1 i0=1'b1; i1=1'b1;
#1 $stop;
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Full Subtractor:
// Module Name: FullSub
module FullSub(b_in, i1, i0, b_out, dif);
input b_in;
input i1;
input i0;
output b_out;
output dif;
assign {b_out,dif}=i0-i1-b_in;
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg b_in;
reg i1;
reg i0;
// Outputs
wire b_out;
wire dif;
// Instantiate the Unit Under Test (UUT)
FullSub uut (
.b_in(b_in),
.i1(i1),
.i0(i0),
.b_out(b_out),
.dif(dif)
);
initial
begin
$display("\t\t\t\t\t\tFull Subtractor");
$display("\t\t-------------------------------------------------------------------------");
$display("\t\tB_in\t\tI1\t\ti0\t\t\tB_out\t\tDifference");
$display("\t\t-------------------------------------------------------------------------");
$monitor("\t\t%b\t\t%b\t\t%b\t\t\t %b\t\t\t %b",b_in,i1,i0,b_out,dif);
#9 $display("\t\t-------------------------------------------------------------------------");
end
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initial begin
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module Multiplier_verilog(Nibble1,
Nibble2,Result);
input Nibble1, Nibble2;
output Result;
assign
Result= (unsigned(Nibble1) *
unsigned(Nibble2));
end module
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8 BIT ADDER
RESULT:
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61
Expt No:
Date:
AIM:
To implement 2 x 4 Decoder and 4 x 2 Encoder Verilog HDL.
APPARATUS REQUIRED:
PC with Windows XP.
XILINX, ModelSim software.
FPGA kit.
RS 232 cable.
PROCEDURE:
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62
Encoder:
Output:
#
#
#
#
#
#
#
#
#
4to2 Encoder
------------------------------------Input
Output
------------------------------------1000
00
0100
01
0010
10
0001
11
------------------------------------
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63
PROGRAM:
Encoder:
// Module Name: Encd2to4
module Encd2to4(i0, i1, i2, i3, out0, out1);
input i0;
input i1;
input i2;
input i3;
output out0;
output out1;
reg out0,out1;
always@(i0,i1,i2,i3)
case({i0,i1,i2,i3})
4'b1000:{out0,out1}=2'b00;
4'b0100:{out0,out1}=2'b01;
4'b0010:{out0,out1}=2'b10;
4'b0001:{out0,out1}=2'b11;
default: $display("Invalid");
endcase
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i0;
reg i1;
reg i2;
reg i3;
// Outputs
wire out0;
wire out1;
// Instantiate the Unit Under Test (UUT)
Encd2to4 uut (
.i0(i0),
.i1(i1),
.i2(i2),
.i3(i3),
.out0(out0),
.out1(out1)
);
initial
begin
$display("\t\t 4to2 Encoder");
$display("\t\t------------------------------");
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Decoder:
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65
Decoder:
// Module Name: Decd2to4
module Decd2to4(i0, i1, out0, out1, out2, out3);
input i0;
input i1;
output out0;
output out1;
output out2;
output out3;
reg out0,out1,out2,out3;
always@(i0,i1)
case({i0,i1})
2'b00: {out0,out1,out2,out3}=4'b1000;
2'b01: {out0,out1,out2,out3}=4'b0100;
2'b10: {out0,out1,out2,out3}=4'b0010;
2'b11: {out0,out1,out2,out3}=4'b0001;
default: $display("Invalid");
endcase
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i0;
reg i1;
// Outputs
wire out0;
wire out1;
wire out2;
wire out3;
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66
Output:
#
#
#
#
#
#
#
#
#
2to4 Decoder
------------------------------------Input
Output
------------------------------------00
1000
01
0100
10
0010
11
0001
------------------------------------
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67
RESULT:
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69
Expt. No:
Date :
AIM:
To implement Multiplexer & Demultiplexer using Verilog HDL.
APPARATUS REQUIRED:
PROCEDURE:
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Multiplexer:
Output:
#
#
#
#
#
#
#
#
#
#
#
4to1 Multiplexer
----------------------------------------------Input=1011
----------------------------------------------Selector
Output
----------------------------------------------{0,0}
1
{1,0}
0
{0,1}
1
{1,1}
1
-----------------------------------------------
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71
PROGRAM:
Multiplexer:
// Module Name: Mux4to1
module Mux4to1(i0, i1, i2, i3, s0, s1, out);
input i0;
input i1;
input i2;
input i3;
input s0;
input s1;
output out;
wire s1n,s0n;
wire y0,y1,y2,y3;
not (s1n,s1);
not (s0n,s0);
and (y0,i0,s1n,s0n);
and (y1,i1,s1n,s0);
and (y2,i2,s1,s0n);
and (y3,i3,s1,s0);
or (out,y0,y1,y2,y3);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i0;
reg i1;
reg i2;
reg i3;
reg s0;
reg s1;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Mux4to1 uut (
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Demultiplexer:
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initial
begin
$display("\t\t\t 4to1 Multiplexer");
$display("\t\t------------------------------------");
#1 $display("\t\t\t Input=%b%b%b%b",i0,i1,i2,i3);
$display("\t\t------------------------------------");
$display("\t\tSelector\t\t\t\tOutput");
$display("\t\t------------------------------------");
$monitor("\t\t{%b,%b}\t\t\t\t\t%b",s0,s1,out);
#4 $display("\t\t------------------------------------");
end
initial
begin
i0=1; i1=0; i2=1; i3=1;
#1 s0=0; s1=0;
#1 s0=1; s1=0;
#1 s0=0; s1=1;
#1 s0=1; s1=1;
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Demultiplexer:
// Module Name: Dux1to4
module Dux1to4(in, s0, s1, out0, out1, out2, out3);
input in;
input s0;
input s1;
output out0;
output out1;
output out2;
output out3;
wire s0n,s1n;
not(s0n,s0);
not(s1n,s1);
and (out0,in,s1n,s0n);
and (out1,in,s1n,s0);
and (out2,in,s1,s0n);
and (out3,in,s1,s0);
endmodule
// Module Name: stimulus.v
module stimulus_v;
// Inputs
Output:
#
#
#
#
#
#
#
#
#
#
#
1to4 Demultiplexer
----------------------------------------------Input=1
----------------------------------------------Status
Output
----------------------------------------------{0,0}
1000
{0,1}
0100
{1,0}
0010
{1,1}
0001
---------------------------------------------
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reg in;
reg s0;
reg s1;
// Outputs
wire out0;
wire out1;
wire out2;
wire out3;
// Instantiate the Unit Under Test (UUT)
Dux1to4 uut (
.in(in),
.s0(s0),
.s1(s1),
.out0(out0),
.out1(out1),
.out2(out2),
.out3(out3)
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RESULT:
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77
AIM:
To implement Flipflops using Verilog HDL.
APPARATUS REQUIRED:
PROCEDURE:
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78
Flip-Flop:
D Flip-Flop:
Output:
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
D FipFlop
-------------------------------------------------------------------------Clock
Reset
Input (d)
Output q(~q)
--------------------------------------------------------------------------0
0
0
0(1)
1
0
0
0(1)
0
0
1
0(1)
1
0
1
0(1)
0
0
0
0(1)
1
0
0
0(1)
0
1
1
0(1)
1
1
1
1(0)
0
1
0
1(0)
1
1
0
0(1)
0
1
1
0(1)
1
1
1
1(0)
0
0
0
0(1)
1
0
0
0(1)
0
0
0
0(1)
--------------------------------------------------------------------------
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79
PROGRAM:
D Flip-Flop:
// Module Name: DFF
module DFF(Clock, Reset, d, q);
input Clock;
input Reset;
input d;
output q;
reg q;
always@(posedge Clock or negedge Reset)
if (~Reset) q=1'b0;
else q=d;
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg Reset;
reg Clock;
reg d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
DFF uut (
.Clock(Clock),
.Reset(Reset),
.d(d),
.q(q)
);
initial
begin
$display("\t\t\t\t\tD FipFlop");
$display("\t\t------------------------------------------------------------");
$display("\t\tClock\t\tReset\t\tInput (d)\t\tOutput q(~q)");
$display("\t\t------------------------------------------------------------");
$monitor("\t\t %d \t\t %d \t\t %d \t\t %d(%d)",Clock,Reset,d,q,~q);
#15 $display("\t\t------------------------------------------------------------");
end
always
#1 Clock=~Clock;
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Output:
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
T FipFlop
--------------------------------------------------------------------------Clock
Reset
Input (t)
Output q(~q)
--------------------------------------------------------------------------0
0
0
0(1)
1
0
0
0(1)
0
0
1
0(1)
1
0
1
0(1)
0
0
0
0(1)
1
0
0
0(1)
0
1
1
0(1)
1
1
1
1(0)
0
1
0
1(0)
1
1
0
1(0)
0
1
1
1(0)
1
1
1
0(1)
0
0
0
0(1)
1
0
0
0(1)
0
0
0
0(1)
--------------------------------------------------------------------------
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81
#2 d=0;
#2 Reset=1; d=1;
#2
d=0;
#2 d=1;
#2 Reset=0; d=0;
#1; // Gap for display.
#2 $stop;
end
endmodule
T Flip-Flop:
// Module Name: TFF
module TFF(Clock, Reset, t, q);
input Clock;
input Reset;
input t;
output q;
reg q;
always@(posedge Clock , negedge Reset)
if(~Reset) q=0;
else if (t) q=~q;
else q=q;
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg Clock;
reg Reset;
reg t;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
TFF uut (
.Clock(Clock),
.Reset(Reset),
.t(t),
.q(q)
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JK Flip-Flop:
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83
$display("\t\t------------------------------------------------------------");
$display("\t\tClock\t\tReset\t\tInput (t)\t\tOutput q(~q)");
$display("\t\t------------------------------------------------------------");
$monitor("\t\t %d \t\t %d \t\t %d \t\t %d(%d)",Clock,Reset,t,q,~q);
#15 $display("\t\t------------------------------------------------------------");
end
always
#1 Clock=~Clock;
initial
begin
Clock=0; Reset=0;t=0;
#2 Reset=0; t=1;
#2 t=0;
#2 Reset=1; t=1;
#2
t=0;
#2 t=1;
#2 Reset=0; t=0;
#1; // Gap for display.
#2 $stop;
end
endmodule
JK Flip-Flop:
Program:
// Module Name: JKFF
module JKFF(Clock, Reset, j, k, q);
input Clock;
input Reset;
input j;
input k;
output q;
reg q;
always@(posedge Clock, negedge Reset)
if(~Reset)q=0;
else
begin
case({j,k})
2'b00: q=q;
2'b01: q=0;
2'b10: q=1;
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Output:
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
JK FipFlop
-------------------------------------------------------------------------Clock
Reset
Input (j,k)
Output q(~q)
-------------------------------------------------------------------------0
0
(0,0)
0(1)
1
0
(0,0)
0(1)
0
0
(0,1)
0(1)
1
0
(0,1)
0(1)
0
0
(1,0)
0(1)
1
0
(1,0)
0(1)
0
0
(1,1)
0(1)
1
0
(1,1)
0(1)
0
1
(0,0)
0(1)
1
1
(0,0)
0(1)
0
1
(0,1)
0(1)
1
1
(0,1)
0(1)
0
1
(1,0)
0(1)
1
1
(1,0)
1(0)
0
1
(1,1)
1(0)
1
1
(1,1)
0(1)
0
0
(0,0)
0(1)
1
0
(0,0)
0(1)
0
0
(0,0)
0(1)
-------------------------------------------------------------------------
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PRBS generators
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87
Accumulator
module accum (C, CLR, D, Q);
input C, CLR;
input [3:0] D;
output [3:0] Q;
reg
[3:0] tmp;
always @(posedge C or posedge CLR)
begin
if (CLR)
tmp = 4'b0000;
else
tmp = tmp + D;
end
assign Q = tmp;
endmodule
RESULT:
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88
Expt No:
Date:
IMPLEMENTATION OF COUNTERS
AIM:
To implement Counters using Verilog HDL
APPARATUS REQUIRED:
PC with Windows XP.
XILINX, ModelSim software.
FPGA kit.
RS 232 cable.
PROCEDURE:
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89
Counter:
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90
PROGRAM:
2- Bit Counter:
// Module Name: Count2Bit
module Count2Bit(Clock, Clear, out);
input Clock;
input Clear;
output [1:0] out;
reg [1:0]out;
always@(posedge Clock, negedge Clear)
if((~Clear) || (out>=4))out=2'b00;
else out=out+1;
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg Clock;
reg Clear;
// Outputs
wire [1:0] out;
// Instantiate the Unit Under Test (UUT)
Count2Bit uut (
.Clock(Clock),
.Clear(Clear),
.out(out)
);
initial
begin
$display("\t\t\t 2 Bit Counter");
$display("\t\t----------------------------------------");
$display("\t\tClock\t\tClear\t\tOutput[2]");
$display("\t\t----------------------------------------");
$monitor("\t\t %b\t\t %b \t\t %b ",Clock,Clear,out);
#28 $display("\t\t----------------------------------------");
end
always
#1 Clock=~Clock;
initial
begin
Clock=0;Clear=0;
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Output:
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
2 Bit Counter
--------------------------------------------------Clock
Clear
Output[2]
--------------------------------------------------0
0
00
1
0
00
0
0
00
1
0
00
0
0
00
1
0
00
0
0
00
1
0
00
0
0
00
1
0
00
0
1
00
1
1
01
0
1
01
1
1
10
0
1
10
1
1
11
0
1
11
1
1
00
0
1
00
1
1
01
0
1
01
1
1
10
0
1
10
1
1
11
0
1
11
1
1
00
0
0
00
1
0
00
------------------------------------------------
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RESULT:
Expt No:
Date:
IMPLEMENTATION OF REGISTERS
AIM:
To implement Registers using Verilog HDL
APPARATUS REQUIRED:
PROCEDURE:
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Register:
OutPut:
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
2 Bit Register
----------------------------------------------------------------------Clock
Clear
Input[2]
Output[2]
----------------------------------------------------------------------0
0
00
00
1
0
00
00
0
0
01
00
1
0
01
00
0
0
10
00
1
0
10
00
0
0
11
00
1
0
11
00
0
1
00
00
1
1
00
00
0
1
01
00
1
1
01
01
0
1
10
01
1
1
10
10
0
1
11
10
1
1
11
11
0
0
11
00
1
0
11
00
0
0
11
00
--------------------------------------------------------------------
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95
PROGRAM:
2 Bit Register:
// Module Name: Reg2Bit
module Reg2Bit(Clock, Clear, in, out);
input Clock;
input Clear;
input [0:1] in;
output [0:1] out;
reg [0:1] out;
always@(posedge Clock, negedge Clear)
if(~Clear) out=2'b00;
else out=in;
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg Clock;
reg Clear;
reg [0:1] in;
// Outputs
wire [0:1] out;
// Instantiate the Unit Under Test (UUT)
Reg2Bit uut (
.Clock(Clock),
.Clear(Clear),
.in(in),
.out(out)
);
initial
begin
$display("\t\t\t\t 2 Bit Register");
$display("\t\t------------------------------------------------------");
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#2 in=2'b10;
#2 in=2'b11;
#2 Clear=1;
in=2'b00;
#2 in=2'b01;
#2 in=2'b10;
#2 in=2'b11;
#2 Clear=0;
#1; //Gap for display.
#2 $stop;
end
endmodule
RESULT:
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Expt. No:
Design of a 10 bit number controlled oscillator using
standard cell approach
Date:
AIM:
To design a a 10 bit number controlled oscillator using standard cell
approach
APPARATUS REQUIRED:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
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ENTITY nco IS
-- Declarations
port ( clk : in std_logic;
reset : in std_logic;
din : in signed(11 downto 0);
dout : out signed(7 downto 0)
);
END nco ;
-- hds interface_end
ARCHITECTURE behavior OF nco IS
type vectype is array (0 to 256) of signed(7 downto 0);
-- ROM cosrom
constant cosrom : vectype := (
0 => "01111111",
1 => "01111111",
2 => "01111111",
3 => "01111111",
4 => "01111111",
5 => "01111111",
6 => "01111111",
7 => "01111111",
8 => "01111111",
9 => "01111111",
10 => "01111111",
11 => "01111111",
12 => "01111111",
13 => "01111111",
14 => "01111111",
15 => "01111111",
16 => "01111111",
17 => "01111111",
18 => "01111111",
19 => "01111111",
20 => "01111111",
21 => "01111111",
22 => "01111111",
23 => "01111111",
24 => "01111111",
25 => "01111110",
26 => "01111110",
27 => "01111110",
28 => "01111110",
29 => "01111110",
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RESULT:
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106
Expt. No:
Date:
AIM:
To design a simple traffic light controller for a 4 way crossing.
using Verilog HDL
APPARATUS REQUIRED:
WORKING:
A traffic light controller works by giving GREEN signal to each road one
by one for determined period of time, the YELLOW signal are generated
for very short duration to intimate the closing of GREEN signal.
Step 1: We would design a simple 8 state counter, and each state would
control the GREEN &YELLOW LEDs.
Step 2: Each GREEN state would stay in state of 10 clock cycles, the
YELLOW state would remain in its state for 3 clock cycles only.
Step 3: The main state counter would increment after 10 clock cycles if
he is in GREEN state, but it would increment in 3 clock cycles
only if he is in YELLOW state.
Step 4: There would be state decoders which will identify the GREEN &
YELLOW states.
Step 5: For controlling the RED signal, it would not be NOR operation of
GREEN & YELLOW signals of its junction. As if any of the
GREEN & YELLOW lights are ON, then the RED should go
OFF, else it should be ON.
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Logic Diagram:
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108
PROGRAM :
Traffic Light Controller:
module Traffic_Top_FPGA( clock,Rst,G3,R4,R2,R1,R3,Y2,Y3,G2,Y4,Y1,G1,G4);
input clock,Rst;
output G3,R4,R2,R1,R3,Y2,Y3,G2;
output Y4,Y1,G1,G4;
wire w18,w19,w20,w21,w22,w23,w24,w25;
wire w26,w27,w28,w29,w30,w31,w32,w33;
wire w34,w35,w36,w37,w38,w39,w40,w41;
wire w42,w43,w44,w45,w46,w47,w48,w49;
wire w50,w51,w52,w53,w54,w55,w56,w57;
wire w58,w59,w60,w61,w62,w63,w64,w65;
wire w66,w67,w68,w69,w70,w71,w72,w73;
wire w74,w75,w76,w77,w78,w79,w80,w81;
wire w82,w83,w84,w85,w86,w87,w88,w89;
wire w90,w91,w92,w93,w94,w95,w96,w97;
wire w98,w99,w100,w101,w102,w103,w104,w105;
wire w106,w107,w108,w109,w110,w111,w112,w113;
wire w114,w115,w116,w117,w118,w119,w120,w121;
wire w122,w123,w124,w125,w126,w127,w128,w129;
wire w130,w131,w132,w133,w134,w135,w136,w137;
wire w138,w139,w140,w141,w142,w143,w144,w145;
wire w146,w147,w148,w149,w150,w151,w152,w153;
wire w154,w155,w156,w157,w158,w159,w160,w161;
wire w162,w163,w164,w165,w166,w167,w168,w169;
wire w170,w171,w172,w173,w174,w175,w176,w177;
wire w178,w179,w180,w181,w182,w183,w184,w185;
wire w186,w187,w188,w189,w190,w191,w192,w193;
wire w194,w195,w196,w197,w198,w199,w200;
and and3_Tr1(w21,w18,w19,w20);
or or2_Tr2(w24,w22,w23);
or or2_Tr3(w25,Rst,w23);
dreg dreg101_Tr4(Y1,w27,w26,Rst,w15);
nor nor3_Tr5(w29,w28,w19,w20);
dreg dreg102_Tr6(G2,w31,w30,Rst,w15);
or or3_Tr7(w32,Y3,Y2,Y4);
nor nor2_Tr8(R1,G1,Y1);
nor nor3_Tr9(w33,w28,w18,w20);
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Output:
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dreg dreg114_co116(w15,w155,w143,Rst,w17);
dreg dreg114_co117(w157,w158,w156,Rst,w17);
xor xor2_co118(w156,w157,w159);
xor xor2_co119(w162,w160,w161);
dreg dreg114_co120(w160,w163,w162,Rst,w17);
xor xor2_co121(w166,w164,w165);
dreg dreg114_co122(w164,w167,w166,Rst,w17);
dreg dreg114_co123(w153,w169,w168,Rst,w17);
xor xor2_co124(w168,w153,w154);
and and2_co125(w159,w148,w150);
and and2_co126(w161,w157,w159);
and and2_co127(w165,w160,w161);
and and2_co128(w154,w164,w165);
not inv_co129(w170,Rst);
xor xor2_co130(w172,w171,w170);
xor xor2_co131(w174,w17,w173);
xor xor2_co132(w177,w175,w176);
dreg dreg111_co133(w179,w180,w178,Rst,w16);
xor xor2_co134(w178,w179,w181);
and and2_co135(w181,w175,w176);
dreg dreg112_co136(w171,w182,w172,Rst,w16);
dreg dreg113_co137(w175,w183,w177,Rst,w16);
and and2_co138(w173,w184,w185);
and and2_co139(w176,w171,w170);
dreg dreg114_co140(w17,w186,w174,Rst,w16);
dreg dreg114_co141(w188,w189,w187,Rst,w16);
xor xor2_co142(w187,w188,w190);
xor xor2_co143(w193,w191,w192);
dreg dreg114_co144(w191,w194,w193,Rst,w16);
xor xor2_co145(w197,w195,w196);
dreg dreg114_co146(w195,w198,w197,Rst,w16);
dreg dreg114_co147(w184,w200,w199,Rst,w16);
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RESULT:
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114
Expt. No:
Date:
AIM:
To implement Real Time Clock using Verilog HDL
APPARATUS REQUIRED:
PC with Windows XP
XILINX, Modelsim software.
FPGA kit
RS 232 cable.
WORKING:
Step1: By using the combination of the 10-bit and 6-bit counter we
construct 60-bit counter, this one is used for counting seconds.
Step2: Similar 60-bit counter is constructed for counting minutes, and is
triggered by the terminal count from seconds counter, after
completion of every sixty seconds.
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115
Step3: By using 10-bit counter and 2-bit counter 24-bit hours counter is
constructed and is triggered by the terminal count from the
minutes counter, after completion of every sixty minutes.
Step4: All these BCD output signals (Hours, Minutes and Seconds) are
converted into seven segments output by using BCD to seven
segment decoder.
Step5: All these selection lines are applied to the multiplexer section, and
one of the out put is selected at a time by using 3- selection lines
from the 3-stage counter .Same selection lines are applied to the
3to 8 decoder section to generate enable signals for multiplexed
mode seven segments in the FPGA kit.
Block Diagram:
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PROGRAM:
Real Time Clock:
module RTC_FPGA_working_SEVEN( clk1,RST,EN5,EN1,EN4,EN0,EN2,EN3, G,A,B,C,D,E,F);
input clk1,RST;
output EN5,EN1,EN4,EN0,EN2,EN3,G,A;
output B,C,D,E,F;
wire w84,w85,w86,w87,w88,w89,w90,w91;
wire w92,w93,w94,w95,w96,w97,w98,w99;
wire w100,w101,w102,w103,w104,w105,w106,w107;
wire w108,w109,w110,w111,w112,w113,w114,w115;
wire w116,w117,w118,w119,w120,w121,w122,w123;
wire w124,w125,w126,w127,w128,w129,w130,w131;
wire w132,w133,w134,w135,w136,w137,w138,w139;
wire w140,w141,w142,w143,w144,w145,w146,w147;
wire w148,w149,w150,w151,w152,w153,w154,w155;
wire w156,w157,w158,w159,w160,w161,w162,w163;
wire w164,w165,w166,w167,w168,w169,w170,w171;
wire w172,w173,w174,w175,w176,w177,w178,w179;
wire w180,w181,w182,w183,w184,w185,w186,w187;
wire w188,w189,w190,w191,w192,w193,w194,w195;
wire w196,w197,w198,w199,w200,w201,w202,w203;
wire w204,w205,w206,w207,w208,w209,w210,w211;
wire w212,w213,w214,w215,w216,w217,w218,w219;
wire w220,w221,w222,w223,w224,w225,w226,w227;
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Output:
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and and2_co565(w623,w616,w617);
and and2_co566(w626,w624,w625);
and and2_co567(w625,w627,w628);
xor xor2_co568(w631,w629,w630);
dreg dreg9_co569(w629,w632,w631,RST,clk1);
dreg dreg10_co570(w634,w635,w633,RST,clk1);
xor xor2_co571(w633,w634,w636);
dreg dreg11_co572(w638,w639,w637,RST,clk1);
xor xor2_co573(w637,w638,w626);
xor xor2_co574(w640,w624,w625);
dreg dreg12_co575(w624,w641,w640,RST,clk1);
dreg dreg13_co576(w643,w644,w642,RST,clk1);
and and2_co577(w646,w645,w606);
and and2_co578(w648,w643,w647);
dreg dreg14_co579(w650,w651,w649,RST,clk1);
dreg dreg15_co580(w645,w653,w652,RST,clk1);
and and2_co581(w628,w650,w646);
xor xor2_co582(w654,w627,w628);
and and2_co583(w630,w634,w636);
dreg dreg16_co584(w627,w655,w654,RST,clk1);
and and2_co585(w636,w638,w626);
xor xor2_co586(w649,w650,w646);
xor xor2_co587(w642,w643,w647);
xor xor2_co588(w652,w645,w606);
and and2_co589(w595,w621,w623);
dreg dreg17_co590(w657,w658,w656,RST,clk1);
dreg dreg18_co591(w660,w661,w659,RST,clk1);
and and2_co592(w663,w657,w662);
dreg dreg19_co593(w11,w665,w664,RST,clk1);
and and2_co594(w662,w660,w648);
xor xor2_co595(w664,w11,w666);
xor xor2_co596(w656,w657,w662);
and and2_co597(w666,w667,w668);
xor xor2_co598(w659,w660,w648);
dreg dreg20_co599(w667,w670,w669,RST,clk1);
and and2_co600(w647,w629,w630);
xor xor2_co601(w669,w667,w668);
xor xor2_co602(w672,w671,w663);
dreg dreg21_co603(w671,w673,w672,RST,clk1);
and and2_co604(w668,w671,w663);
dreg dreg22_co605(w675,w676,w674,RST,clk1);
xor xor2_co606(w674,w675,w668);
dreg dreg23_co607(w678,w679,w677,RST,clk1);
xor xor2_co608(w677,w678,w666);
endmodule
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RESULT:
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Expt No:
Date :
AIM:
To design pipeline Serial Adder module for adding two 8-bit
numbers using Verilog HDL
APPARATUS REQUIRED:
WORKING:
Step1: Two 8-bit numbers from A, B inputs are stored into two 8-bit shift
registers by activating the LOAD signal.
Step2: These registered inputs from both registers are shifted serially,
From LSB to MSB bits into the 1-bit full adder section by the
arrival of each clock pulse with the LOAD signal as low.
Step3: The carry_out from full adder section is feed back as carry_in to
the same full adder section and the sum Output bits from the full
adder section are entered as serially into the serial in parallel out
shift register by the arrival of each clock pulse.
Step4: The addition process would take 8 clock cycles to complete. The
sum and carry out bits are again stored into Parallel in parallel out
register, by the arrival of the terminal count from the divide by 8
counter sections these sum and carry bits are appeared on out put
LEDs.
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Serial adder
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PROGRAM:
Serial Adder:
module SERIALADDER_TOP( RST,LOAD,A3,A2,A0,A1,A5,A4,A6,A7,B7,B6,B4,B5,B1,B0,
B2,B3,clk1,S3,S4,S0,Cout,S2,S1,S7,S6,S5,Done);
input RST,LOAD,A3,A2,A0,A1,A5,A4;
input A6,A7,B7,B6,B4,B5,B1,B0;
input B2,B3,clk1;
output S3,S4,S0,Cout,S2,S1,S7,S6;
output S5,Done;
wire w50,w51,w52,w53,w54,w55,w56,w57;
wire w58,w59,w60,w61,w62,w63,w64,w65;
wire w66,w67,w68,w69,w70,w71,w72,w73;
wire w74,w75,w76,w77,w78,w79,w80,w81;
wire w82,w83,w84,w85,w86,w87,w88,w89;
wire w90,w91,w92,w93,w94,w95,w96,w97;
wire w98,w99,w100,w101,w102,w103,w104,w105;
wire w106,w107,w108,w109,w110,w111,w112,w113;
wire w114,w115,w116,w117,w118,w119,w120,w121;
wire w122,w123,w124,w125,w126,w127,w128,w129;
wire w130,w131,w132,w133,w134,w135,w136,w137;
dreg #(12) dreg6(w32,w36,w34,w35,clk1);
mux #(10) mux(w34,w32,LOAD,LOAD);
or #(16) or2(w35,RST,Done);
dreg #(12) dreg7(w38,w39,w37,w31,clk1);
dreg #(12) dreg8(Cout,w49,w38,RST,Done);
or #(86) or21(w31,RST,LOAD);
mux #(12) mux_Sh1(w51,w50,A5,LOAD);
mux #(12) mux_Sh2(w53,w52,A6,LOAD);
dreg #(6) dreg2_Sh3(w54,w55,w51,RST,clk1);
dreg #(6) dreg1_Sh4(w52,w57,w56,RST,clk1);
mux #(12) mux_Sh5(w58,w54,A4,LOAD);
dreg #(6) dreg3_Sh6(w60,w61,w59,RST,clk1);
mux #(12) mux_Sh7(w56,RST,A7,LOAD);
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Output:
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RESULT:
Expt No:
PIPELINE
Date :
IMPLEMENTATION OF PARALLEL
ADDER & SUBTRACTOR
AIM:
To design pipelined Adder and Sub tractor for two 8-bit numbers
using Verilog HDL.
APPARATUS REQUIRED:
WORKING:
The adder/subtractor works on the principle of addition of 2s
complement input with another input for subtraction.
Step1: Circuit loads two 8-bit numbers from A, B inputs and stores these
two numbers in two 8-bit registers.
Step2: The registered inputs from B- reg and its complements are applied
to the multiplexer section. By using the selection line Add/Sub of
mux it selects one of the B inputs.
Step3: Multiplexer output is complimented form of B when selection
line as sub and same inputs of B when selection line as add.
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Step4: Both registered outputs are applied to the parallel adder section in
first clock cycle, and result is stored in 9-bit register and
registered output appears on out put LEDs.
Step5: Circuit acts as adder when selection line is zero and acts as
Subtractor when selection line is one.
BLOCK DIAGRAM:
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PROGRAM:
module Adder_Subtractor_Top( B5,addbsub,clk1,RST,A7,A6,A5,A4,
A3,A2,A1,B7,B6,B4,B3,B2,
B1,B0,A0,Q7,COUT,Q0,Q1,Q2,
Q3,Q4,Q5,Q6);
input B5,addbsub,clk1,RST,A7,A6,A5,A4;
input A3,A2,A1,B7,B6,B4,B3,B2;
input B1,B0,A0;
output Q7,COUT,Q0,Q1,Q2,Q3,Q4,Q5;
output Q6;
wire w68,w69,w70,w71,w72,w73,w74,w75;
wire w76,w77,w78,w79,w80,w81,w82,w83;
wire w84,w85,w86,w87,w88,w89,w90,w91;
wire w92,w93,w94,w95,w96,w97,w98,w99;
wire w100,w101,w102,w103,w104,w105,w106,w107;
wire w108,w109,w110,w111,w112,w113,w114,w115;
wire w116,w117,w118,w119,w120,w121,w122,w123;
wire w124,w125,w126,w127,w128,w129,w130;
not #(17) inv(w21,RST);
dreg #(12) dreg2(w23,w24,w22,RST,clk1);
not #(10) inv(w66,w23);
mux #(10) mux(COUT,w23,w66,addbsub);
not #(10) inv(w67,w21);
mux #(17) mux(w50,w67,w21,addbsub);
dreg #(3) dreg16_re1(w16,w68,B4,RST,clk1);
dreg #(3) dreg17_re2(w15,w69,B3,RST,clk1);
dreg #(3) dreg18_re3(w13,w70,B0,RST,clk1);
dreg #(3) dreg19_re4(w12,w71,B1,RST,clk1);
dreg #(3) dreg20_re5(w14,w72,B2,RST,clk1);
dreg #(3) dreg21_re6(w18,w73,B6,RST,clk1);
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RESULT:
Expt No:
Date :
IMPLEMENTATION OF PARALLEL
PIPELINE ADDER
AIM:
To implement Parallel Pipeline Adder using Verilog HDL
APPARATUS REQUIRED:
WORKING:
Step1: Circuit loads two 8-bit numbers from A, B inputs and stores these
two numbers in two 8-bit registers, also store carry input in one
bit register.
Step2: Registered two 8-bit inputs and carry input are applied to the
parallel adder section in first clock cycle.
Step3: 8-bit sum and single bit carry out puts from the parallel adder are
stored in 9-bit registers and the result appears on output LEDs in
the second clock cycle.
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BLOCK DIAGRAM:
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PROGRAM:
module Adder_Par_Top( Cin,RST,B7,clk1,A7,A6,A5,A4,
A3,A2,A1,A0,B6,B5,B4,B3,
B2,B1,B0,R0,R7,R6,R5,R4,
R3,R2,R1,Cout);
input Cin,RST,B7,clk1,A7,A6,A5,A4;
input A3,A2,A1,A0,B6,B5,B4,B3;
input B2,B1,B0;
output R0,R7,R6,R5,R4,R3,R2,R1;
output Cout;
wire w58,w59,w60,w61,w62,w63,w64,w65;
wire w66,w67,w68,w69,w70,w71,w72,w73;
wire w74,w75,w76,w77,w78,w79,w80,w81;
wire w82,w83,w84,w85,w86,w87,w88,w89;
wire w90,w91,w92,w93,w94,w95,w96,w97;
wire w98,w99,w100,w101,w102,w103,w104,w105;
wire w106,w107,w108,w109,w110,w111,w112;
dreg dreg1(w3,w47,Cin,RST,clk1);
dreg dreg2(Cout,w57,w18,w56,clk1);
or or2_fa1_pa1(w60,w58,w59);
xor xor2_fa2_pa2(w61,w1,w3);
and and2_fa3_pa3(w59,w1,w3);
and and2_fa4_pa4(w58,w61,w2);
xor xor2_fa5_pa5(w19,w61,w2);
or or2_fa6_pa6(w64,w62,w63);
xor xor2_fa7_pa7(w65,w4,w60);
and and2_fa8_pa8(w63,w4,w60);
and and2_fa9_pa9(w62,w65,w5);
xor xor2_fa10_pa10(w20,w65,w5);
or or2_fa11_pa11(w68,w66,w67);
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Output:
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xor xor2_fa30_pa30(w24,w81,w13);
or or2_fa31_pa31(w84,w82,w83);
xor xor2_fa32_pa32(w85,w14,w80);
and and2_fa33_pa33(w83,w14,w80);
and and2_fa34_pa34(w82,w85,w17);
xor xor2_fa35_pa35(w25,w85,w17);
or or2_fa36_pa36(w18,w86,w87);
xor xor2_fa37_pa37(w88,w16,w84);
and and2_fa38_pa38(w87,w16,w84);
and and2_fa39_pa39(w86,w88,w15);
xor xor2_fa40_pa40(w26,w88,w15);
dreg dreg16_re41(w11,w89,A4,RST,clk1);
dreg dreg17_re42(w9,w90,A3,RST,clk1);
dreg dreg18_re43(w2,w91,A0,RST,clk1);
dreg dreg19_re44(w5,w92,A1,RST,clk1);
dreg dreg20_re45(w7,w93,A2,RST,clk1);
dreg dreg21_re46(w17,w94,A6,RST,clk1);
dreg dreg22_re47(w15,w95,A7,RST,clk1);
dreg dreg23_re48(w13,w96,A5,RST,clk1);
dreg dreg16_re49(w10,w97,B4,RST,clk1);
dreg dreg17_re50(w8,w98,B3,RST,clk1);
dreg dreg18_re51(w1,w99,B0,RST,clk1);
dreg dreg19_re52(w4,w100,B1,RST,clk1);
dreg dreg20_re53(w6,w101,B2,RST,clk1);
dreg dreg21_re54(w14,w102,B6,RST,clk1);
dreg dreg22_re55(w16,w103,B7,RST,clk1);
dreg dreg23_re56(w12,w104,B5,RST,clk1);
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RESULT:
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Step 3: In the New Project window enter project name and project
location.
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Step 6: Enter the file name and then select Verilog module.
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Step 7: Define the input and output port names ,then click Next for all
successive windows.
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Step 9: Double click the Verilog file and enter the logic details and save
the file.
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Step 10: Double click Synthesize XST for checking the syntax .
Step 11: Right click the halfadd.v file and select new source ,then click
Implementation Constraints File and enter the filename.
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Step13: Open the .ucf file and enter the pin location and save the file
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Step 15: In Slave Serial mode ,right click and select Add Xilinx Device.
Step 16: In the Add Device window select the .bit file to add the device.
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Step 17: Connect the RS232 cable between computer and kit. Connect the
SMPS to kit and switch on the kit.
Step 18: Right click the device and select Program to transfer the file to
kit.
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