计算机体系结构讲义

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.()
1.
ENIACElectronic Numerrical Integrator And Computer
EDVACElectronic Discrete Variable Automatic Computer

2. P2
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1. P21.1
MAR
2.
RD
WR
00000H
101010010
FFFFFH
MDR
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1.
2.(P7)
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CPU
MAR
ALU
PC
ID
FR
IR
+1
MDR
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BUS *I/O
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.
Microprocessor,Microcomputer,Microcomputer System
ALU
ROM
I/O
I/O
I/O
RAM
AB
DB
CB
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.
1.
Intel 8080,8085;
Intel 8086,80286,80386,80486;
Pentitum,Pentium II(P6),Pentium III,Pentium IV.
Zilog Z80; Z8000; Z80000.
Motorola MC6800(8),MC6800016,MC68020(32)
Power PC 620(64)
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.
1.Moore
231824
Gordon Moore1965
* Gordon MooreInter
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.
1978
8086
2.9 3
1982
80286
13.5
1985
80386
32
1990
80486
120
1993
Pentium
320
1996
Pentium Pro 550
19972
Pentium II 750300MHz
1999
Pentium III
2000(4) Pentium IV 42001.4GHz(0.18um)
Bill GatesMoore20..
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.
CPUCentral
Processing Unit
I/O
1ALU
SUB AL5 AND ALFEHADD AL10OR AL01H
2/
IN AL50H OUT 51HAL
3Program Counter--PCInstruction Counter
1
4
5
6
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.
1.
2.
,4~64;
,
I/O
CPU
3.()
CPU++I/O+
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Data Bus --DB--

Address Bus---AB--
Control BusCB--
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4.
(1):.
4816
3264
(2):
(Byte)128MB---2pXq.
(3):
MIPS(Million Instruction Per Second)
(4)()
MTBF(Mean Time Between Failures),
(5)/
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5.
*SPEC(Standard Performance Evaluation Corporation)
SPECBenchmarksSPEC89
*iCOMP(intel Comparative Microprocessor Performance)
1992iCOMP Index 1.0

1996iCOMP 2.0
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.-- Intel
CPU
InteliCOMP
iCOMP Index 1.02.0

Intel
Intel1992iCOMP
iCOMP Index1.0()
iCOMP Index1.0
DOS16CAD/CAM16
UNIX3232
16321632
BMbenchmark,P1-6
0Intel
3D
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.-- Intel
1-6 iCOMP 1.0
(P)
16
ZD Labs CPUmix
67%
16
Whetstone
2%
16
ZD Labs CPUmix
1%
32
SPEC int92
25%
32
SPEC fp 92
5%
16
ZD Labs/SPEC int92
0%
32
ZD Labs/SPEC int92
0%
16
ZD Labs/SPEC int92
0%
32
ZD Labs/SPEC int92
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0%
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.-- Intel
iCOMP Index1.0FPU25MHz80486(486SX-25)
(Base)iCOMP100
iCOMP
iCOMP = 100 X [(
BM 9
BM 1
BM 2
) P1 +
) P2 + ...... +
) P9 ]
Base _ BM 1
Base _ BM 2
Base _ BM 9
Base-BMi486SX_25i BMi
iPii
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.-- Intel
Pentium
iCOMP1.0
CPU
(MHz)
(MHz)
iCOMP1.0
Pentium-60
60
60
510
Pentium-66
66
66
567
Pentium-75
75
50
1.5
610
Pentium-90
90
60
1.5
735
Pentium-100
100
66
1.5
815
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Each short block is 8-bits long
General Registers
EAX
AH
EBX
BH
ECX
CH
EDX
DH
Segment Registers
AX
BX
CX
DX
AL
CS
BL
DS
CL
ES
DL
SS
EBP
BP
ESI
SI
EDI
DI
ESP
SP
Flags Register
EFlags
Instruction Pointer Register
EIP
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Some of the registers in the Pentium
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Understanding Personal Computers
Code Cache
8KB
256bits
Instruction Prefetch
64-bit data bus
control bus
Bus Interface
32-bit address bus
32
pentium
Microcode
ROM
Decode Unit
32
Execution Unit
ALU
ALU
1 1 01 1 1 0 10 1
0 0 00 0 1 0 10 1
32
32
Data Cache
8KB
Floating
Point
Unit
Registers
(16&32bits wide)
Internal view of a Pentium(simplified)

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**
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CPU
CPU
Intel 8086
8086
1979VLSIHMOS
2.9
16202201M16
+5V
5MHz808610MHz808618MHz80862
133160.4us0.5us
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**
Intel 808816
168
80888086
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**
1.80862.1
BIU(Bus Interface Unit);
EU(Execution Unit).
(1).BIU
416CSDSESSS
116IP1
6; /
BIUI/O
BIU
EUBIUEUI/O
EUI/O
IN AL,50H;ADD AL,[2035H].
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()
(1)CPU>>>
8086BIUEUEU
BIU
BIUEUEU
CPU
PipeLine Computer
(2)20
CPU
808600000HFFFFFH2201M
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()
80861616
2201M
1M64K
16
Offset
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()
16
CSDSSSESBXBPIPSP
SIDIEAEffective Address*
1200H:0345H12345H
1100H:1345H12345H

MOV AX,[BX];
MOV AX,[BX+SI];
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()
X16+
15
15
0000
19
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()
1.(CS)=4232H ,(IP)=66H
42320H
66H
4 2 3 2 0 H
64K
216
64K
42386H
6 6 H
...
...
4 2 3 8 6 H
5231FH
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()
2.
(DS)2234H EA22H
15
0
2 2 3 4
15
2 2 3 4
0 0 2
2 2 3 6
0
0 0 2 2
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()
(2)EUExecution Unit
ALU
AX,BX,CX,DX;
BP()
SP()
SI()
DI()
FR
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()
15
14
13
12
11
10
OF
DF
IF
TF
SF
ZF
4
AF
2
PF
0
CF
Trace Flag
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()
1.
STATE:
IN AL, 0DAH;
TEST AL, 02H;
JZ STATE
ZFZero Flag0ZF1ZF0
1MOV AL, 4
ZF1
SUB AL, 4
2XOR AX, AX
ZF1
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()
CFCarry Flag
D7D15
D7D15
MOV AL, 3;
SUB AL, 4;
CF1
PFParity Flag81
PF1PF0
MOV AL, 2
ADD AL, 1
PF1
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()
AFAuxiliary carrry Flag
34;
34
OFOverflow FlagOF1
2. (3)
SetReset
IFInterrupt Enable FlagIF1CPU
CPU
10 IF
STI IF1
CLI IF0
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()
DFDirection FlagDF
0DF1
STD CLD
TFTrap FlagTF1CPU
3.BIUEUP19
*Pipeline Computer
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()
0
EA
EA
EA
38
3X618
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()
*1990
RISCCISC
CPU
1.fetch
2.decoding);
3.EAEffective Address
4.
5.
6.
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()
CPU
1
2
1
3
2
BIUEUCPU
BIU
EU
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()
4
80868038614
AX,BX,CX,DX;SP,BP,SI,DI;CS,DS,SS,ES;IP,FR.
Pentium
Some of the registers in the Pentium
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()
8086/8088IO
8086/8088
BIUIO
8086/80884
IO
T31Tw
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()
T1
T2
T3
Tw
T4
TI
TI
T1
T2
T3
BIUI/O
BIUEU
BIU
Ti
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()
CPU8086

8086
8086
8086
COProcessor
8086
8087/8089
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()
CPU
Ready
T1
T2
T3
CLK
READY
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Tw
T4
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()
TEST
8087
8087BUSY
8086TEST8086
WAITTEST
TEST
8086
TESTWAIT
8086
TEST
+5V
BUSY
8087
*8087Math. CO-Processor
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()
BHE/S78/BUS High Enable/Status
80861688
8816BHE
P2322
INTRMaskable
INTA
CPUINTRINTR
IF=1CPU
INTA
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()
NMI(Non-Maskable Interrupt request):

IF
WR:
RD:
CPU()
IO()IOCPU
M/IO
M/IO(Memory / IO):IO
CPU
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()
HOLD(Hold request):
HLDA(Hold Acknowledge):
T1
T2
T3
T4
CLK
HOLD
HODA
AD15AD0 , A19/S6A16/S3
WR,RD,
CPU
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()
CPUHOLD
(T4)HLDA
HOLDCPU/
()
(DMAC)HLDA
HOLDHLDA
()HOLD
CPUHOLDHLDA
CPU
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()
()
ALE(Address latch Enable):
8086/8088
I/O
8086/80888282/8283,
ALE(P342.12)
*Intel 8282(8)(
2.13)
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()
DEN(Data Enable):
(8286/8287)
DT/R(Data Transmit/Receive)/
2.152.16
*Intel 8286 /8287 8
SS0:
SS080808086BHE/S7;
8088SS0M/IO,DT/R8(000111)
(I/OI/O
)
MN/MX:/
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()
(Data Latch)
Q
83
1
1
0
0
0
1
0
1
0
1
(D)
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()
8.6
D
t2D
t0
t1
QD
t2
8.7
n
D0
D1
n-1
Q0
Q1
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n-1
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()
()80862.12
1MN/MX+5V8086
238282
328286418284
()8086/8088
MN/MX8086/80882431
1.
2.
QS1,QS0
(8087) 8086/8088
S2 S1S0 Bus Cycle Status)
S2 S1S082882.18
8288S2 S1S0 IO
MRDC, MWTC, IORC, IOWC)INTA, DT/R, DEN,
ALE)
8259 8286
8282
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()
.
1.8086
1M512K
D7-D0
D15-D8
BHE
A0
A19 -A1
D7-D0

SEL A18-A0
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D15-D8

SEL A18-A0
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()
8 D7-D0
8 D15-D8
BHE0A00
*EVEN
EVEN
DATA-SEG SEGMENT
EVEN
WORD-ARRAY DW 100 DUP(?)
DATA-SEG ENDS
2. 8088P32 2.11
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()
. CPU
1.P43
(T
)
M1(Machine Cycle)
(
M2()
M3()
* BIU
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()
ABCPU
ACPU8MHzB12MHz4
A0.4MIPS,
BMIPS?
10 6 s
A
0 . 4 10
= 2 .5 s
2 .5 s
= 5
0 . 125 s 4
B0.4 MIPS X 12/8=0.6 MIPS
1
1
12 10
= 0 . 6 MIPS
4 5
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()
2.
210
3.
1
2
3
4
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()
T1
CLK
M/IO
A19/S6-A16/S3
T2
T3
Tw
T4
BHE/S7
AD15-AD0
ALE
READY
RD
DT/R
DEN
8086
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()
1.8086T
2.TW
CPU80861
400nsCPU
3.80x86CPU
(1) MOV AX,32C5H

(2)MOV AX,0E453H
ADD AX,546AH
ADD AX,0C572H
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()
4. 16CPU20MHz4
Tw
Bytes/Sec
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1.
2.
3.
4.
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(field)
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1 INC
AX
ADD AX, BX
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.8086
1.
2.
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(Immediate
addressing)
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example
MOV AL, 80H ;
AX
MOV AX, 3064H ;
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64
ADD AL, 20H ;

ADD AX, 1090H;
OP
30
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81616
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Register
addressing)
8 AH, AL, BH,

BL, CH, CL, DH, DL .
16AX, BX,
CX, DX, SI, DI, SP BP
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EXAMPLE
INC AX
MOV AX, BX
DEC AX
ROL AH , 1
AH
CF
D7
D0
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CPU
2
*
MOV BX , AX )
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Direct
Addressing)
EA Effective Address)
EA
EA
()
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,
)
1. MOV AX , [2000H]
(DS)= 3000H,
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OP
00
20
DS.
50
30
30000H AX
32000H
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MOV AX , ES : [3000H] ;
ES: MOV AX , [3000H] ;
( MOV [2000H] , [3000H] )
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() (Register
indirect Addressing)
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(BX,BP,SIDI),
EA=
[BX].. DS
[BP].. SS
[SI] ..DS
[DI] .DS
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Example
MOV AX , [BX] ;
( DS) = 2000H ,(BX) = 1000H
20000H 1000H =21000H
AX
*
A0H
50 H
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MOV AX,ES:

Register relative addressing)
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816
BX,SI,
DIDS
BPSS.
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EA =
[BX]
[BP] +
[SI]
[DI]
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16
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Example
MOV AX, [SI+3000H]

OP
OP
(DS)4000H,(SI)=2000H
00
30
40000H+2000H+3000H
45000H
34
AX
40000H
12
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43000H
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Based
indexed addressing)
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[BX]
[SI]
BX,
DS
EA
ss
+
[BP]
[DI]
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BP,
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Example
MOV AX,[BX+DI]
(DS)=2100H,(BX)=0158H,[DI]=10A5H.
EA= 0158H+10A5H=11FDH
21000H+11FDH=221FDH
*
[BX]
21000H
),
21158H
AX
34
12
221FDH
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( )
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(Relative based indexed
address~)
816
[BX] [SI]
BX,
DS
EA=
SS
+
[BP]
+
[DI]
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BP,
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MOV AX,[BX+SI+0250H]
OP
(DS)=3000H,(BX)=2000H,(SI)=1000H,
OP
EA 2000H+1000H+0250H=3250H
50
02
30000H+3250H=33250H
AX
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[BX] 30000H
32000H
34
32250H
12
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BP(MOV BP,SP).
(SIDI)
[BP]
[SI]
A(0)
A(1)
A(n)
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8086
1.
2.
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. 8086
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1.
(MOV
(PUSH,POP)
(XCHG)
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(1) MOV
MOV DST,SRC;
DST
SRC
CPU
(.
: MOV AL, BL;
MOV [DI], AX;
MOV CX,[1000H];
MOV BL, 40
MOV WORD PTR[SI],01H;
BYTE PTR
WORD PTR
DWORD PTR

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MOV
2035H
01H
.
02H
2045H
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MOV BL, [2035];

MOV CL,[2045H];
MOV [2045H],BL;
MOV [2035H],CL;
HLT
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MOV SI , 2035H;
MOV DI, 2045H;
MOV AH, [SI];
MOV AL, [DI];
MOV [2035H],AL;
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MOV [2045H] AH
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BLOCK1BLOCK2
2040H
BLOCK1
2060H
BLOCK2
2040H102060
10
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3
2040H10
2060H10
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ANSWER
START: MOV SI, 2040H ;
MOV DI, 2060H ;
MOV CX, 0AH;
LOOP1: MOV BL, [SI+09H];
MOV [DI+09H],BL ;
DEC SI ;
DEC DI ;
DEC CX ;
JNZ LOOP1;
HLT ;
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(2)
* [
PUSH
SRC
(SS)
SP
SP-2
SP+1,SP)
SRC
(SP)
DST
POP
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DST
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POPF
O D I T S Z A P C
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3
XCHG OPR1, OPR2
OPTR1
OPTR2
O D I T S Z A P C
- - - - - - - - XCHG AL,BL;
XCHG BX,CX;
XCHG [2530], CX;
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XCHG
MOV BL , [SI +09H];
XCHG BL , [DI+09H];
MOV [SI+09H], BL;
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2.
(INOUT
(XLAT)
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(1)
<1>
IN AL, PORT ;:AL

IN AX, PORT;
OUT PORT,AL;
(PORT)
AX
(PORT+1,PORT)
(PORT)
AL
OUT PORT,AX;
(PORT+1,PORT)
AX

PORT0255(00~FFH)
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<2>
IN AL, DX; AL
(DX)
IN AX, DX;
AX
OUT DX,AL;
(DX)
(DX+1,DX)
AL
OUT DX,AX;
(DX+1,DX) AX

DX.
MOV DX,XXXXH;
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0:8
1110
1:16
10W
PORT
0
1
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1110
PORT
11 W
0 ()
1(
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IN
.
IN AL, 27H;
IN AL ,28H;
MOV [2000H],AL;
AL,000001000B;
TEST
JNZ ERROR
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OUTI/O
26H()7
COM- REG
EQU 26H
BEGIN- BIT
EQU 10000000B
MOV AL, OTRCNBITS;

OR AL, BEGIN-BIT;
OUT COM-REG, AL;
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(2)XLAT(Translate)
XLAT BX
()
AL
XLAT
AL
MOV BX, 1000H;(TABLE)
MOV AL, 05H;
XLAT;AL5
HLT
00001010
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2 8255P231
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3.
LEA (Load Effective Address)
LDS (Load pointer into register and DS)
LES (Load pointer into register and ES)
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LEA REG , SRC;

REG
SRC; --------*EA
16
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LEA BX,[BX+DI+6H]
(BX)=1000H,(DI)=0200H,
,(BX)=1206H
MOV BX,[BX+DI+6H]
LEA AX,VAR
MOV AX,VAR
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2 LDS REG,SRC
REG
(SRC)
DS
(SRC+2)
--------(4
DS
(
()
DS
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Example
1. LDS DI,[2130H]
(DS)=3000H
32130H
DI
DS
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2 P62
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(3) LES REG,SRC
REG
ES
(SRC)
(SRC+2)
* LDSLES
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4.
: LAHF
8
AH
: SAHF
8
AH
PUSHF
POPF
P62~P63
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()
1.
ADD DST,SRC
ADC DST,SRC
SUB DST, SRC
SBB DST,SRC
DST
DST
DST
DST
SRC+DST
SRC+DST+CF
DSTSRC
DST-SRC-CF
O D I T S Z A P C
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Example
W
X+Y+24Z(X.Y.Z
MOV AX, X ;
ADD AX, Y ;
ADD AX, 24 ;
SUB
AX, Z;
MOV W, AX;
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Example
(
16)
2000H
3000H
16
16
16
16
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2000H()
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MOV
MOV
MOV
ADD
SI , 2000H ;
AX, [SI] ; 16AX
DI ,3000H;
AX, [DI] ; 162 16.(
CF,CF)
MOV [SI],AX; 16
MOV AX, [SI+2];
ADC AX,[DI+2];16CF(16).
MOV [SI+2],AX; 16.
((
)
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3
() 2500H

2000H3000H(),
2000H
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2. 1 1
1
INC OPR
OPR OPR+1
1
DEC OPR
OPR OPR-1
(Negate) NEG OPR
OPR OPR
CMP OPR1,OPR2 OPR1OPR2

INCDEC: O D I T S Z A P C
- - - NEGCMP: - - -
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NEG
NEG
NEG
(
(NEG
()
1.
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Example
* AL=00010001B=+17,NEG AL
AL=11101111B=[17]
*
AL=11010001B=[47]NEG
AL
AL=00101111B=+47
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CMP(JZ ,
JG , JO
. X>50,TOO-HIGH;
XYOVERFLOW;
X-Y ,RESULT(
X,Y,RESULT
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.
MOV AX , X ;
(X)AX
CMP AX , 50;
JG TOO-HIGH;
(X)50, TOO-HIGH
SUB AX, Y;
(Y)
JO OVERFLOW;
JNS NONNEG ;
NEG AX;
NONNEG: MOV RESULT , AX ;
RESULT
TOO-HIGH:
OVERFLOW:
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3.
CBW ALAH
CWD AXDX
.
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4.
1.
*IMUL SRC
*
: AX
(Al)*(SRC)
DX:AX
(AX)*(SRC)
(
2.
*MUL SRC
*
IMUL,
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5.
*IDIV SRC
*
AL
(AX)/(SRC)
AH
(AX)/(SRC)
AX
(DX:AX)/(SRC)
DX (DX:AX)/(SRC)
.

*DIV SRC
*
IDIV
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O D I T S Z A P C
IMUL U U U U X
MUL U U U U X
IDIV
U U U U U U
DIV
U U U U U U
X
U

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AX (V-(X*Y+Z-540))/X
DX
X Y Z V
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MOV AX, X;
IMUL Y;
MOV CX, AX;
MOV BX, DX;
MOV AX, Z;
CWD
ADD CX, AX;
ADC BX, DX;
SUB CX, 540;
SBB BX, 0;
MOV AX, V;
CWD;
SUB AX, CX;
SBB DX, BX;
IDIV X;
PROGRAM
X*Y,DX:AX
BX:CX
ZBX:CX
BX:CX540
V(BX:CX)
X,AXDX
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6. BCD
BCD
(Binary Coded Decimal),4
(00001001BCD
10101111BCD).
BCD2BCD
0011 0111
37
BCD4BCD
40.
37
0000 0011
0000 0111
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(1)BCD
1 18 7 25
0 0 0 1 1 0 0 0 - - - - - - - - 18
+0000 0111-------- 7
0001 1111-------- ?
(1111BCD
(),6
0001 1111
+0000 0110
0 0 1 0 0 1 0 1 - - - - - - - - 25(
)
34(
)AF=1
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BCD
BCD6
16
BCD
110 (6)
BCDBCD
9(1010~1111),6
()
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BCD
2 19 + 8 = 27
0 0 0 1 1 0 0 1 --------- 19
+ 0 0 0 0 1 0 0 0 --------- 8
0 0 1 0 0 0 0 1----------21()
(AF=1CF=1),
16106
6.
0010 0001
+0000 0110
0 0 1 0 0 1 1 1-----------27(
BCDAF=1(CF1)4
(4)6
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BCD
BCD
BCD1010
1111
(AF=1CF=1),
6(0110B)
BCD
1.AF=1,
6
2. CF=1,
6
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(2)BCD
*
DAA
AL
ALBCD
*
DAS
AL
ALBCD
DAADecimal Adjust for Addition
DAS Decimal Adjust for Subtraction
O D I T S Z A P C
U
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BCD3 BCD1+BCD2
BCD1BCD2,BCD3
4BCD
(BCD1) =1834 , (BCD2) = 2789.
AL, AF, CF
3
1
4
8
8 9
2 7
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2 3
4 6
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MOV AL, BCD1;
AL 34
AL CF AF
34
ADD AL, BCD2;

DAA
;
AL 34+89 BDH
23
BCD
MOV BCD3,AL;
(BCD3) 23
23
1
*
MOV AL, BCD1+1;
AL 18
18
1
*
0
1
ADC AL, BCD2+1; AL 18+27+CF 40H
46 BCD 0
*
DAA
;
0
*
MOV BCD3+1,AL; (BCD3+1) 46 46
183427894623
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BCD
8086BCD
8086BCD
BCD
(BCD)
BCD
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(3)BCD
(AAA)
(AAS)
(AAM)
(AAD)
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()
1.
NOT OPR
OPR OPR
OR DST,DST
DST DST V SRC
AND DST,SRC
DST DST
SRC
XOR DST,SRC
DST DST
SRC
TEST OPR1,OPR2 OPR1 OPR2
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2.
SHL OPR,CNT
CF
(OPRCNT1CL)
CF
SAL OPR,CNT
1()0 11 0)OF=1,
OF 0
SHR OPR,CNT 0
SAR OPR,CNT
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CF
CF
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.
00.
.
0.
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3.
ROL OPR ,CNT

CF
ROR OPR , CNT
CF
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RCL OPR , CNT

CF
RCR OPR , CNT

CF
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(CFJC
JNC
n2 (n)
62 (2) 0000011010000011000
* n2(n)
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1AL
10(10x)
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SAL
MOV
MOV
SAL
ADD
AL, 1 ; AL12x
BL, AL; 2xBL.
CL, 2 ; CL
AL,CL; 2x28x
AL, BL; 2x 8x,AL10x
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Example
2UNPACKED16
BCDBCD
PACKED
0000
4
5
4
UNPACKED
0000
0000
0000
5
6
7
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PACKED
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MOV DX, 8; 8
MOV CL, 4; 4
MOV SI, 0;
MOV DI, SI;
CONVERT:MOV AX, WORD PTR[SI+UNPACKED];
SHL AL, CL;
SHR AX, CL;
MOV PACKED[DI], AL;
ADD SI, 2;
INC DI ;
DEC DX ; 1
JNZ CONVERT
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()
DI+1
DI+2
DI+1
DI+2
MOVSB (DI) (SI),SI SI+1,DI

MOVSW (DI) (SI),SI SI+2,DI
CMPSB (SI) (DI), SI SI+1,DI
CMPSW (SI) (DI), SI SI+2,DI
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4REP
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Example
1. (MOVSB)
2..(P76)
3. (P77)
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()
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JMP 1000H ;
JMP AX;
(
JMP 2500H:3600H
JMP DWORD PTR[DI]
DI,DI+1,DI+2,DI+3
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1.
: JMP SHORT OPR (

: IP IP+8 (128~+127)
: : JMP NEAR PTR OPR(
)
: IP
IP+16(32768~
+32767)
2. :
: JMP WORD PTR OPR(

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3.()
: JMP FAR PTR OPR ()
: IP OPR
CS OPR
4.
: JMP DWORD PTR OPR
: IP (EA)
CS (EA+2)
: JMP DWORD PTR [BX+DI+6]
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MOV CX , N
BEGIN:
.
.
.
DEC CX
JNZ BEGIN
LOOP BEGIN
LOOP
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LOOP OPR
CX =
LOOPZ OPR/LOOPE OPR ZF=1

CX=0
LOOPNZ OPR/LOOPNE OPR
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CX=0
ZF=0
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1.CX CX1
2.OPR
3.(ZF
CX1ZF=1CX
0ZFCX
0.)
100
$( P81)
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(1)
Call DST
SP
SP-2
(SP+1,SP)
IP(
IP
)
Call
DST
IP+(
SP SP-2
(SP+1,SP) IP
IP (EA) (EA:DST
)
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Call DST
SP
SP-2
(SP+1,SP)
SP SP-2
CS
(SP+1,SP) IP
IP
CS
all FAR PTR Display

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Call DST
SP
SP-2
(SP+1,SP)
SP SP-2
CS
(SP+1,SP) IP
IP
CS (EA+2)
EA:DST
Call DWORD PTR [BX+SI]

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(2)
RET (C3H)
RET n
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IP
IP
(SP+1,SP)
SP SP+2
(SP+1,SP)
SP SP+2
SP
SP+n(n
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(2)
RET (CBH)
RET n
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IP
IP
(SP+1,SP)
SP SP+2
CS (SP+1,SP)
SP SP+2
(SP+1,SP)
SP SP+2
CS (SP+1,SP)
SP
SP+2
SP SP+n(n)
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()
Proc-A
PROC NEAR(FAR)
____________
____________
.
.
.
____________
RET
ENDP
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RET n
.FFIT
FFIT
ESDI ,
DISPLAY
FFIT:
call
FFIT
DISPLAY:
call DISPLAY
ret 4
ret
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RET
DISPLAY
AX
DI
ES
BP
SP
FFIT
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FFIT
FFIT: PUSH BP
MOV BP, SP
PUSH ES
PUSH DI
LES DI , [BP+04]; ESDI
AAA: ES:MOV AL, [DI]; ESDI
CMP AL,00
;
JZ EEE
PUSH AX
;DISPLAY(
)
CALL DISPLAY
INC DI
JMP AAA
EEE: POP DI
POP ES
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POP BP
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1.
(1)AND AX , 00FF H;
(2) ADD AL , [BX+100];
(3)
MOV BX , [SI+BX];
(4) MOV [BX+DI+10H], AH ;

(5) MOV [BP+1054H], AX ;
(6) ADD AX, [SI];
(7) MOV SI, 100 ;
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2. (DS)=4000H,(BX)=3000H,(SI)=2000H,
(DI)=1000H,134
3. (CS)=2500H,(DS)=2400H,(SS)=2430H,
(ES)=2530H,(BP)=0200H,(SI)=0010H,(DI)=020
6H,
MOV AX,[BP+SI+4]
______________,
__________;
MOV AX, [DI+100]
_____________,
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4. AX,BX,CX,DX1020
3040PUSH AX, PUSH BX,
POP CX, POP DX, PUSH CX, PUSH DX,
POP AX,POP BX AXBX
5. ( )2500 H
2000H
3000 H (),
2000H
6. P87(3) 7. P87(7)
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8. P116(5)
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Assemble Language
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Assemble Language
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1.
2.
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Edit.exe
Prog.asm
Prog.obj
Masm.exe
Prog.exe
Link.exe
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1.
2.
3.
4.
.OBJ)
.LST
.CRF
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MASM.EXE
.ASM
.OBJ
.LST
.CRF
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1.
ASM.EXE
MASM.EXE
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2.
OBJ
.EXE
LINK.EXEOBJ
EXE
MAPLIB
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LINK.EXE
.OBJ
.OBJ
.EXE
.LIB
.MAP
.LIB
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3. (DEBUG.COM)
>DEBUG PROG.EXE
- U ()
- g =
- T =
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Handwritten source program
EDIT Editor program

MASM assembler program
PROG1.LST
Libraries
PROG1.OBJ
LINK linker program
DEBUG debug program

Final debugged run module
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PROG1.CRF
Other
.OBJ files
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BIOSDOS
ROM BIOS(Basic Input Output System)

0FE00H8k ROM
I/O
BIOS
I/O
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INT XXH
MOV CX,0;
MOV DX,0;
MOV AH,1; 1
INT 1AH;
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DOS DOS
21H
/
$:
MOV DL,$; (24H)
MOV AH,6;
6
INT 21H;
DOS
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MACRO)
Macro-name
MACRO
ENDM
[dummy Parameter List]
MACROENDM
.
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Macro-name [actual parameter list](

)
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SAVEREG MACRO
PUSH AX
PUSH BX
PUSH CX
PUSH DX
PUSH SI
PUSH DI
ENDM
SAVEREG

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2
FOO MACRO P1, P2, P3
MOV AX, P1
P2 P3
ENDM
FOO WORD_VAR, INC, AX
MOV AX, WORD_VAR
INC AX
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XA,yB
Qx,y
CALL Q
xC,yD
CALL Q
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Q:
.
.
.
RET
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Qx,y
Q A,B
Q(A,B)
Q C,D
Q(C,D)
Q MACRO x,y
ENDM
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1.
2.
3.
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(P88)
DATA SEGMENT
NUM DW 0011101000000111B
NOTES DB The result is :,$
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
BEGIN:
MOV AX, DATA
MOV DS,AX
MOV DX,OFFSET NOTES
MOV AH,9H
INT 21H
MOV BX,NUM
MOV CH,4
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ROTATE :
MOV CL, 4
ROL BX,CL
MOV AL,BL
AND AL,0FH
ADD AL,30H
CMP AL,9
AX,4C00H
JLE DISPLAY
ADD AL,07H
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DISPLAY:
MOV DL, AL
MOV AH,2
INT 21H
DEC CH
JNZ ROTATE
MOV
INT 21H
CODE ENDS
END BEGIN
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STACK SEGMENT STACK

STA DB 50 DUP (?)
TOP EQU LENGTH STA
STACK ENDS
CODE SEGMENT
ASSUME CS:CODE,DS:DATA,ES:DATA,SS:STACK
START:MOV AX,DATA
MOV DS,AX
MOV AX,STACK
MOV SS, AX
MOV SP,TOP
:
CODE ENDS
END START
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CPU(
I/O)
DMA(Direct Memory Access)
CPU
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(Peripheral
Device)/
(INOUT)
()
CPU
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CPU
CPU
CPU
I/O
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CPU
()
(P117)
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()CPU
(
)
CPU
CPU
(
)
(PUSH)
(POP)
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(
)
(CPU)
(
)(Z8080X86)
P11816
8086/8088
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123456
3()
3(
)
CPU
()
(FR)
()
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1.(Priority)
CPU
()
()
(daisy chain)
(8259)
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(1)
7
INT
XXH
CRT
INT
CPU
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(2) *
CPU
INT1
INT2
INTA
INTR
+5V
INT1+INT2+INT3
(OC)
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INT3
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(2)
INTR=INT1+INT2+INT3
INTA
CPUINT
INTA
()
INTA
INTR
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(3)(8259)
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2.
STI
STI
..
.
IRET
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IRET
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8086/8088
.8086/8088
(5.1)
NMI:IF
INTR:IF8259
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(IFCPUIF
IF0INTR
()CPU
(8259)I/O(8255)
)
CPU
(TFOF)(INT n)
0
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(
)().
4
(IP)()
();
(CS)()
()
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8086/8088P1205.2
8086/8088256
()
256256*41024
00000H~003FFH
5(04)
27(531)0000:0014H
0000:007FH108
224(32255)
0000:0080H~0000:03FFH
21HMS-Dos)
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4
CPUN4
4N(4
)
IPIP
(4N,4N+1),CS
CS
(4N+2,4N+3)N
[N
(:NMIINTR)
]
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13
34
000CH
00000H
00001H
0000CH
(0000:000CH)
00(IPL)
0A(IPH)
00(CSL)
1E00 0 H
+ 0A0 0 H
1E(CSH)
1EA00H
(1E00:0A00H)
FFFFFH
....
1EA0 0 H
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2.20H
0000:0080H4
(0080H)=10H
(0081H)=20H
(0082H)=30H
(0083H)=40H
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3.23(17H)
:2340:7890H
17H0
0000:005CH(17H4=5CH)
(005CH)=
(005DH)=
(005EH)=
(005FH)=
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2:
0001 0111 B
0101 1100 B
5
C H
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8086/8088
(1)
(1)
INT
n,INT0?
(2)
INTR?
N
FR>
(3)
TF>
(4)
0>TFIF
(5)
CSIP>
NMI?
IF=1?
(4N,4N+1)>
IP
(4N+2,4N+3)>
CS
TF=1?
N
NMI
N
Y
=1?
N
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IRET
(CS,IP,FR)
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8086/8088
*8086(Priority)
(1)~(5)CPU(
)
(INT n
INT0)NMI
INTR
INTR
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,INTn,INT0
NMI
INTR
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IF=1
TF=1
DIVIDIV
00H
2010H:4030H
.
.
.
.
5040H:7060H
IRET
CSIPFR
FR->,TF->
IF,TF
CS,IP->
(0,1)->IP
(2,3)->CS
01H
FR->,TF->
IF,TF
CS,IP->
(4,5)->IP
(6,7)->CS
,
IRET,CS,IP,FR
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60
70
40
50
(FR)
30
40
10
20
(FR)
IP
CS
(TF=1)
INTR
4030H:2080HINTR
9080H:3020H.
TF=0
IP
CS
TF=1
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()
(0)0
DIV()IDIV()
00
CPU
OF1
INTO4
CPUOF=0
INTOINTO
INTO
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.
.
ADD AX,BX; OF=1

INTO
IRET
()(INT n)
CPU
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INT3INT
CPU
1
TF=1
..
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()
CPU(
)
(
INTOINT n)
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http://www.csai.cn

()
STI();
PUSH AX
PUSH BX
PUSH CX
POP CX
IRET
POP BX
POP AX
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**
1->TF
10TF
PUSHF;
FR
POP AX;
FRAX
0->TF
PUSHF
POP AX
OR AX,0100H; AXTF1
AND AX,
PUSH AX;
AX
PUSH AX;
POPF
FR(TF=1)
POPF
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8259A
(8259A Programmable Interrupt Controller-PIC)
Intel 8259A80x86
8259A8
649
8259A
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8259A
CPU
8259A
INTR
INT
INTA
INTA
CPU
IR0
.
.
.
INTR
8259A
INTA
IR7
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IR.0
.
.
.
IR. 7
8259A
.
.
.
IR0
IR7
8259A
.
.
.
IR0
IR7
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8259A
8259A
2828pin
DIP),DIP:Dual-In-Line Package ,5.7
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8259A
1
2
WR
RD
3
D7
4
D6
5
D5
6
7 8259A
D4
8
D3
D2
9
D1
10
D0
11
CAS0
12
CAS1
13
GND
14
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CS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A0
INTA
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0
INT
SP/EN
CAS2
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8259A
Chip Select)
CS
CPU
8259A
WR CPU
8259ACPU
WR
CS
WR
RD CPU
8259A
RD
RD
CS
CPU
CS
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8259A
D7~ D0 :
D7~ D0
IR7~IR0 :
INTCPU
INTA
CPU
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8259A
A08259A
CAS2~ CAS0:CASCADELINES3
SP/
EN :/
8259A1
SP/ EN
8259A0P1305.9
SP/ EN
8286
*8259A
8259A
ICW4
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8259A
CPU
CAS0
CAS1
CAS2
SP/EN
AD7~AD0
D7~D0
ISR
PR
IRR
RD
.
.
.
INTA
INTR
WR
ICW1
A0
ICW2
OCW2
CS
ICW3
OCW3
INTA
ICW4
INT
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OCW1 (IMR)
IR0
.
.
.
IR7
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8259A
IRRInterrupt Request Register

PR---Priority Resolver
ISR---In-Service Register
IMR---Interrupt Mask Register
ICWs---Initialization Command Words
OCWs---Operation Command Words
7CPU
ICW1 ~ICW4---
OCW1~OCW3(
).
The OCWs can be written into the 8259A anytime after
initialization.(P6137
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8259A
7:
A0
0
ICW4:D4=1
ICW2
ICW3
ICW4
1
1
ICW1
OCW1:ICW1
OCW2
D4=0
OCW3
D4
D3
ICW1
OCW2
OCW3
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(A0)
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8259A
8259A
IRR8
IR0IR7
ISR
PR
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8259A
IR0IR7->IRR
1->IMR(=1
=0)->PR->PR
->
CPU
CPUIF=1CPU
INTA (
P1225.4)
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8259A
():
8259A
IRRIR0IR7
IRR(
)
ISR1
IRR
8259A
(ICW2)D7D0
ICW4AEOI1 INTA
ISR INTA 1()
(EOI)
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8259A
1 .
(1) (FULLY NESTED MODE)

IRi
IR0()>IR7().
This mode is entered after initialization unless another mode
is programmed.
ISRISn1
8259A
()CPU
(EOI)1
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8259A
(2) (SPECIAL FULLY NESTED MODE

SFNM)
8259
ICW4SFNM(p132)
8259()
8259()
IR0
IR1
IR0
IR1
CPU
IR7
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IR7
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8259A
(3) (AUTOMATIC ROTATION)
()
IR0->IR7
IR0IR0
IR0
IR1IR2IR3IR4 IR5 IR6 IR7IR0
IR7
IR4IR4
IR6
__________________________________
IR5
OCW2( p132 P133)
IR4
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IR 1
IR 2
IR 3
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8259A
(4)(SPECIFIC
ROTATION)
IR4IR5
(OCW2:110)
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8259A
2. ()
(IMR)1
OCW1IMR1
*(SPECIAL MASK MODE)
P129
OCW3(ESMM=1,SMM=1)
OCW1(IMR1)
OCW1(IMR0)
OCW3(ESMM=1SMM=0)
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8259A
3. (END OF INTERRUPTEOI)
(1)(AUTOMATICAEOI)
INTA ISR
AEOI
ISR08259A
IF1
()
CPU
AEOI
ICW4AEOI(AEOI=1)
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8259A
(2)()
8259A
(OCW2:EOI=1,SL=0,R=0)
MOV AL,20H; OCW2=20H
OUT 20H,AL; =20H()
ISR1
0
IR0
1 1 0 1
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IR7
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8259A
(3)(SPECIFIC EOISEOI)
(
)ISR
()
EOI
SEOI
OCW2:EOI=1,SL=1,R=0,L2L0.
L2L0ISR
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8259A
4.
IRi
IRi
ICW1LTIM
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8259A
5.
(ICW4BUF=1)
8259A(8286)
8259A SP / EN ( EN )
ICW4M/S()8259A
(ICW4BUF=0)
8259A
8259A SP / EN (SP )
SP / EN 8259A
ICW4BUF0M/S
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8259A
(Polling)
8259ACPU
CPUIF=0(CPU
)
CPU
8259A(poll command)
OCW3:
0 0 0 0 1 1 0 0
P
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8259A
(IN)
A0
D7
IR
D0
W2 W1 W0
1:
8259AP=1 RD
ISR1INTA
CPU
AL
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8259A
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8259A
1 .
ICW1~ICW4.(
P131)
ICW1
ICW2
NO(SNGL=1)
8259A
YES(SNGL=0)
ICW3
NO(IC4 =0)
ICW4?
YES(IC4=1)
ICW4
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8259A
8259A(P134)
2. 8259AOCW1~OCW3(P132)
3.8259A
()
IRR
OCW3(RR=1,RIS=0)
(IN AL,20H)
ISR:
P=1OCW3
(IN AL,20H)
OCW3(RR=1,RIS=1)
(IN AL,20H)
IMR
(IN AL,21H)
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1
IN AL,21H ; IMR
AND AL,7FH ; IR7
OUT 21H,AL
2
IN AL,21H ; IMR
OR AL,80H ; IR7
OUT 21H,AL
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8259A
(1)
ALDS:DX
AH=25H
AL=
DS:DX=
INT 21H
(2)
AL
ES:BX
AH=35H
AL=
ES:BX=
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INT 21H
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8259A
DOS
.
MOV AL,N;
MOV AH,35H;
INT 21H;
PUSH ES;
PUSH BX;
PUSH DS;
MOV AX,SEG INTHAND;
MOV DS,AX;
MOV DX, Offset INTHAND;
MOV AL, N;
MOV AH, 25H;
INT 21H;
POP DS;
type N Interrupt
get Interrupt vector
save the old base and
offset of interrupt N
base of INTHAND in DS
offset in DX
Set Interrupt Vector
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8259A
POP DX;
POP DS;
MOV AL,N;
MOV AH,25H;
INT 21H;
RET ;
INTHAND:
.
IRET
restore the old offset

and base of interrupt
set interrupt vector
return
Interrupt Processing Routine
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1.
(TF=1)INTR
4030H:2080HINTR
9080H:3020H.
2.
P135 (7)
3.
P135 (8)
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CPU
CPU
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CPU
CPU

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CDROM
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* CDROMCompact Disk
Read Only Memory
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RAM
ROM
SAMSequential
Access
Memory
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DAMDirect
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2
1p
q:
*q
Access Time
Memory Cycle
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>
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61
RAMVolatile
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ROM
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RAM
1 RAMSRAMStatic RAM
1 RAM
Cells
6.2
2 RAM 6 1 1 6
2K8
CMOS
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RAM
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SRAMP138
2 RAMDRAMDynamic
RAM
1DRAMDRAM
2DRAM
3DRAM6.11
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ROM
1 ROM
2 PROMProgrammable ROM
3 EPROMErusable PROM
1 EPROM
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2 EPROM2764A
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( )
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3.5 Memory System Design

Using ICs
Memory system designers use commercially

available RAM chips to design larger memory
systems:the major steps in such memory
designs are the following:
1Based on speed and cost
parameters,determining the types of
memory ICs(static or dynamic) to be used in
the design.
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l
l bl
f h
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4Arranging the above N ICs in a P*Q

matrix,where Q=(number of bits per word in
memory system)/(number of bits per word in
the ICs) and P=N/Q.
5Designing the decoding circuitry to selcet
a unique word corresponding to each address.
We have not addressed the issue of

memory control in this design procedure.The
control unit of the computer system,of which
the memory is a part,should produce control
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signals to strobe the address into the
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The following example illustrates the

design.
4 K 8
Example 3.4
1
K
4
Design a 4K*8 memory .using Intel 2114
RAM chips
12
1Number
of chips needed
2
= Total memory capacity/chip
capacity
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=8
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4The 2114 has 10 address lines.The least

significant 10 bits of the memory system MAR
are connected to the 10 address lines of each
2114.A 2-to-4 decoder is used to decode the
most significant two bits of the MAR,to select
one of the four rows of 2114 chips through
the CS signal on each 2114 chips .
5I/O lines of chips in each row are
connected to the MBR .Note that these I/O
lines are configured as tristate .The WE lines
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of all the 2114 chips are tied together to form
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The memory system is shown in

Figure 3.25.Note that the number of bits in
the memory word can be increased in
multiples of 4 simply by including additional
columns of chips.If the number of words
needs to be extended beyond 4K , additional
decoding circuitry will be needed.
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Of Reference)
[Cache]
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2 .[
CPUCache]
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CPUCPU
CPUIBM 904CPU
12us12us
CPU
CPU
ns33MHz80386
60ns
nsDRAM
100nsCPU
DRAM
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RAMSRAM25ns
SRAMDRAM
CPUCPU
-------
CacheSRAMDRAM
SRAMDRAM------SRAMDRAM
32
80386CacheCPU80486Pentium
CPUCache
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3. Cache
CacheSRAMDRAMCache
Cache
(SRAM)
Main
Memory
(DRAM)
CPU
Cache
Controller
Cache Memory System
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Cache
Loop
Cache
80386DX
Loop
Cache
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CPUCache
CacheCache
CPUCache
Cache hitCPU
CacheCache missCache
CacheCacheCache
hit rateCacheCache
Cache
80386Cache
95%[IBM 36099%]
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100%
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4. Cache
Cache---line
Cache32
4
CPUCacheCache
Cache
Cache
CacheCache
direct mapped
two way set associative
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10.42
Cache
64K
64K0n
X(0)(n)
CacheX
64K
Cache
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CACHE MEMORY
X (n )
64 KB
Of
Memory
X (1 )
X
X (0 )
Page n
Page 2
Page 1
Page 0
Figure
64 KB
Of
Memory
10 .42 Organization of a direct
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Main
Memory
Pages
-mapped memory subsystem
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10.43
64KCache
32KCache
BANK A BANK B
CacheBANK
BANK 32K
BANK A BANK B
X(2)X(A)
X(B)
Cache
Cache
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32KB
Of
Memory
Bank A
Bank B
32KB
Of
Memory
X(2)
X(1)
X(A)
X(B)
X(0)
Page n
Page 2
Page 1
Cache Memory
Page 0
Main Memory Pages
Figure 10.43 Organization of a two -way

set associative memory subsystem
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5. Cache82385
8238580386
132Cache
Cache
Cache
Cache
Cache
82385CacheSRAM
32KB Cache4GB4
2W / D
82385
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http://www.csai.cn
(1).
82385Cache
82385Cache12.11
CacheCache80386 4GB
4GB32KB8K-----
4GB32KB=128K=217
0217-117
Cache
Cache1024(set)8
Cache
Cache261024
Cache
Cache17TAG1
832K
17
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Cache
8
01
8
8038632232
4000M
8238580386A312
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80386328238510
1024
A31A151
1Cache
80386
80386Cache
82385
8038617Cache
10
1
A31A15
117
0
1
http://www.csai.cn
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32KB
8K
17
32
217-1
.
.
.
217-2
1023
1
0
82385cache
SRAM
32KB
(cache)
12.11 Cache (82385)

http://www.csai.cn
http://www.csai.cn
(2).
82385Cache
82385CacheCache
12.12
4GBCache32KBAB16KB
328
512
[]16KB4GB256K
82385Cache5122
2718256K1
8
Cache
AB
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82385AB
LRULeast Recently Used
82385
AB
82385Cache
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A13A55122
82385A31A14
82385Cache
ACache
LRUBLRU
A
80386
CacheCacheCache
ACacheA
LRUBBB
CacheLRUA
0
Cache
SRAMCache
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18
18
A
32
B
32
16KB
LRU
218-1
.
.
.
511
218-2
2
1
Cache
32KBCache
SRAM32KB
4
(DRAM)
12.12 Cache
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6 .Cache
CacheCache
DMA
DMACache
Cache
Cache
Cache
Cache
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3
(1)Write through
CPU
CacheCache
Cache
Cache
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(2)buffered Write through

Cache
Cache
CPU
CPU
http://www.csai.cn
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(3)(write back)
Cache
CPUCache
1
CacheCache
0Cache
CacheCache
Cache
Cache
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(
Cache)
(1).
Cache
Cache
CacheCache
Cache82385
Cache
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http://www.csai.cn
(2).
Cache
Cache
Cache
CacheCache
Cache
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http://www.csai.cn
(3)
CacheCPU
Cache
Cache
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(4) Cache
Cache
Cache
CacheCache
Cache
Cache
Cache
Cache
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1.Cache
00005FFH(26,
Cache
Cache
2. 82385CPU
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1.16K1RAM
256K64K
2. 6116 RAM 4k*16

74LS138
CPU (8086)
8086 8282
8286
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I/O
(I/O)
I/O
1
2
A/D,D/A
3
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CPUI/O
1.
1
2
2.
Ready
Busy
CPU
3.
CPU
A/D
D/A
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I/O(P1627.1)
I/OCPU
I/O(I/O PORT)
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I/O
1. I/OMemory Mapped I/O

I/O
XXXXH
XXXXH
I/O
:ADD AL, [2000H]
I/O
I/O
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I/O
0
2. I/O
I/O Mapped I/O
I/O
XXXXH
INOUT
I/O
CPU
MI/O?
CPU
M/IO80x86
P164
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0
I/O
XXXXH
http://www.csai.cn
I/O
IBM PC, P165 717-2
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I/O
CPUIN AL,
XXH OUT XXH, AL,
Chip Select
CSI/O
I/O
3874LS138
I/O
A5
A6
A7
A
B
C
A8
A9
G2B
G2A
AEN
G1
Y0
Y7
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I/O
1.
2.. P167
1.
2.
aCPUCPU
bCPU
c
DMA
DMADMAC
DMAC/CPU
CPUP1697.5
DMA
I/O
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I/O
I/O
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DMA
DMA
P170 16
DMA
DMACI/O
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DMA
1.

CPU
2.

CPU
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3.
DMAC
I/ODMA
DMA
CPUDMA
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DMA
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1.DMA
P173 7.8
19
6DMACMEMR7DMACIOW
2. DMA
19 P174
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DMA8237
P6101
8237 P175 7.97-3
8237Pin Configration
* 204P177
8237
1.
2.
3.
4.
Single Transfer Mode

Block Transfer Mode
Demand Transfer Mode
Cascade Mode
8237
*
8237
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DMAI/O
DMA
DMA
DMA
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DMA
CPU
I/O
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Intel
8237/8237-2
HIGH PERFORMANCE
PROGRAMMABLE DMA CONTROLLER
Enable/Disable Control of Individual DMA Request

Four Independent DMA Channels
Independent Autoinitialization of all Channels
Memory-to- Memory Transfers
Memory Block Initialization
Address Increment or Decrement
High Performance: Transfers up to 1.6M Bytes/Second with 5 MHz
8237-2
Directly Expandable to any Number of Channels \
End of Process Input for Terminating Transfers
Software DMA Requests
Independent Polarity Control for DREQ and DACK Signals
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P189 (26)
8237 0 -----3
8000H------------8000H:0H
3
82H .
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1.
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2.
1.
Simplex)
Data flow
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Half Duplex
Data flow
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B
/
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Full Duplex
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2.
bpsbit per
second

11

10
1

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4090180270
3/
900
101
001
1800
00
110
010
000
100
011
111
2700
5075110150
3006001200
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3.
CLK()
RxC 11632
RxD
TxC
11632
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TxD
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Modulator Demodulator
Modem
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0
(a)
(b)
(c)
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4.
f = 19.2 kHz16
1200 bps

12001619200
F1Mhz8253
8253

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8251
1MHz
CLK
8253 OUT
19.2KHz
116
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5.
Asynchronous
15
1 1
n+1
1/0
5-8
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111
1/0
2
1
1
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2Synchronous
15
P194P195
SYN1)
SYN2)
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DATA)
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*
SDLC/HDLC
2048
2048/20484897%
3
SDLC/HDLC1.0N/(N+48)
N
01111110
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CRC
8
CRC
8
01111110
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6.
Parity Check
CRCCyclic Redundancy Check
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EIA RS232C/CCITT V.24
EIA RS232C1969DTE
DCE
198711RS
232D
DTEData Terminal Equipment
DCEData Communication Equipment
Data Circuitterminating Equipment
PSTNPublic Switched Telephone Network
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1. 8.6
DB25 ISO 2113

EIA RS232DISO 2110
EIAfemaleDCE
maleDTE
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2. 81
252222
RS-232C82
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3.
5V15V0
5V15V1
RS-232CTTL8.8
TTLRS-232CMC1488
RS-232CTTLMC1489
15V
5V
5V
15V
15V
2V
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3V
3V
15V
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4.
EIA RS232-CCCITT V.24ISO/OSI
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RS-232C
2.
3.
4.
Null Modem
DB-9
1.
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DB-9 and DB-25 RS-232
Pin Designations
Signal
DCD
RxD
TxD
DTR
GND
DSR
RTS
CTS
RI
DB-9
1
2
3
4
5
6
7
8
9
DB-25
8
3
2
20
7
6
4
5
22
The 9- and 25-Pin Connectors used by the PCs serial ports are male
connectors; the printer and video cards use female connectors.
ModemP81
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RS-449RS-422ARS-423A
EIA RS-449937
1977.11
EIA RS-423A1978.9
300k bps
10m300k bps1000m3k bps
EIA RS-422A1978.9
10M bps
10m10M bps1000m100k bps
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CCITT
101
103
108
20
22
3-5 V.24/RS-232C
a)
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Modem
Modem
109
125
102
107
Modem
106
105
104
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31 CCITTV.24/RS232C
SG
TXD
CCITTV
101
102
103
EIA
AA
AB
BA
1
7
2
Modem
RXD
104
BB
Modem
RTS
105
CA
Modem
CTS
106
CB
Modem
DSR
107
CC
ModemModem
Modem
DTR
108
CD
20
Modem
CD
109
CF
Modem
Modem
RI
125
CE
22
ModemModem
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1EIA
A
B
C
D
S
2
SGSignal Ground
TXDTransmit DataDTRData Terminal Ready
RXDReceive DataDSRData Set Ready
RTSRequest To SendCDCarrier Detect
CTSClear To SendRIRing Indicate
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8.10
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8251A
USART /
Universal
Synchronous Asynchronous
Receiver/Transmitter
UARTUniversal
Asynchronous
Receiver
Transmitter
USRTUniversal Synchronous Receiver Transmitter
Intel 8251Zilog SIOMotorola ACIA
USARTAPPENDIX B
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intel
8251A
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PROGRAMMABLE COMMUNICATION INTERFACE
Synchronous and Asynchronous Operation
Synchronous 5-8 Bit Characters Internal or External Character
Synchronization Automatic Sync Insertion
Asynchronous 5-8 Bit Characters Clock Rate-1,16 or 64
Times Baud Rate Break Character Generation1,1.5, or 2
Stop Bits False Start Bit Detection Automatic Break Detect
and Handling
Synchronous Baud Rate DC to 64K Baud
Asynchronous Baud Rate DC to 19.2K Baud
Full Duplex, double Buffered, Transmitter and Receiver
Error Detection Parity, Overrun and Framing
Fully Compatible with 8080/8085 CPU
28-Pin DIP Package
All Inputs and Outputs are TTL Compatible
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Single + 5V Supply
Single TTL Clock
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83 8251A/
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18251A
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2 http://www.csai.cn
8251A
CPU8251A
8.17
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CPU8251A
IN8251A
8251A
8.18
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8251A
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8.22
Handshaking
8255
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8255A
ABC
C
AB
402VccGND
24
RESETCSWRRDD7~D0A1A0
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8.24P222
A APA7~PA0
C4PC7PC4
B C4PC3PC0
BPB7PB0
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8255A
1 8.25
D71
D6D5D4D3A
D2D1D0B
P224
2 C108.26
D70
D6D5D4
D3D2D1
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D0
1 1 0 0
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8255A
10
AC4B16
21

118.27
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C
A
PC4STBA A
PC5IBFA A
PC3INTRA A
B
PC2STBB B
PC1IBFB B
PC0INTRB B
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A1P226
*B 1A
1828
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21829
P226
830
*32A
2
*8255A
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P23632
8255AOBO
CO
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A01HB
04H,
40
PC0=1?
Yes
A02H
A04H
B01H
20
B02H,
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P235
P235
P235
P236
(18)
(20)
(31)
(32)
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/
2003.11
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1. CPU
MOV CX,H
HERE:LOOP HERE

CPU
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2.
td
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3./
()
Zilog
Z80-CTC
Intel
8253(8254)
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http://www.csai.cn
/8253
.8253
(1)16
(2)
(3)2MHZ
(4)
(5)TTL
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8253
P238 9.1
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(8)
Vcc
RD
GATE0
WR
WR
OUT0
IO/M
CS
D0-D7
0
(CR)
GND
RD
CLK0
1
(OL)
CLK1
GATE1
OUT1
A1
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CLK2
(CE)
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1. (8),
(CR)CPU
2. (OL)CPU.
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. 8253
9.3
CLK
OUT
GATE
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.8253
1.0
WR
CW
N=4
N+1
CLK
GATE()
OUT
CR CE
2 1 0
0
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(
).
OUT(WR)
N+1CLK
GATE,
GATE(9.5)
(9.6)
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2.1
WR
CW
N=2
CLK
GATE
OUT
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2(9.8)
3(9.9)
4(9.10)
4:
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8253
P245~P246 (1)~(5)
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.8253
1.
2.
9.1
D5,D4
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3.
9.12
D7
D6
D5
D4
D3 D2
D1 D0
M1
BCD
SC1 SC0 RL1 RL0 M2
M0
65536
BCD 10000
2MHZ,2BCD
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4.
1.
2.
P247
http://www.csai.cn
http://www.csai.cn
. 8253
1.
2.(P249)
http://www.csai.cn
http://www.csai.cn
8253
1. 8253(
).
2. 8253A/D
.
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P255
(6)
----------2.5MHz, 11KHz
,2----------------
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(Chip Bus,C-BUS):
(Internal Bus,I-BUS):
(External Bus,E-BUS):
(Modem)
EIA-RS232C,IEEE488,USB
10.1
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ISOIEEE
S-100
PC
IEEEIEEE696
S-100PC
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S-100
9
;
100
(*)
DMA
;
8V18V
8V18V
5V
8V5V
IEEE696
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Intel MultiBus(IEEE-796);
Zilog Z-Bus(122);
IBM 62(IBM-PC/XT);
IBM PC/AT;
ISA(Industrial standard Architecture),XT
ATISA
EISA(Extended ISA);
PCI(Peripheral Component Interconnect).
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8289
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P258
I
II
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http://www.csai.cn
II
1
2
2
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P259
N2N
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MultiBus(
1.
2.
3.
4.
5.
IntelIEEE
IEEE-796
816
32MultiBusII
//
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MultiBus
MultiBus
P1P2P1
86P260
P1
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P2
http://www.csai.cn
MultiBus
P13.96mm;P2
2.54mm.
P186101
8
(1,2,11,12,75,76,8,86),8+5V
(3,4,5,6,81,82,83,84)
P260102
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http://www.csai.cn
1.
16
P120( ADR 0 -- ADR13 )-IEEE

P24( ADR14--ADR17 )-Intel
I/O
8
16( ADR -- ADR )

8( ADR -- ADR )I/O
0
16
20( ADR -- ADR )

12( ADR -- ADR )I/O
B
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INH 1 INH 2
:[inhibit]
INH 1 RAMRAM
INH 2 ROMROM
RAMROMROM
()
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ROM()
ROM
ROM
ROM()
RAM
RAM()
INH1(RAM)INH2(ROM)
0
0
1
0
1
0
ROM
ROM
RAM
()
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2.
DATF
DAT7
DAT0
DAT0
16
8
XACK
XACK
READY
BHEN
8 DATF DAT8
MRDC MWTC
I/O IORC I/O IOWC
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3.
MultiBus8 INT0
INT7 1 INTA
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4.
BCLK
BPRO
BUSY
BREQ
BPRN
CBRQ
5
*MultiBus
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ISAEISA
ISA
IBM PC/XT(8)IBM PC/AT

(16)ISA()
10.6
D18
D1
B31 ..
C18
C1
A31
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B1
A1
()
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ISA
62(XT8
)XT
36
623616
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http://www.csai.cn
ISA62(IBM PC/XT)
8SD0SD7
20SA0SA19
6IRQ2IRQ7
6DMA(DRQ1DRQ3DACK1DACK3)
/
RESET DRV
SYSCLK
OSC
5(+5V,+5V,-5V,+12V,-12V)
3(GND)
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EISA (Extended ISA),1998
ISA
(Burst Transfer)
1632
2432
P266P267
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http://www.csai.cn
VESA(VL-BUS)PCI
(GUI)
(bottle-neck)
http://www.csai.cn
http://www.csai.cn
30640*48024
28M/s,100Mbps
12.5M/s
ISA,EISA
CPU
I/O
()I/O
()
10.8
http://www.csai.cn
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VESAVL-BUS
3264
264MB/S
i486
Pentium
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PCI
PCI(Peripheral Component Interconnect)

Intel
PCI
CPU
PCI
PCI
ISAEISA
http://www.csai.cn
http://www.csai.cn
PCI
PCI():PCI
PCI
ISAEISA
:,
.
PCI
http://www.csai.cn

计算机体系结构讲义

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http://www.csai.

EDVACElectronic Discrete Variable Automatic Computer

Data Bus --DB--

*SPEC(Standard Performance Evaluation Corporation)

1992iCOMP Index 1.0

iCOMP Index 1.02.0

1-6 iCOMP 1.0

64-bit data bus

32-bit address bus

Internal view of a Pentium(simplified)

BHE/S78/BUS High Enable/Status

NMI(Non-Maskable Interrupt request):

ALE(Address latch Enable):

B0.4 MIPS X 12/8=0.6 MIPS

(1) MOV AX,32C5H

MOV AL, 80H ;

ADD AL, 20H ;

8 AH, AL, BH,

ES: MOV AX , [3000H] ;

( MOV [2000H] , [3000H] )

MOV AX, [SI+3000H]

MOV BL, [2035];

IN AL, PORT ;:AL

MOV AL, OTRCNBITS;

LEA (Load Effective Address)

LDS (Load pointer into register and DS)

LES (Load pointer into register and ES)

LEA REG , SRC;

(3) LES REG,SRC

SUB DST, SRC

CMP OPR1,OPR2 OPR1OPR2

MOV AL, BCD1;

ADD AL, BCD2;

ROL OPR ,CNT

ROR OPR , CNT

RCL OPR , CNT

RCR OPR , CNT

MOVSB (DI) (SI),SI SI+1,DI

: JMP SHORT OPR (

: JMP WORD PTR OPR(

LOOPZ OPR/LOOPE OPR ZF=1

all FAR PTR Display

Call DWORD PTR [BX+SI]

(4) MOV [BX+DI+10H], AH ;

Handwritten source program

EDIT Editor program

DEBUG debug program

ROM BIOS(Basic Input Output System)

[dummy Parameter List]

Macro-name [actual parameter list](

STACK SEGMENT STACK

DMA(Direct Memory Access)

ADD AX,BX; OF=1

IRRInterrupt Request Register

(1) (FULLY NESTED MODE)

(2) (SPECIAL FULLY NESTED MODE

(3) (AUTOMATIC ROTATION)

*(SPECIAL MASK MODE)

restore the old offset

Interrupt Processing Routine

3.5 Memory System Design

Memory system designers use commercially

4Arranging the above N ICs in a P*Q

We have not addressed the issue of