DEPT OF ECE,MLMCE 1

CHAPTER 1
INTRODUCTION
Cryptography provides the mechanisms necessary to provide accountability,
accuracy and confidentiality in inherently public communication mediums such as the
Internet. The widespread adoption of the Internet as a trusted medium for
communication and commerce has made cryptography an essential component of
modern information systems. The growth of innovation for these devices can be seen
in todays mobile phones, portable devices and computer/network security in
industrial control system . In order to reach the demand of low-power devices with
high-security features, researchers generally focus around the cryptographic algorithm
actually implemented in the hardware itself to encrypt and decrypt information. Thus,
securing cryptographic devices against various side channel attacks (SCAs) has
become a very attractive research topic in recent years along with the developments of
information technologies. Synchronous logic with clocked structures has dominated
the digital design over the past decades. As the decrease of feature sizes and the
increase of the operating frequency of integrated circuits (IC), clock-related issues
become more serious, such as clock skews, increased power at the clock edges, extra
area, and layout complexity for clock distribution networks, and glitches. These
motivate the research of asynchronous (i.e., clockless) logic design which has benefits
of eliminating all the clock-related.

Advanced Encryption Standard (AES) was announced with the intention of being
a faster and more secure encryption algorithm over others since its algorithm is
comprised of multiple processes used to encrypt information with supports of up to
256-bit key and block sizes, making an exhaustive search impossible to check all
2256 possibilities. Usually, the hardware AES implementation has higher reliability
than software since it is difficult to be read or modified by attackers and less prone to
reverse engineering. Unfortunately, AES is still vulnerable to SCAs [2]. Our proposed
Null-Conventional-Logic based (NCL) Substitution Box (S-Box) design essentially
matches all the important security properties: asynchronous, dualrail encoding, and an
intermediate state (i.e., NULL). Unlike other asynchronous designs, NCL adheres to
the monotonic transitions between DATA (i.e., data representation) and NULL (i.e.,
control representation), which utilizes dual-rail and quadrail signaling methods to
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achieve the delay insensitivity.This would significantly reduces the design
complexity. With the absence of a clock, the NCL system is proved to reduce the
power consumption, noise, and electromagnetic interference.

1.1 OBJECTIVE
The main objective of the proposed work :
To study about the Advanced Encryption Standard Substitution Box
(AES S BOX) and the operations involved.
To study about the null convention logic NCL.
To study about the side channel attack.
Implementation of NCL logic in S Box.
Comparison of AES S BOX and NCL S BOX.





















DEPT OF ECE,MLMCE 3

CHAPTER 2
LITERATURE SURVEY
Many researches has been carried out for securing the electronic data from
attackers. But most of them are vulnerable to side channel attack. Thus, securing
cryptographic devices against various side channel attacks (SCAs) has become a very
attractive research topic in recent years along with the developments of information
technologies.
On 2nd January 1997, the National Institute of Standards and Technology
(NIST) invited proposals for new algorithms for the new Advanced Encryption
Standard (AES). The goal was to replace the older Data Encryption Standard (DES)
which was introduced in November 1976 when DES was no longer secure. After
going through 2 rounds of evaluation, Rijndael was selected and named the Advanced
Encryption Standard algorithm on 26
th
November 2001.
The AES algorithm[1] has a fixed block size of 128 bits and a key length of
128, 192 or 256 bits. It generates its key from an input key using the Key Expansion
function. The AES operates on a 4x4 array of bytes which is called a state. The state
undergoes 4 transformations which are namely the AddRoundKey, SubByte,
ShiftRow and MixColumn transformation.The AddRoundKey transformation
involves a bitwise XOR operation between the state array and the resulting Round
Key that is output from the Key Expansion function. SubByte transformation is a
highly non-linear byte substitution where each byte in the state array is replaced with
another from a lookup table called an S-Box. ShiftRow transformation is done by
cyclically shifting the rows in the array with different offsets. Finally, MixColumn
transformation is a column mixing operation, where the bytes in the new column are a
function of the 4 bytes of a column in the state array. Of all the transformation above,
the SubByte transformation is the most computationally heavy.Many researches has
been carried for securing cryptographic devices against various side channel attacks
(SCAs). Unfortunately, AES is still vulnerable to SCAs.
Side-channel attacks[2] are typically passive: an adversary usually just
observes the target system under normal operation. What the attacks exploit is the
presence of a sidechannel, an unintentional source of information about the internal
operation of the target system. Power analysis, the observation of the power
consumption of a target system, has emerged as one of the the most effective,
DEPT OF ECE,MLMCE 4

practical, and consequently well-studied type of side-channel attack. Other types of
side-channels have been successfully exploited, as well; examples include
electromagnetic emission analysis and timing analysis.
Karl Fant and Scott Brandt in 1994 proposed theNull Convention Logic
(NCL) and it is further developed by Dr. Scott Smiths research group . NCL initially
aimed at designing Application Specific Integrated Circuit (ASIC) and Very-large-
scale Integration (VLSI) circuits with lower power, lower noise, and lower
electromagnetic interference (EMI).
Jun wu and yong-bin kim proposed the implementation of NCL logic in
asynchronous s box to resist the side channel attacks. This design demonstrates that
NCL has the advantage of securing cryptographic devices against various power
analysis attacks, including Simple Power Analysis (SPA), Differential Power
Analysis (DPA), and Cor- relation Power Analysis (CPA). Designing an NCL circuit
is less complex than designing the traditional asyn- chronous circuit due to the
absence of global clock.



















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CHAPTER 3
PROJECT OVERVIEW
Study of AES algorithm
o Operations involved in S BOX
o Implementation of AES algorithm in S BOX
o Simulation Of AES S BOX
Study of side channel attack
Study of Null Convention Logic(NCL)
o Implementation of Null Convention Logic in S box
o Comparison of AES S BOX and NCL S box
o Implementation on SPARTEN 3 FPGA






















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CHAPTER 4
ADVANCED ENCRYPTION STANDARD
The AES algorithm consists of a number of rounds that are dependent on the key
size[6]. For both cipher and inverse cipher of the AES algorithm, each round consists of linear
operation (i.e., ADDROUNDKEY, SHIFTROWS, and MIXCOLUMNS steps) and nonlinear
operation (i.e., SUBBYTES step). SUBBYTES step is the first step of AES round. Each byte
in the array is updated by an 8-bit S-Box, which is derived from the multiplicative inverse
over GF(28). The AES S-Box is constructed by combining the inverse function with an
invertible affine transformation in order to avoid attacks based on mathematics. The S-Box is
one the of most critical components in the implementation of AES hardware. It consumes the
majority of power and is also the most vulnerable component to SCAs.

Block Diagram of AES SBOX


Fig 1 (a) Combinational S-Box architecture with encryption and decryption datapaths. (b)
Block diagram of multiplicativ inversion over the GF(28) component, where MM is modular
multiplication and XOR is EXCLUSIVE OR operation
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4.1 Affine Transformation And Inverse Affine Transformation



Table 1: Affine Transformation And Inverse Affine Transformation

The affine transformation and inverse affine transformation components follow a
series of Boolean equations as given in table 1. Both transformations require many
XOR gates. The multiplicative inversion in GF(28) follows the procedure shown in
Fig. 1(b). First, map operation converts the 8-bit input into elements of GF(24) (i.e.,
ah and al). Second, calculate the square of ah and al. It should be noticed that
multiplication in GF(24) is done by multiplying the polynomial ah(x)ah(x) followed
by a modular reduction. Third, a series of multiplication and XOR operations were
implemented to extend the field GF(24) to the field GF(28). The main loop of the
AES encryption algorithm performs four different operations on the State matrix,
called SubBytes, ShiftRows, MixColumns, and AddRoundKey in the specification.

The SubBytes operation: substitution operation that takes each byte in the
State matrix and substitutes a new byte determined by the Sbox table
Shift row operation: permutation operation that rotates bytes in the State
matrix to the left.
Mix columns operation: It replaces each byte with the result of mathematical
field additions and multiplications of values in the byte's column
Add round key operation: Each byte of the state is combined with the round
key using bitwise xor.





DEPT OF ECE,MLMCE 8

4.2 Null Convention Logic

4.2.1 Overview Of NCL

NCL is a delay-insensitive (DI ) asynchronous (i.e. clockless) paradigm, which
means that NCL circuits will operate correctly regardless of when circuit inputs
become available; therefore NCL circuits are said to be correct by- construction[8].
(i.e. no timing analysis is necessary for correct operation). NCL circuits utilize dual-
rail or quad-rail logic to achieve delay-insensitivity. A dual-rail signal, D, consists of
two wires, D0 and D1, which may assume any value from the set {DATA0, DATA1,
NULL}. The DATA0 state (D0 = 1, D1 = 0) corresponds to a Boolean logic 0, the
DATA1 state (D0 = 0, D1 = 1) corresponds to a Boolean logic 1, and the NULL state
(D0 = 0, D1 = 0) corresponds to the empty set meaning that the value of D is not yet
available. The two rails are mutually exclusive, such that both rails can never be
asserted simultaneously; this state is defined as an illegal state. In this project i had
used the dual rail logic.
NCL circuits are comprised of 27 fundamental gates, as shown in Table 2,
which constitute the set of all functions consisting of four or fewer variables. Since
each rail of an NCL signal is considered a separate variable, a four variable function is
not the same as a function of four literals, which would normally consist of eight
variables.















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Table 2: ncl logic gates



Fig 2. THmn threshold gate


Fig 3.TH34w threshold gate
There are two types of NCL threshold gates: THmn and THmnWw1..wR,
where n represents the number of inputs and m is the threshold value of the gate [8].
This means that at least m of the n inputs must be asserted before the output becomes
asserted. Available w1..wR are the integer weights of input1..inputR, respectively.
For example, a TH34w2 gate has n = 4 inputs and its weight of the first input is w1 =
2. In order to assert its output, at least three of the four inputs must be asserted since
m = 3.
DEPT OF ECE,MLMCE 10

The inputs and outputs of a threshold gate can be one of two states, NULL or
DATA. For example, the 1-bit NCL register consists of two TH22n gates and a TH12
gate. A threshold gate starting with its output in an NULL state will remain in the
NULL state until the specified number of inputs are placed in the DATA state. Once
the gate reaches the DATA state, it remains in this state until all of the inputs return to
the NULL state. The hysteresis in the threshold gate provides the threshold needed to
keep from switching during intermediate state when the number of inputs in the
DATA state is between zero and the threshold limit.


Fig 4: Block Diagram Of NCL
NCL uses two states, DATA (i.e., data representation) and NULL (i.e., control
representation) to synchronize itself and control the input and output, eliminating the
need of a reference clock signal. To mark the transition between the NULL and
DATA states, each NCL combination logic must be bracketed by input and output DI
registers, these registers have an input/output acknowledgment signal that alternates
between 0s and 1s to provide request-for-NULL (i.e.,RFN) and request-for- DATA
(i.e.,RFD), respectively.
These signals are used to initiate a delay insensitive handshaking protocol that
handles timing locally. The four-phase handshaking protocol includes: 1) The proper
conditions are met to provide DATA at the output of the registration element; 2) RFN
goes back to its previous state; 3) All of the inputs to the registration element are at
NULL state; and 4) RFD is generated and it goes back to the previous state. The
completion detection component is used to determine whether the corresponding
pipeline stage is ready for another DATA/NULL cycle. It consists a cascade of NCL
AND gates at which the output is fed back to the previous register. When it detects
the current operation is a complete DATA set or a complete NULL set, the output will
DEPT OF ECE,MLMCE 11

be asserted to request the next cycle. Therefore, the period of DATA-to-DATA cycle
consists of four stages:
Time for NULL combinational evaluation (TNi ! TRNi+1);
Time for NULL completion acknowledgement (TNi+1 ! TRDi);
Time for DATA combinational evaluation (TDi ! TRDi+1);
Time for DATA completion acknowledgement (TDi+1 ! TRNi);
where TDi and TDi+1 represent the propagation time of DATA in the current stage
and next stage, respectively. Similarly, TNi and TNi+1 represent the propagation time
of NULL on the current stage and next stage, respectively. TRNi, TRDi, TRNi+1 and
TRDi+1 represent the acknowledge time of request for NULL/DATA on the current
or next stage, respectively.
4.3 Implementing Conventional S Box Using NCL
The main gates used in conventional S box are MUX,XOR,AND gates.To
implement the S BOX using NCL we need dual rail NCL gates[4]. NCL has a total of
27 threshold gates to realize various logic functions. In order to achieve the input
completeness and observability, it is important to choose appropriate threshold gates.
Consider a 2:1 mux according to the K map as shown in fig 5 according to the
Karnaugh
map in
Fig. 5, the sum-of-product (SOP) functions can be simplified as follows.

fig 5 k map of 2:1 mux








DEPT OF ECE,MLMCE 12

Z0 =A0S0 + S1B0 (1)

Z1 =A1S0 + S1B1. (2)
After modifying both functions for input completeness, new SOP functions are
obtained as follows:

Z0 =A0S0(A0 + A1)(B0 + B1) + S1B0(A0 + A1)(B0 + B1) (3)

Z1 =A1S0(A0 + A1)(B0 + B1) + S1B1(A0 + A1)(B0 + B1) (4)


Both the equation can be mapped to a NCL circuit witha TH24comp gate, a
THand0 gate and a TH22 gate. The finalized NCL MUX logic diagram is shown in
fig 6. Likewise, two TH24comp gates can be used to implement an XOR logic
function. THand0 and TH22 gates are used to implement an AND logic function.


Fig 6 NCL MUX


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Fig 7 (a) Input-complete NCL XOR and (b) NCL AND functions for the proposed NCL S-
Box.


4.4 FUNCTIONAL VERIFICATION OF PROPOSED NCL S-BOX
The proposed NCL S-Box has been implemented in veryhigh- speed
integrated circuits (VHSIC) hardware description language (VHDL) and simulated
with ModelSim by Mentor Graphics. The initial value of the input and that of the
output are NULL and DATA0, respectively, as previous input registers are reset to
NULL and output registers are reset to DATA0. As soon as the reset falls down to 0,
Ko from the output register becomes 1, and Ki for the input register connected to Ko
becomes 1. As Ki rises, the input is changed to the waiting input signal 01 01 01 01 01
01 01 01 in dual-rail signaling, which means 00000000 in binary and 0x00 in
hexadecimal. The output arrives later due to the propagation delay; the output
becomes 01 10 10 01 01 01 10 10 in NCL, which means 01100011 in binary and 0x63
in hexadecimal. The input signals are cumulative from 0 to 255, with increment by 1
in each cycle.
When the input signal increases from 0x00 to 0x02, and the corresponding
output signals are 0x63, 0x7C, and 0x77, respectively. The results are matching with
the standard S-Box. As every bit of the output signal changes from NULL to DATA,
Ko falls to 0, which means that the output register has received the proper output
DATA wave. Every single component (i.e., affine and inverse affine transformation,
and multiplicative inversion) has been separately verified. All the input/output data
were extracted using the VHDL textio package; then, a scripting program was written
DEPT OF ECE,MLMCE 14

to verify each of the output date, ensuring the function correctly. the NCL S-Box
output is 16 bits, which are the extended dual-rail signals. For example, for input 158,
the NCL S-Box output is 01 01 01 01 10 01 10 10, and this dual-railencoded data
word is equivalent to 00001011 in binary, which is equal to the output of the
conventional synchronous S-Box.





























DEPT OF ECE,MLMCE 15

CHAPTER 5
RESULT AND SIMULATIONS
5.1 SIMULATION TOOL
Xilinx ISE Design Suite 13.3 tool & VHDL programming is used.
MODELSIM tool is used for Simulation process. Xilinx Xpower Analyzer tool is
used for power analysis.


Fig 8:AES Encryption And Decryption

Inputs and outputs are 8 bits .Depending upon the select line given the output
is obtained.Each sub module also simulated separately and they further combined to
form entire top module





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Encryption
Input
Sub_in:00001001
Sub_in1:00001001
Sel:0
Output:
Crypto output:00000001
Decryption
Input
Sub_in:00000001
Sub_in1:0000001
Sel:1
Output
Crypto output:00001001




Fig 9 NCL Encryption And Decryption

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Inputs are 8 bit and outputs are 16 bits .Depending upon the select line given
the output is obtained.Each sub module also simulated separately and they further
combined to form entire top module

Encryption
Input
Sub_in:00001001
Decrypt:00001001
Sel:0
Output
Final_out: 0101010101010110
Decryption
Input
Sub_in:00000001
Decrypt:00000001
Sel:1
Output
Final_out: 0101010110010110









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5.2 COMPARISON OF RESULTS
Power , area and delayof the proposed NCL S BOX is compared with the AES
S BOX

Fig 10 Power Analysis Of AES



FIG 11 Power Analysis Of NCL




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FIG 12 AES S BOX Delay Report


FIG 13 NCL S BOX Delay Report







DEPT OF ECE,MLMCE 20





FIG 14 Device Utilization Of AES S BOX



FIG 15 Device Utilization Of NCL S BOX










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5.3 POWER COMPARISON

S BOX POWER(W) DELAY(ns) No.0f LUTs
AES S BOX 43.079 30.180 87
NCL S BOX 25.700 8.766 8
Table 3 Power Comparison



5.4 SIMULATION COMPARISON

MODE INPUT S BOX OUTPUT NCL S BOX
OUTPUT


ENCRYPTION

00001001 00000001 0101010101010110
00011010 10100010 1001100101011001
01101010 00000010 0101010101011001
01111010 11011010 1010011010011001
00000001 00001001 0101010110010110
10100010 00011010 0101011010011001
DECRYPTION 00000010 01101010 0110100110011001
11011010 01111010 0110101010011001
Table 4. Simulation Comparison











DEPT OF ECE,MLMCE 22

5.5 ADVANTAGES OF USING NCL
NCL is an asynchronous logic, which eliminates the need for a global clock
and the clock distribution network. Therefore, timing design is easier than its
synchronous counterpart due to the lack of requirement to compensate clock skew,
clock jitter, and glitches. NCL has the potential to process at its maximum frequency
due to the fact that the data go through path with minimal delay. This allows a NCL
circuit to potentially operate faster than a Boolean asynchronous design.
Another benefit of NCL is the lower power consumption. This is proved by
Jun Wu, Yiyu Shi, and Minsu Choi seniour members in IEEE , that total power
consumption of both synchronous S-Box and NCL S-Box is compared based on the
measurement results of EDA tools and FPGA simulation.
5.6 APPLICATION OF NCL
Asynchronous Nanowire Reconfigurable Crossbar Architecture (ANRCA).




















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CHAPTER 6
CONCLUSIONS AND FUTURE ENHANCEMENT
6.1 CONCLUSIONS
A new asynchronous combinational S-Box design for AES cryptosystems has
been proposed and validated in this work. The proposed S-Box design is based on a
delay-insensitive logic paradigm known as Null Convention Logic (NCL). The
proposed NCL S BOX and AES S BOX has been implemented in veryhigh- speed
integrated circuits (VHSIC) hardware description language (VHDL) and simulated
with ModelSim by Mentor Graphics.Power analysis performed in X Power Analyzer
in Xilinx 13. The proposed design has been compared with the existing synchronous
combinational logic AES S-Box design and the proposed NCL S BOX has 16 bit
output and its difficult for the attacker to decrypt the original data.The proposed
sytem has less power compared to the AES .the two S BOX has been vrfied in FPGA
SPARTEN 3.
6.2FUTURE ENHANCEMENT
Our future enhancement is the hardware implementation of proposed NCL S
BOX for studying side channel attack on various devices.
















DEPT OF ECE,MLMCE 24


REFRENCES

[1] NIST,Advanced Encryption Standard (AES), FIPSPUBS 197, National Institute
of Standards and Technology, NIST, Nov 2001
[2] P. Kocher, J. Jaffe and B. Jun, Introduction to differential power analysis and
related attacks, Technical Report, Cryptography Research Inc., San Francisco,
California, 1998.
[3] S. Moore, R. Anderson, P. Cunningham, R. Mullins and G. Taylor, Improving
smart card security using self-time circuits, Proceeding of Eighth International
Symposium on Asynchronous Circuits and System, pp. 211-218, IEEE Computer
Society, 2002.
[4] S. C. Smith and J. Di, Designing Asynchronous Circuits using NULL
Convention Logic, Synthesis Lectures on Digital Circuits and Systems, Vol. 4/1,
July 2009
[5] K. Tiri, D. Hwang, A. Hodjat, B.-C. Lai, S. Yang, P.Schaumont, and I.
VerbauwhedePrototype IC with WDDL and Differential Routing - DPA Resistance
Assessment, Workshop on Cryptographic Hardware and Embedded Systems (CHES
2005), LNCS, vol. 3659, pp. 354-365, Aug 2005
[6] S. Mangard, N. Pramstaller, and E. Oswald, Successfully Attacking Masked AES
Hardware Implementations, Workshop on Cryptographic Hardware and Embedded
Systems (CHES 2005), LNCS, vol. 3659, pp. 157-171, Aug 2005

[7] W. Johannes, O. Elisabeth and L. Mario, An ASIC Implementation of the AES
SBoxes, Topics in cryptology, CT-RSA 2002, LNCS, Vol. 2271, pp. 29-52, Jan
2002
[8] K. Fant and S. Brandt, NULL Convention Logic: A Complete and Consistent
Logic for Asynchronous Digital Circuit Synthesis, International Conference on
Application Specific Systems, Architectures, and Processors, pp. 261-273, 1996
[9] V. Satagopan, B. Bhaskaran, A. Singh, S.C. Smith, Automated energy calculation
and estimation for delay-insensitive digital circuits, Elseviers Microelectronics
Journal, Vol 38/10-11, pp. 1095-1107, Oct/Nov 2007
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[10] J.Wu, Y.-B. Kim, andM. Choi, Low-power side-channel attack-resistant
asynchronous s-box design for AES cryptosystems, in Proc. 20th Symp. Great Lakes
Symp. VLSI, 2010, pp. 459464.
[11] R. Jevtic and C. Carreras, Power measurement methodology for FPGA
devices, IEEE Trans. Instrum. Meas., vol. 60, no. 1, pp. 237247, Jan. 2011.





























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APPENDIX-1
VHDL CODE FOR NCL S BOX

library ieee;
use ieee.std_logic_1164.all;


entity multiply_with_constant_lamda is
port( x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0) );
end multiply_with_constant_lamda;


architecture ar of multiply_with_constant_lamda is
begin

y(3) <= x(2) xor x(0);
y(2) <= x(1) xor x(3) xor x(2) xor x(0);
y(1) <= x(3);
y(0) <= x(2);

end ar;
library ieee;
use ieee.std_logic_1164.all;


entity inverse_delta_block is
port( a : in std_logic_vector(7 downto 0);
b : out std_logic_vector(7 downto 0) );
end inverse_delta_block;


architecture ar of inverse_delta_block is
begin
DEPT OF ECE,MLMCE 27


b(7) <= a(7) xor a(6) xor a(5) xor a(1);
b(6) <= a(6) xor a(2);
b(5) <= a(6) xor a(5) xor a(1);
b(4) <= a(6) xor a(5) xor a(4) xor a(2) xor a(1);
b(3) <= a(5) xor a(4) xor a(3) xor a(2) xor a(1);
b(2) <= a(7) xor a(4) xor a(3) xor a(2) xor a(1);
b(1) <= a(5) xor a(4);
b(0) <= a(6) xor a(5) xor a(4) xor a(2) xor a(0);

end ar;

library ieee;
use ieee.std_logic_1164.all;


entity inv_affine_trans is
port( a : in std_logic_vector(7 downto 0);
b : out std_logic_vector(7 downto 0) );
end inv_affine_trans;


architecture ar of inv_affine_trans is
begin

b(7) <= a(6) xor a(4) xor a(1) xor '0';
b(6) <= a(5) xor a(3) xor a(0) xor '0';
b(5) <= a(7) xor a(4) xor a(2) xor '0';
b(4) <= a(6) xor a(3) xor a(1) xor '0';
b(3) <= a(5) xor a(2) xor a(0) xor '0';
b(2) <= a(7) xor a(4) xor a(1) xor '1';
b(1) <= a(6) xor a(3) xor a(0) xor '0';
b(0) <= a(7) xor a(5) xor a(2) xor '1';

DEPT OF ECE,MLMCE 28

end ar;

library ieee;
use ieee.std_logic_1164.all;

entity multipl_inves is
port(A:in std_logic_vector(7 downto 0);
B:out std_logic_vector(7 downto 0));

end multipl_inves;

architecture struc of multipl_inves is

component delta
port( a : in std_logic_vector(7 downto 0);
b : out std_logic_vector(7 downto 0) );
end component;

component squarer
port( x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0) );
end component;

component Multiplication
port( x : in std_logic_vector(3 downto 0);
y : in std_logic_vector(3 downto 0);
z : out std_logic_vector(3 downto 0) );
end component;

component multiply_with_constant_lamda
port( x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0) );
end component;
component NCL_XOR is
DEPT OF ECE,MLMCE 29

port(a,b:in std_logic;
z:out std_logic);
end component;

component inverse
port( x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0) );
end component;

component inverse_delta_block
port( a : in std_logic_vector(7 downto 0);
b : out std_logic_vector(7 downto 0) );
end component;
signal s1,s2:std_logic_vector(7 downto 0);
signal squ1_out,squ2_out:std_logic_vector(3 downto 0);
signal mm1,mm2,mm3,m1:std_logic_vector(3 downto 0);
signal inverse_1:std_logic_vector(3 downto 0);
signal xor_1,xor_2,xor_3:std_logic_vector(3 downto 0);
signal z0,z1,z2,z3,y0,y1,y2,y3,w0,w1,w2,w3:std_logic;

begin

xor_1<=z3&z2&z1&z0;
xor_2<=y3&y2&y1&y0;
xor_3<=w3&w2&w1&w0;
s2<= mm2(3 downto 0)&mm3(3 downto 0);

x1:delta port map(A,s1);
x2:squarer port map(s1(7 downto 4),squ1_out);
x3:squarer port map (s1(3 downto 0),squ2_out);
x4:multiplication port map(s1(7 downto 4),s1(3 downto 0),mm1);

x5:NCL_XOR port map (s1(7),s1(3),z3);
x6:NCL_XOR port map (s1(6),s1(2),z2);
DEPT OF ECE,MLMCE 30

x7:NCL_XOR port map (s1(5),s1(1),z1);
x8:NCL_XOR port map (s1(4),s1(0),z0);

x9:multiply_with_constant_lamda port map(squ1_out,m1);

x10:NCL_XOR port map(m1(3),squ2_out(3),y3);
x11:NCL_XOR port map(m1(2),squ2_out(2),y2);
x12:NCL_XOR port map(m1(1),squ2_out(1),y1);
x13:NCL_XOR port map(m1(0),squ2_out(0),y0);

x14:NCL_XOR port map(xor_2(3),mm1(3),w3);
x15:NCL_XOR port map(xor_2(2),mm1(2),w2);
x16:NCL_XOR port map(xor_2(1),mm1(1),w1);
x17:NCL_XOR port map(xor_2(0),mm1(0),w0);


x18:inverse port map(xor_3,inverse_1);
x19:multiplication port map(s1(7 downto 4),inverse_1,mm2);
x20:multiplication port map(inverse_1,xor_1,mm3);
x21:inverse_delta_block port map(s2,B);

end struc;
library ieee;
use ieee.std_logic_1164.all;


entity delta is
port( a : in std_logic_vector(7 downto 0);
b : out std_logic_vector(7 downto 0) );
end delta;


architecture ar of delta is
begin
DEPT OF ECE,MLMCE 31


b(7) <= a(7) xor a(5);
b(6) <= a(7) xor a(6) xor a(4) xor a(3) xor a(2) xor a(1);
b(5) <= a(7) xor a(5) xor a(3) xor a(2);
b(4) <= a(7) xor a(5) xor a(3) xor a(2) xor a(1);
b(3) <= a(7) xor a(6) xor a(2) xor a(1);
b(2) <= a(7) xor a(4) xor a(3) xor a(2) xor a(1);
b(1) <= a(6) xor a(4) xor a(1);
b(0) <= a(6) xor a(1) xor a(0);

end ar;
library ieee;
use ieee.std_logic_1164.all;


entity Multiplication is
port( x : in std_logic_vector(3 downto 0);
y : in std_logic_vector(3 downto 0);
z : out std_logic_vector(3 downto 0) );
end Multiplication;


architecture ar of Multiplication is

component Multi_2bit
port( x : in std_logic_vector(1 downto 0);
y : in std_logic_vector(1 downto 0);
z : out std_logic_vector(1 downto 0) );
end component;

component multiply_with_constant_O
port( x : in std_logic_vector(1 downto 0);
y : out std_logic_vector(1 downto 0) );
end component;
DEPT OF ECE,MLMCE 32


signal a1,a2 : std_logic_vector(1 downto 0);
signal b1,b2,b3 : std_logic_vector(1 downto 0);
signal c1 : std_logic_vector(1 downto 0);

begin

a1 <= x(3 downto 2) xor x(1 downto 0);
a2 <= y(3 downto 2) xor y(1 downto 0);

s1: Multi_2bit port map(x(3 downto 2),y(3 downto 2),b1);
s2: Multi_2bit port map(a1,a2,b2);
s3: Multi_2bit port map(x(1 downto 0),y(1 downto 0),b3);

s4: multiply_with_constant_O port map(b1,c1);

z(3 downto 2) <= b2 xor b3;
z(1 downto 0) <= b3 xor c1;

end ar;

library ieee;
use ieee.std_logic_1164.all;


entity multiply_with_constant_O is
port( x : in std_logic_vector(1 downto 0);
y : out std_logic_vector(1 downto 0) );
end multiply_with_constant_O;
architecture ar of multiply_with_constant_O is
begin

y(1) <= x(1) xor x(0);
y(0) <= x(1);
DEPT OF ECE,MLMCE 33


end ar;
library ieee;
use ieee.std_logic_1164.all;


entity squarer is
port( x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0) );
end squarer;


architecture ar of squarer is
begin

y(3) <= x(3);
y(2) <= x(2) xor x(3);
y(1) <= x(1) xor x(2);
y(0) <= x(0) xor x(1) xor x(3);

end ar;
library ieee;
use ieee.std_logic_1164.all;


entity sub_byte is
port( sub_in,decry : in std_logic_vector(7 downto 0);
sel:in std_logic;
sub_out : inout std_logic_vector(7 downto 0);
final_out:out std_logic_vector(15 downto 0));
end sub_byte;


architecture ar of sub_byte is
DEPT OF ECE,MLMCE 34


component multipl_inves is
port(A:in std_logic_vector(7 downto 0);
B:out std_logic_vector(7 downto 0));

end component;

component inv_affine_trans is
port( a : in std_logic_vector(7 downto 0);
b : out std_logic_vector(7 downto 0));
end component;

component NCL_MUX is
port(a,b,s:in std_logic;
z:out std_logic);
end component;

component affine_trans
port( a : in std_logic_vector(7 downto 0);
b : out std_logic_vector(7 downto 0) );
end component;
component NCL_MUX_mod is
port(a,b,s:in std_logic;
z:out std_logic_vector(1 downto 0));
end component;

signal out1,out2,x,m:std_logic_vector(7 downto 0):="00000000";
signal x0,x1,x2,x3,x4,x5,x6,x7:std_logic_vector(1 downto 0);
signal m0,m1,m2,m3,m4,m5,m6,m7:std_logic;
signal y0,y1,y2,y3,y4,y5,y6,y7:std_logic_vector(1 downto 0);
begin
--x<=x7&x6&x5&x4&x3&x2&x1&x0;
process(m0,m1,m2,m3,m4,m5,m6,m7,x0,x1,x2,x3,x4,x5,x6,x7,m)
begin
DEPT OF ECE,MLMCE 35

if( x7="01")then
m7<='0';
else
m7<='1';
end if;
if( x6="01")then
m6<='0';
else
m6<='1';
end if;
if( x5="01")then
m5<='0';
else
m5<='1';
end if;
if( x4="01")then
m4<='0';
else
m4<='1';
end if;
if( x3="01")then
m3<='0';
else
m3<='1';
end if;
if( x2="01")then
m2<='0';
else
m2<='1';
end if;
if( x1="01")then
m1<='0';
else
m1<='1';
DEPT OF ECE,MLMCE 36

end if;
if( x0="01")then
m0<='0';
else
m0<='1';
end if;

m<=m7 & m6 & m5 & m4 & m3 & m2 & m1 & m0;
end process;

s0:inv_affine_trans port map(decry,out1);

s1:NCL_MUX_mod port map (sub_in(7),out1(7),sel,x7);
s2:NCL_MUX_mod port map (sub_in(6),out1(6),sel,x6);
s3:NCL_MUX_mod port map (sub_in(5),out1(5),sel,x5);
s4:NCL_MUX_mod port map (sub_in(4),out1(4),sel,x4);
s5:NCL_MUX_mod port map (sub_in(3),out1(3),sel,x3);
s6:NCL_MUX_mod port map (sub_in(2),out1(2),sel,x2);
s7:NCL_MUX_mod port map (sub_in(1),out1(1),sel,x1);
s8:NCL_MUX_mod port map (sub_in(0),out1(0),sel,x0);

s9:multipl_inves port map(m,out2);
s10:affine_trans port map(out2,sub_out);
s11:NCL_MUX_mod port map (sub_out(7),out2(7),sel,y7);
s12:NCL_MUX_mod port map (sub_out(6),out2(6),sel,y6);
s13:NCL_MUX_mod port map (sub_out(5),out2(5),sel,y5);
s14:NCL_MUX_mod port map (sub_out(4),out2(4),sel,y4);
s15:NCL_MUX_mod port map (sub_out(3),out2(3),sel,y3);
s16:NCL_MUX_mod port map (sub_out(2),out2(2),sel,y2);
s17:NCL_MUX_mod port map (sub_out(1),out2(1),sel,y1);
s18:NCL_MUX_mod port map (sub_out(0),out2(0),sel,y0);

final_out<=y7&y6&y5&y4&y3&y2&y1&y0;

DEPT OF ECE,MLMCE 37

end ar;


library ieee;
use ieee.std_logic_1164.all;

entity NCL_XOR is
port(a,b:in std_logic;
z:out std_logic);
end NCL_XOR;
architecture behav of NCL_XOR is

signal a0,a1,b0,b1,c0,c1,z0,z1:std_logic;
begin
process(a0,a1,b0,b1,c0,c1,z0,z1,a,b)
begin
if(a='0')then
a0<='1';
a1<='0';
end if;

if(a='1')then
a0<='0';
a1<='1';
end if;
if(a='U')then
a0<='0';
a1<='0';
end if;
if(b='0')then
b0<='1';
b1<='0';
end if;
if(b='1')then
DEPT OF ECE,MLMCE 38

b0<='0';
b1<='1';
end if;
if(b='U')then
b0<='0';
b1<='0';
end if;


c0<=(a1 and b1);
c1<=(b0 and a1);
z0<=c0 or(a0 and b0);
z1<=c1 or (b1 and a0);

if(z0='0'and z1='1')then
z<='1';
elsif(z0='1' and z1='0')then
z<='0';
end if;
end process;
end ;
library ieee;
use ieee.std_logic_1164.all;

entity NCL_MUX_mod is
port(a,b,s:in std_logic;
z:out std_logic_vector(1 downto 0));
end NCL_MUX_mod ;
architecture behav of NCL_MUX_mod is

signal a0,a1,b0,b1,s0,s1,c0,c1,c2,z0,z1:std_logic;
begin
process(a0,a1,b0,b1,s0,s1,c0,c1,c2,z0,z1,a,b,s)
begin
DEPT OF ECE,MLMCE 39

if(a='0')then
a0<='1';
a1<='0';
end if;

if(a='1')then
a0<='0';
a1<='1';
end if;
if(a='U')then
a0<='0';
a1<='0';
end if;
if(b='0')then
b0<='1';
b1<='0';
end if;
if(b='1')then
b0<='0';
b1<='1';
end if;
if(b='U')then
b0<='0';
b1<='0';
end if;

if(s='0')then
s0<='1';
s1<='0';
end if;
if(s='1')then
s0<='0';
s1<='1';
end if;
DEPT OF ECE,MLMCE 40

if(s='U')then
s0<='0';
s1<='0';
end if;


c0<=((a0 and b0) or (a1 and b0) or (a0 and b1) or (a1 and b1));
c1<=((s1 and s0) or (s0 and a0) or (s1 and b0));
c2<=((s1 and s0) or (s0 and a1) or (s1 and b1));
z0<= c0 and c1;
z1<=c0 and c2;

--if(z0='0'and z1='1')then
-- z<='1';
-- end if;
-- if(z0='1' and z1='0')then
-- z<='0';

-- end if;
z<=z1&z0;
end process;
end ;