LG Zenith C-Line Zp94 95 Projection TV Training Manual 2000 (Et)

2000 C-Line Projection TV
Zp94 & ZP95
7HFKQLFDO 7UDLQLQJ 0DQXDO

3URGXFW 2YHUYLHZ
&KDVVLV 'HVFULSWLRQV
)DFWRU\ 6HWXS
&RQYHUJHQFH
&LUFXLW 7URXEOH 6KRRWLQJ
( ! " " # $
(
Z E N I T H E L E C T R O N I C S C O R P O R AT I O N
Q v r qD V T 6
C
! a r v u@ y r p v p 8 h v
201 JAMES RECORD ROAD HUNTSVILLE, AL. 35824
CONTENTS
Safety Information
........................................................................................................
General Information
........................................................................................................
Service Menus
........................................................................................................
Convergence Setup
........................................................................................................
15
Circuit Descriptions
........................................................................................................
28
Troubleshooting
........................................................................................................
90
PRODUCT SAFETY
PRODUCT SAFETY SERVICING GUIDELINES FOR AUDIO-VIDEO PRODUCTS
IMPORTANT SAFETY NOTICE
This manual was prepaired for use only by proporly trained audio-visual service
technicians.
A.C. VOLTMETER
When servicing this product, under no circumstances should the original design be
modified or altered without permission from Zenith Electronics Corporation. All
components should be replaced only with types identical to those in the original
circuit and their physical location, wiring and lead dress must conform to original
layout upon completion of repairs.
Special components are also used to prevent x-radiation, shock and fire hazard. These
components are indicated by the letter x included in their component designators
and are required to maintain safe performance. No deviations are allowed without
prior approval by Zenith Electronics Corporation.
Circuit diagrams may occasionally differ from the actual circuit used. This way,
implementation of the latest safety and performance improvement changes into the
set is not delayed until the new service literature is printed.
Caution: Do not attempt to modify this product in any way. Never perform
customized installations without manufacturers approval. Unauthorized modifications
will not only void the warranty, but may lead to property damage or user injury.
0.15uf
Good earth ground

such as a water
pipe, conduit, etc.
10 Watt
X-RADIATION
1.
Be sure procedures and instructions to all service personnel cover the subject of
x-radiation. The only potential source of x-rays in current TV receivers is the
picture tube. However, this tube does not emit x-rays when the HV is at the
factory-specified level. The proper value is given in the applicable schematic.
Operation at higher voltages may cause a failure of the picture tube or highvoltage supply and, under certain circumstances, may produce radiation in excess
of desirable levels.
The exclamation point within an equilateral triangle is intended

to alert the service personnel to important safety information in
the service literature.
2.
Only factory-specified CRT anode connectors must be used.
3.
It is essential that the service personnel have available an accurate and

reliable high-voltage meter.
The lightning flash with arrowhead symbol within an equilateral

triangle is intended to alert the service personnel to the presence
of noninsulated dangerous voltage that may be of sufficient
magnitude to constitute a risk of electric shock.
4.
When the high-voltage circuitry is operating properly, there is no possibility

of an x-radiation problem. Every time a color chassis is serviced, the
brightness should be run up and down while monitoring the high voltage
with a meter, to be certain that the high voltage does not exceed the
specified value and that it is regulating correctly.
5.
When troubleshooting and making test measurements in a product with a

problem of excessively high voltage, avoid being unnecessarily close to
the picture tube and the high voltage power supply. Do not operate the
product longer than necessary to locate the cause of excessive voltage.
6.
Refer to HV, B+, and shutdown adjustment procedures described in the

appropriate schematics and diagrams (where used).
Service work should be performed only after you are thoroughly familiar with these
safety checks and servicing guidelines.
Graphic symbols
The pictorial representation of a fuse and its rating within an

equilateral triangle is intended to convey to the service
personnel the following fuse replacement caution notice:
CAUTION: FOR CONTINUED PROTECTION AGAINST RISK OF
FIRE, REPLACE ALL FUSES WITH THE SAME TYPE AND
RATING AS MARKED NEAR EACH FUSE.
SERVICE INFORMATION
While servicing, use an isolation transformer for protection from AC line shock.
After the original service problem has been corrected, make a check of the following:
FIRE AND SHOCK HAZARD

1.
2.
3.
4.
1500 Ohm
Place this probe

on each exposed
metal part
Be sure that all components are positioned to avoid a possibility of

adjacent component shorts. This is especially important on items transported
to and from the repair shop.
IMPLOSION
1.
All direct view picture tubes are equipped with an integral implosion
protection system; take care to avoid damage during installation.
2.
Use only the recommended factory replacement tubes.
TIPS ON PROPER INSTALLATION

1.
Never install any receiver in a closed-in recess, cubbyhole, or closely

fitting shelf space over, or close to, a heat duct, or in the path of heated
air flow.
2.
Soldering must be inspected to discover possible cold solder joints,

solder splashes, or sharp solder points. Be certain to remove all loose
foreign particles.
Avoid conditions of high humidity such as: outdoor patio installations

where dew is a factor, near steam radiators where steam leakage is a factor,
etc.
3.
Check for physical evidence of damage or deterioration to parts and

components, for frayed leads or damaged insulation (including the AC
cord), and replace if necessary.
Avoid placement where draperies may obstruct venting. The customer

should also avoid the use of decorative scarves or other coverings that
might obstruct ventilation.
4.
Wall- and shelf-mounted installations using a commercial mounting kit

must follow the factory-approved mounting instructions. A product mounted
to a shelf or platform must retain its original feet (or the equivalent
thickness in spacers) to provide adequate air flow across the bottom. Bolts
or screws used for fasteners must not touch any parts or wiring.
Perform leakage tests on customized installations.
5.
Caution customers against mounting a product on a sloping shelf or in a

tilted position, unless the receiver is properly secured.
6.
A product on a roll-about cart should be stable in its mounting to the cart.

Caution the customer on the hazards of trying to roll a cart with small
casters across thresholds or deep pile carpets.
7.
Caution customers against using a cart or stand that has not been listed
by Underwriters Laboratories, Inc. for use with its specific model of
television receiver or generically approved for use with TVs of
the same or larger screen size.
8.
Caution customers against using extension cords. Explain that a forest of

extensions, sprouting from a single outlet, can lead to disastrous
consequences to home and family.
Verify that all protective devices such as insulators, barriers, covers,

shields, strain reliefs, power supply cords, and other hardware have been
reinstalled per the original design. Be sure that the safety purpose of the
`polarized line plug has not been defeated.
5.
No lead or component should touch a receiving tube or a resistor rated at

1 watt or more. Lead tension around protruding metal surfaces must be
avoided.
6.
After re-assembly of the set, always perform an AC leakage test on all

exposed metallic parts of the cabinet (the channel selector knobs, antenna
terminals, handle and screws) to be sure that set is safe to operate without
danger of electrical shock. DO NOT USE A LINE ISOLATION
TRANSFORMER DURING THIS TEST. Use an AC voltmeter having 5000
ohms per volt or more sensitivity in the following manner: Connect a 1500
ohm, 10 watt resistor, paralleled by a .15 mfd 150V AC type capacitor between
a known good earth ground (water pipe, conduit, etc.) and the exposed metallic
parts, one at a time. Measure the AC voltage across the combination of 1500
ohm resistor and .15 mfd capacitor. Reverse the AC plug by using a nonpolarized adaptor and repeat AC voltage measurements for each exposed
metallic part. Voltage measured must not exceed 0.75 volts RMS. This
corresponds to 0.5 milliamp AC. Any value exceeding this limit constitutes
a potential shock hazard and must be corrected immediately.
PRODUCT SAFTEY
CHASSIS HIGH VOLTAGE ADJUSTMENT
PROCEDURE
1. Connect High Voltage meter to FBT High
Voltage output. Connect Ground of High Voltage
meter to CRT Ground or FBT Ground.
2. Check that the High Voltage adjustment VR
(RH44) is set to its mechanical center on the
Deflection PWB. This VR is located just behind
the Flyback transformer as viewed from the
Front of the set. (See diagram below)
3. Receive an NTSC generator signal. (Picture
should be stationary for this adjustment.
4. Video Controls should be set to Factor Settings.
5. Adjust the High Voltage to the following specifications by turning RH44 slowly.
6. Lock Paint the control. If available.
Checking Procedure :
1. Check that the picture is turned off and the
horizontal deflection circuit stops operation.
After Checking:
1. Unplug set and Remove Jig. Allow set to remain
in the off condition for at least 15 seconds.
2. Apply AC and confirm the set returns to normal
operation.
+50V Pulse
DH24
CH30
Add JIG to check Hi

Volt Limit Circuit
JIG = 1k ohm 1/8W
RH54
DH31
RH55
TH01
FBT
RH44
High Voltage ADJ.
CHASSIS HIGH VOLTAGE LIMITER

CHECK
Check Preparation:
1. The set can face any direction.
2. Receive the Cross-Hatch Signal
3. VIDEO CONTROLS: Brightness to Maximum.
4. SCREEN FORMAT: Should be PROGRESSIVE mode.
5. Attach the JIG (1k ohm 1/8W resistor) to both
ends of DH31 as shown in the diagram below.
(See Diagram)
CHASSIS FLYBACK PROTECTION

CIRCUIT CHECK
Check Preparation:
3. VIDEO CONTROLS: Factory Preset.
5. Attach a 100 K ohm 1/16W ~ 1/8W resistor
between QP02 base and Gnd. (SD4 connector
Pin 4) and check operation.
After Checking:
1. Unplug set and Remove Jig. Allow set to remain
in the off condition for at least 15 seconds.
2. Apply AC and confirm the set returns to normal
operation.
PRODUCT SAFETY
CHASSIS SWEEP LOSS DETECTION
CIRCUIT CHECK
Check Preparation:
Check Number (1):
2 Receive the Cross-Hatch Signal
5. Attach the JIG (A) (100 ohm 1/8W resistor) to
right hand side of RN01 and to Ground as
shown in the diagram below.
Check Number (2):
5. Attach the JIG (B) (100 ohm 1/8W resistor) to
right hand side of RN11 and to Ground as
shown in the diagram below.
Checking Procedure :
1. Check that the picture is turned off in either
check.
After Checking:
1. Remove Jig after each check.
2. Confirm the set returns to normal operation.
&1
&1
PRODUCT SAFTEY
+9 &DEOH
7$%
)O\EDFN
326,7,21
9@AG@8UDPI
QX7
A7U
6IP9@
8PII@8UPS
Perform the following when the

HV connector (anode connector) is removed or inserted for
CPT replacement, etc.
),* %
3. Remove the connector slowly by pulling it away

from the case.
+9 &DEOH
%RRW $VVHPEO\
/(66 7+$1 PP

)O\EDFN
QVTC
QVTC
ADB6
During Removal
1. Roll out silicon cover from FBTs contact
area slowly.
2. While turning the connector about 90 degrees following the arrow (0 position). Push the
connector slightly toward the case. (Fig. A)
During Insertion
1. Please refer to direction for insertion as
shown in Fig. B (L position). Insert connector
until CLICK sound is heard.
2. Make sure the connector is pressed right in,
so that it has a good contact with the spring.
3. Confirm the contact by pulling the connector
slightly. (Dont pull hard because it may damage
the connector).
4. Cover the high voltage output by carefully
pushing silicon boot onto it. (Dont turn the
connector).
Note: Make sure the silicon boot is covering the
high voltage output.
GENERAL INFORMATION
SPECIFICATIONS FOR IQB-94/95 SERIES MODELS
Mode l:
IQC50H94/95
IQC60H94/95
R = P16LFM00RFA(LU)
G = P16LFM00HHA(LU)
B = P16LFM00BMB(EU)
120 Volt AC, 6OHz
Powe r Input
224/232 Watts - Maximum
Powe r
Consumption: 192/206 Watts Operating
75ohm Unbalanced
Antenna
Impedence :
VFH / UHF / CAT V
BAND
CH
Receiving
Channel:
VHF
2-13
UHF
14-69
EXT . Mid
(A-5)~(A-1),4+
CAT V Mid
A~I
CAT V Super
J~W
CAT V Hyper
(W+1) (W+28)
Picture
I-F
Carrier
45.75
MHz
Intermediate
Freque ncy:
Sound I-F Carrier 41.25 MHz
Color Sub Carrier 42.17 MHz
Vide o Input: 1 Volt p-p, 75 Ohm
1 Volt p-p, 75 Ohm (Y)
07. Volt p-p, 75 Ohm, (Cb, Cr)
Vide o O utput: 1 Volt p-p, 75 Ohm
Cathode -Ray
Tube:
Audio Input:
470 mVrms, 47 k Ohm
Stere o Audio O utput:

Audio O utput Power:
470 mVrms, 1 k Ohm

Front- 12 Watt at 10% distortion, 8 Ohm Imp.
Max Output - 24 Watt
30.0 + 1.5kv (1.25 + 0.2ma)
Anode Voltage :
Brightne ss
Size
Full White
50"
Brightne ss Max
Spe akers:
60"
Dime nsion:
Height
Width
Depth
Weight
Circuit Board
Asse mblies:
ZP94
130
ZP95
130
100
2 woofers - 5 Inch
(12cm) Round
50" Series Models
52
43 1/2
23 1/2
190
Power Supply P.W.B.
VM P.W.B
Surround P.W.B
Signal P.W.B.
Audio Out P.W.B.
2H P.W.B
Sensor Dist P.W.B.
100
60" Series Models

60 1/2
51 1/2
26 1/2
308
C.P.T . (B) P.W.B
C.P.T . (G) P.W.B.
C.P.T . (R) P.W.B.
Power/Deflection P.W.B.
Control P.W.B.
T erminal P.W.B
Sub Deflection P.W.B.
GENERAL INFORMATION
General Information
In 2000 Zenith will introduce a new C line of
Digital Ready Projection TVs. This new line will
help move Zenith forward with its goal to be the
Digital Leader in consumer electronic products and
reaffirm its continued commitment to supply
innovative and high quality products to our
customers. In this manual we will discuss the new
features and designs incorporated in the new
chassis line and newly designed cabinets in an
effort to enable our ASCs to offer better service
to our customers in the event that they require
service on their Zenith product.
The new C line ZP chassis family will be broken
down into service modules as follows: Power/
Deflection P.W.B., Main Chassis (Signal P.W.B.),
Signal Sub. P.W.B., VM P.W.B. Jack Pack and SP
Matrix (Audio) P.W.B. module. The new
Projection TV line will continue to be supported
to the modular level, which means that the repairs
to these units will be done by properly diagnosing
a defective module and replacing it. Since the
Projection TV line will be supported to the
modular level there will be no need to get prior
approval from Tech Support for defective module
replacement.
Remote Access
When using the MBR for customer menus, it must
be placed in the TV mode (by pressing the TV
button at the top). The customer menu is a bar of
ICONS at the top of the customer menu display.
By pressing the menu key you can select which
menu to use. Use of the Up/Down small arrows
allows the sub menu or feature item to be selected.
To adjust or change a feature selection you use the
Left/Right small arrows. Pressing the enter key
usually allows you to exit the customer menu.
<<figure 1>>
Video Performance
Mechanical features include a Delta 78 lens
system, single piece Fresnel screen with special
cut of the front and back to add in distortion
reduction when moving from one viewing position
to another. The screen also incorporates vertical
black strip matrixing which gives an increased
contrast ratio. Finally the set comes with the tinted
screen protector already installed to prevent
damage to the screen. (scratches and cracks)
Electrical Features include a 3 line comb filter for
processing incoming signals to provide fine detail
images. Auto skin tone circuitry automatically
maintains natural skin tones. Black level
enhancement, white level, and peak white level
compression circuitry maintains black/white
contrast ratio and peak luminance level for detail
in both light and dark video areas. All these features
work together to provide a resolution level of 1000
lines on the ZP94/95 series.
6
MBR3475Z
924-10068
GENERAL INFORMATION
SOURCE
-VOLUME+
-CHANNEL+
POWER
DIGITAL
SETUP
MENU
65
EXIT
65
69,'(2
9,'(2
/()7
5,*+7
$8',2
$8',2
DIGITAL CONVERGENCE
SETS ONLY
TV / VIDEO
Source Selector
<<figure 2. Control Panel>>
ANT A
To
Converter
S-VIDEO
S-VIDEO
S-VIDEO
ANT B
VIDEO
VIDEO
VIDEO
(MONO)
P BC B
(MONO)
P BC B
(MONO)
L
R
L
P RCR
AUDIO
TO HI-FI
P RCR
R
AUDIO
R
AUDIO
INPUT 1
INPUT 2
R
AUDIO
MONITOR
OUT
<<figure 3 Rear Connection Panel>>

7
SERVICE MENUS
Service Menu Access
To access the service menu on the ZP94/95 series;
1. Press and hold the SOURCE button on the user control panel at the front of the set.
2. While holding the SOURCE button, press the POWER button on the user control panel at the front of
the set to activate the service menu.
3. Receive signal on main picture.
4. Check the service menu items according to the following tables, using the up and down buttons on
Remote Control.
5. Press MENU key to exit service menu adjustment mode.
NOTE:
1. If there is a different value than shown in table above, for fixed data, adjust it using buttons (only
in this case).
2. When exchanging microprocessor and TV is turned on for first time, it requires initialization of
VIDEO CHROMA ADJ on P1 to P6.
SERVICE MENUS
ITEM
P01
ADJUST MODE
SETTING RANGE DESCRIPTIO N

ZP94/95
*Non-Adjustable Data
Version 704
SUB BRT
SERVICE
3C-C3 Sub Brightness

0
SERVICE
DEF RESET
V/P RESET
3DYC RESET
FLEX RESET
DSP RESET
CCD RESET
FACT RESET
MEMORY INITIAL
P02
ZP94/95
ADJUST MODE
T A1300 31.5khz M
315
H POSI
40
FLEX CONT
VD POS
3F
UPD64081
DYGA
09
DCGA
06
VAPGA
00
VAPIN
00
YHCOR
00
P02
ZP94/95
ADJUST MODE
T A1270-S
T INT (T V)
T OFFO (TV)
T OFQ (T V)
SUB CNT
SUB CLR
Resets Memory
Resets Memory
00-7F
Horizontal Position
00-7F
Vertical Position
00-0F
00-0F
00-07
00-1F
00-01
Y Motion Detection Gain

Chroma Motion Detection Gain
Vertical Aperture Controle Gain
Vertical Aperture Controle Invert
Y Output High Frequency Coring
00-7F
Horizontal Position
00-7F
Vertical Position
00-0F
00-0F
00-07
00-1F
00-01
Y Motion Detection Gain

Chroma Motion Detection Gain
Vertical Aperture Controle Gain
Vertical Aperture Controle Invert
Y Output High Frequency Coring
3C
00
00
0F
1B
ZP94/95
00-7F
00-07
00-07
00-1F
00-1F
Main NT SC T int
Main NT SC T OF fO Peak Frequency Switch
Main NT SC T OFQ Switch
Main NT SC Contrast
Main NT SC Color
3C
00
00
0F
1B
00-7F
00-07
00-07
00-1F
00-1F
Main NT SC T int
Main NT SC T OF fO Peak Frequency Switch
Main NT SC T OFQ Switch
Main NT SC Contrast
Main NT SC Color
T A1300 33.75khz M 3375

H POSI
40
FLEX CONT
VD POS
3F
UPD64081
DYGA
09
DCGA
06
VAPGA
00
VAPIN
00
YHCOR
00
P03
ZP94/95
ADJUST MODE
T A1270-M
T INT (T V)
T OFFO (TV)
T OFQ (T V)
SUB CNT
SUB CL
P03
ADJUST MODE
0
0
0
0
0
0
0
0
SERVICE MENUS
10
ITEM
P04
FLEX CONT
39 HHPF1
41 V-CRG
42 H-CRG
43 V-ENH
44 H-ENH
96 YVHENH
100 CVHENH
P04
FLEX CONT
39 HHPF1
41 V-CRG
42 H-CRG
43 V-ENH
44 H-ENH
96 YVHENH (720p
100 CVHENH
SETTING
ZP94/95
NT SC
00
00
00
00
00
0B
12
ZP94/95
AT SC
00
00
00
00
00
00 (10)
12
P05
FLEX CONT
71 YV-ENH
79 CV-ENH
87 YH-ENH
94 CH-ENH
66 YV-DSB
75 CV-DSB
82 YH-DSB
90 CH-DSB
69 YV-CLP
84 YH-CLP
P05
FLEX CONT
71 YV-ENH
79 CV-ENH
87 YH-ENH (1080i
94 CH-ENH
66 YV-DSB
75 CV-DSB
82 YH-DSB
90 CH-DSB
69 YV-CLP
84 YH-CLP
ZP94/95
NTSC
00
00
07
0F
00
00
00
00
00
00
ZP94/95
ATSC
00
00
07 (00)
0F
00
00
00
00
00
00
P06
FLEX CONT
97 YV-NLP
98 YH-NLP
101 Y-LMT
83 YH-FRQ
91 CH-FRQ
70 YV-LT I
78 CV-CT I
86 YH-LTI
93 CH-CT I
ZP94/95
NTSC
00
0A
FF
00
02
00
00
01
01
RANGE DESCRIPTIO N
00-01
00-03
00-03
00-03
00-03
00-1F
00-1F
Characteristic Switch 0 = Low Frequency, 1 = High Frequency

Vertical Enhance Coring
Horizontal Enhance Coring
Vertical Enhance
Horizontal Enhance
Y Vertical & Horizontal Enhance Gain
Color Vertical & Horizontal Enhance Gain
(480i, 480p, 1080i, 720p)

00-01 Characteristic Switch 0 = Low Frequency, 1 = High Frequency
00-03 Vertical Enhance Coring
00-03 Horizontal Enhance Coring
00-03 Vertical Enhance
00-03 Horizontal Enhance
00-1F Y Vertical & Horizontal Enhance Gain
00-1F Color Vertical & Horizontal Enhance Gain
00-0F
00-0F
00-0F
00-0F
00-03
00-03
00-03
00-03
00-0F
00-0F
Y Vertical Enhance Gain

Color Vertical Enhance Gain
Y Horizontal Enhance Gain
Color Horizontal Enhance Gain
Y Vertical Dynamic Shoot Balance Gain
Color Vertical Dynamic Shoot Balance Gain
Y Horizontal Dynamic Shoot Balance Gain
Color Horizontal Dynamic Shoot Balance Gain
Y Vertical Enhance Clip Offset
Y Horizontal Enhance Clip Offset
(480i, 480p, 1080i, 720p)

00-0F Y Vertical Enhance Gain
00-0F Color Vertical Enhance Gain
00-0F Y Horizontal Enhance Gain
00-0F Color Horizontal Enhance Gain
00-03 Y Vertical Dynamic Shoot Balance Gain
00-03 Color Vertical Dynamic Shoot Balance Gain
00-03 Y Horizontal Dynamic Shoot Balance Gain
00-03 Color Horizontal Dynamic Shoot Balance Gain
00-0F Y Vertical Enhance Clip Offset
00-0F Y Horizontal Enhance Clip Offset
00-3F
00-3F
00-FF
00-03
00-03
00-01
00-01
00-01
00-01
Y Vertical Nonlinear Peaking

Y Horizontal Nonlinear Peaking
Y Amplitude Limit
Y Horizontal HPF Peak Frequency Switch
Color Horizontal HPF Peak Frequency Switch
Y Vertical Enhance Clip 0 = Enhance, 1 = LT I
Color Vertical Enhance Clip 0 = CTI, 1 = Enhance
Y Horizontal Enhance Clip 0 = Enhance, 1 = LT I
Color Horizontal Enhance Clip 0 = CT I, 1 = Enhance
SERVICE MENUS
ITEM
P06
FLEX CONT
97 YV-NLP
98 YH-NLP
101 Y-LMT
83 YH-FRQ
91 CH-FRQ
70 YV-LT I
78 CV-CT I
86 YH-LT I
93 CH-CT I
P07
FLEX CONT
69 YVDSBC
77 CVDSBC
85 YHDSBC
92 CHDSBC
95 Y-CRG
99 C-CRG
64 YNR-IN
73 CNR-IN
80 YNRPAS
88 CNRPAS
P07
FLEX CONT
69 YVDSBC
77 CVDSBC
85 YHDSBC
92 CHDSBC
95 Y-CRG
99 C-CRG
64 YNR-IN
73 CNR-IN
80 YNRPAS
88 CNRPAS
P08
FLEX CONT
65 YNRRDC
74 CNRRDC
67 YNR-DC
76 CNR-DC
81 YNR-O
89 CNR-O
45 CB-BLK
46 CR-BLK
27 FRMBRT *
102 CLPOUT
P09
FLEX CONT
10 MPLL-S
17 SPLL-S
12 MPLL-E
19 SPLL-E
11 MVW-PH
18 SVW-PH
14 MHS-HP
21 SHS-HP
13 MY-CLP
20 SY-CLP

ZP94/95
AT SC
(480i, 480p, 1080i, 720p)
00
00-3F Y Vertical Nonlinear Peaking
0A
00-3F Y Horizontal Nonlinear Peaking
FF
00-FF Y Amplitude Limit
00
00-03 Y Horizontal HPF Peak Frequency Switch
02
00-03 Color Horizontal HPF Peak Frequency Switch
00
00-01 Y Vertical Enhance Clip 0 = Enhance, 1 = LTI
00
00-01 Color Vertical Enhance Clip 0 = CT I, 1 = Enhance
01
00-01 Y Horizontal Enhance Clip 0 = Enhance, 1 = LTI
01
00-01 Color Horizontal Enhance Clip 0 = CT I, 1 = Enhance
ZP94/95
NTSC
00
00-07 Y Vertical Dynamic Shoot Balance Coring Amplitude
00
00-07 Color Vertical Dynamic Shoot Balance Coring Amplitude
00
00-07 Y Horizontal Dynamic Shoot Balance Coring Amplitude
00
00-07 Color Horizontal Dynamic Shoot Balance Coring Amplitude
00
00-07 Y Coring Amplitude
00
00-07 Color Coring Amplitude
04
00-07 YNR Input Level Gain
04
00-07 CNR Input Level Gain
00
00-07 YNR Passage Level Limit
02
00-07 CNR Passage Level Limit
ZP94/95
ATSC
(480i, 480p, 1080i, 720p)
00
00-07 Y Vertical Dynamic Shoot Balance Coring Amplitude
00
00-07 Color Vertical Dynamic Shoot Balance Coring Amplitude
00
00-07 Y Horizontal Dynamic Shoot Balance Coring Amplitude
00
00-07 Color Horizontal Dynamic Shoot Balance Coring Amplitude
00
00-07 Y Coring Amplitude
00
00-07 Color Coring Amplitude
04
00-07 YNR Input Level Gain
04
00-07 CNR Input Level Gain
00
00-07 YNR Passage Level Limit
02
00-07 CNR Passage Level Limit
ZP94/95
NT SC/ATSC (480i, 480p, 1080i, 720p)
00
00-07 YNR Reducing Gain
00
00-07 CNR Reducing Gain
00
00-03 YNR DC Shift
00
00-03 Color DC Shift
00
00-07 YNR 0 Point
00
00-0F CNR 0 Point
07
00-0F CB Blanking Level Offset
07
00-0F CR Blanking Level Offset
60
00-7F Y Frame Bright
7F
00-FF Clamp Output Offset
ZP94/95
NT SC/ATSC
0F
00-1F Main PLL Vertical Mask Pulse Start Position Offset
0F
00-1F Sub PLL Vertical Mask Pulse Start Position Offset
0F
00-1F Main PLL Vertical Mask Pulse End Position Offset
0F
00-1F Sub PLL Vertical Mask Pulse End Position Offset
05
00-07 Main Vertical Write Input Horizontal Phase Adjustment
05
00-07 Sub Vertical Write Input Horizontal Phase Adjustment
0F
00-1F Main Horizontal Sync Horizontal Phase Offset
0F
00-1F Sub Horizonyal Sync Horizontal Phase Offset
03
00-07 Main Y Clamp Refrence Offset
03
00-07 Sub Y Clamp Refrence Offset
11
SERVICE MENUS
ITEM
P10
FLEX CONT
23 V-POS
24 V-SIZ
50 HD-POS
48 VBLK-T
49 VBLK-B
51 HBLK-R
52 HBLK-L
40 READ F
P11
FLEX CONT
35 FRMT OP-2
FRMT OP-L*
36 FRMBTM-2
FRMBT M-L*
37 FRMRGT
38 FRMLFT
59 BS-TOP
60 BS-BT M
61 BS-RGT
62 BS-LFT
P12
FLEX CONT
120 T V/CINE
121 T /C DET
122 T /C UNL
123 T /C LCK
126 T /C ARE
127 T /C CBR
128 T /C YBR
P13
T A1298
SHARP
APACON
YNR
P13
T A1298
SHARP
APACON
YNR
P13
T A1298
SHARP
APACON
YNR
P13
T A1298
SHARP
APACON
YNR
P13
T A1298
SHARP
APACON
YNR
12

ZP94/95
NT SC/ATSC (480i, 480p, 1080i, 720p)
3F
00-3F Wide Vertical Position
7F
00-FF Wide Vertical Size
3F
00-7F HD Position Offset
7F
00-FF Vertical Blanking Top Position Offset
7F
00-FF Vertical Blanking Bottom Position Offset
7F
00-FF Horizontal Blanking Right Position Offset
7F
00-FF Horizontal Blanking Left Position Offset
10
00-3F A/D Converter Clock Sampling Phase
ZP94/95
NT SC/ATSC (480i, 480p, 1080i, 720p)
07
00-0F Frame Top Position Offset (2Pix)
07
00-0F Frame Top Position Offset (Letter)
07
00-0F Frame Bottom Position Offset (2Pix)
07
00-0F Frame Bottom Position Offset (Letter)
07
00-0F Frame Right Position Offset
07
00-0F Frame Left Position Offset
07
00-0F Black Strech Stop Pulse T op Position Offset
07
00-0F Black Strech Stop Pulse Bottom Position Offset
07
00-0F Black Strech Stop Pulse Right Position Offset
07
00-0F Black Strech Stop Pulse Left Position Offset
ZP94/95
01
07
01
03
05
07
07
ZP94/95
NTSC
0C
06
00
ZP94/95
480I
0A
06
00
ZP94/95
480P
0A
06
00
ZP94/95
1080I
07
05
00
ZP94/95
720P
0A
06
00
00-01
00-0F
00-07
00-0F
00-FF
00-0F
00-0F
T V Cinema Detection
T V Cinema Detection Vertical Gate Area Start Position
T V Cinema Detection Unlock Protection Count
T V Cinema Detection Lock Protection Count
T V Cinema Detection Motion Area Border Volume Offset
T V Cinema Detection Color 2 Bit Border Volume Offset
T V Cinema Detection Y 2 Bit Border Volume
00-1F
00-07
00-03
Sharpness (Center Adjustment)

APACON Peak fO
YNR
00-1F
00-07
00-03

APACON Peak fO
YNR
00-1F
00-07
00-03

APACON Peak fO
YNR
00-1F
00-07
00-03

APACON Peak fO
YNR
00-1F
00-07
00-03

APACON Peak fO
YNR
SERVICE MENUS
ITEM
P14
T A1298
COLOR
T INT
R-Y PH
R/B GA
G-Y PH
G/B GA
COLOR SYSTEM
P14
T A1298
COLOR
T INT
R-Y PH
R/B GA
G-Y PH
G/B GA
COLOR SYSTEM
P14
T A1298
COLOR
T INT
R-Y PH
R/B GA
G-Y PH
G/B GA
COLOR SYSTEM
P15
T A1298
RGB BRT
RGB CNT
G DRV (W)
B DRV (W)
SUB CLR
SUB CNT
VSM PH
VSM GA
OS ACL
RGB ACL
P16
T A1298
CLR G
CLT
YOUT G
YG PNT
S T RK
RGBG
DC PNT
DC RAT
DC LMT
SETTING
ZP94/95
NT SC
40
45
02
01
00
00
00
ZP94/95
SDTV
4F
3B
02
02
01
00
01
ZP94/95
HDTV
40
43
00
02
02
00
01
ZP94/95
RANGE DESCRIPTIO N
00-7F
00-7F
00-03
00-03
00-03
00-03
00-07
Color (Center Adjustment)

T int (Center Adjustment)
R-Y Phase
R/B Gain
G-Y Phase
G/B Gain
COLOR SYST EM
00-7F
00-7F
00-03
00-03
00-03
00-03
00-07

R-Y Phase
R/B Gain
G-Y Phase
G/B Gain
COLOR SYST EM
00-7F
00-7F
00-03
00-03
00-03
00-03
00-07

R-Y Phase
R/B Gain
G-Y Phase
G/B Gain
COLOR SYST EM
50
50
39
2D
10
1F
05
00
01
00
ZP94/95
00-7F
00-7F
00-7F
00-7F
00-1F
00-1F
00-07
00-03
00-01
00-01
RGB Brightness
RGB Contrast
Green Drive (WARM)
Blue Drive (WARM)
Sub Color (Demodulator)
Main NT SC Contrast
VM Phase
VM Gain
OSD Auto Contrast Limiter Switch
RGB Auto Contrast Limiter Switch
00
00
00
00
00
00
00
00
00
00-03
00-01
00-01
00-01
00-03
00-01
00-07
00-07
00-03
Color G Corection Piont

Color Limiter Level
Y G (After Contrast) Switch
Y G Point
Sharpness T racking
RGB Switch
DC Restoration Point
DC Restoration Rate
DC Restoration Limit Point
13
SERVICE MENUS
ITEM
P17
T A1298
BSP
APL/BS
B COR
B GA
B DET
DABL PN
DABL GA
ABL PN
ABL GA
P18
V CHIP RAT ING
POLLING
T IMEOUT
STAT US
SETTING
ZP94/95
RANGE DESCRIPTIO N
03
00
01
00
00
00
07
07
05
ZP94/95
00-07
00-03
00-01
00-01
00-01
00-07
00-07
00-07
00-07
Black Strech Point

APL / Black Strech Point
Black Level Correction
Black Strech Gain
Black Detect Level
Dynamic ABL Detection Point
Dynamic ABL Gain
ABL Detection Point
ABL Gain
0F
05
02
00-0F
00-0F
00-0F
0
0
0
AFC/CLOCK T EST
SERVICE ADJUSTMENT PROCEDURE ORDER

The following is the suggested order for adjustment procedures.
ZP 94/95 SERVICE ADJUSTMENT ORDER PREHEAT BEFORE BEGINNING

Adjustment Item
Screen Format
Signal
DCU Data
Pre HEAT
N/A
NTSC
N/A
Cut Off
Progressive
NTSC
Pre Focus Lens and Static
Progressive
NTSC
DCU Phase Data Setting
Progressive
NTSC
DCU Phase Data Setting
HD
2.14H
Horz. Position Adj. (Coarse)
Progressive
NTSC
Horz. Position Adj. (Coarse)
HD
2.14H
Raster Tilt
Progressive
NTSC
CLEAR
Beam Alignment
Progressive
NTSC
Raster Position
Progressive
NTSC
CLEAR
Horz. Size Adjust
Progressive
NTSC
CLEAR
Horz. Size Adjust
HD
2.14
CLEAR
Vertical Size Adjust
Progressive
NTSC
CLEAR
Beam Form
Progressive
NTSC
Lens Focus Adjust
Progressive
NTSC
Static Focus Adjust
Progressive
NTSC
Blue Defocus
Progressive
NTSC
White Balance Adjustment
Progressive
NTSC
Sub Brightness Adjustment
Progressive
NTSC Color Bar
Horz. Position Adjustment
Progressive
NTSC
Horz. Position Adjustment
HD
2.14H
Convergence Alignment
Progressive
NTSC
CLEAR to start
Convergence Alignment
HD
2.14H
necessary to follow the order when performing an alignment on the ZP 94/95 chassis.
Order
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
It is
14
CONVERGENCE
MEMORY INITIALIZATION PROCEDURE
WARNING: This should only be done in extreme
cases. I2C Data will be reset as well. Be sure
and write down all data values before
continuing.
1. Disconnect Power to Television.
2. Remove the Back Cover.
3. Remove the two screws holding the Main chassis
to the Cabinet if necessary.
4. Disconnect wiring harness clips to free up the
chassis if necessary.
5. Reconnect Power to the Television and turn the
set ON.
6. Locate PP1 and add a jumper between pins 1
and 2 of the PP1 connector.
7. Hold jumper in place for 5 seconds. (A beep will
NOT be heard).
8. Remove the jumper.
9. Confirm EEPROM reset, Input source is now set
to Air and not to Cable 1 or 2. No Child Lock,
and only channels 2 through 13 are in memory.
10.Reassemble Chassis and reinstall PTV back. Set
is now ready to operate.
NOTE: All customers' Auto Programming and
Set-Ups are returned to factory settings.
Pre HEAT
PRESET EACH ADJUSTMENT VR TO CONDITION AS SHOWN:
A) Before Pre Heat Run.
1. Red and Green Drive VR on the CRT PWB. (Not
on Blue CRT).
a
2. SCREEN VR ON FOCUS PACK.
6&5((1 95
Pre Set fully counter clockwise.

3. Focus VR on focus pack
)2&86 95
Pre Set fully clockwise.

CUT OFF
ADJUSTMENT PREPARATION:
A) Pre Heat Run should be finished.
ADJUSTMENT PROCEDURE:
1. Go to I2C ADJ Mode. Press and hold the
Source key on the front panel and then POWER
ON to access I2C adjustment mode.
2. Choose SERVICE item [2] of I2C ADJ. Mode.
(Select CURSOR RIGHT (right arrow key).
3. Screen VR should be turned clockwise gradually
and set so that retrace lines begin to appear.
4. Return to normal mode by using the left arrow key.
5. Adjust focus VRs so that focus is even all around
the screen.
PRE-FOCUS ADJUSTMENT
Adjustment preparation
1. The set can face in any direction: west, east,
north or south.
2. Receive the cross-hatch pattern signal.
'5,9( 95
Pre set between the 12 oclock and 2 oclock

position.
CONTRAST : 60-70%
BRIGHTNESS : 50%
3. The electrical focus adjustment should have been
completed.
4. The centering DY inclination should have been
adjusted.
15
CONVERGENCE
Adjustment procedure
1. Loosen the fixing screw on the lens cylinder so
that the lens cylinder can be turned. (Be careful
not to loosen too much. If the screw is loosened too much, rattling when tightening becomes
greater and the focus may drift). After completing
steps (5), (6), and (7) below, tighten the fixing
screws for each lens with a torque of 12~17 Kgf
cm.
S@9
8CSPH6UD8
67@SS6UDPI
TGDBCU`7GV@8CSPH6UD867@SS6UDPI
PSIP8PGPS
2. Apply covers to 2 of R, G, and B lenses, and

project a single color on the screen and adjust in
sequence.(The adjustment order of R, G, and B is
only an example.)
3. For each of the R, G, and B lenses, observe the
color aberration generated on the outer circumference of the cross-hatch bright line at the center
section (3 pitches vertically and horizontally from
the center.)
4. If the lens adjustment knob is turned clockwise,
viewed from the front, the color aberration
changes as follows.
Lens
R Lens
G Lens
B Lens
16
Set Size
50"
55"
60"
Pitch between L1 & L2

3.0 cross-hatch pitches
6. In case of R lens, set to the position where the

chromatic aberration changes from red to crimson. As shown below, observe the vertical bright
line at the center and set to the position where the
crimson chromatic aberration slightly appears
inside and red outside (reference value: 1~3mm)
within the cross-hatch pitches specified in next
Change of color aberration

Red
Crimson
Blue
Red
Purple
Green
5. In case of G lens, set to the point where the

chromatic aberration switches from blue to red.
If the chromatic aberration appearing all over the
screen is not the same, observe the vertical bright
line at the center of the screen and set to the
position where red chromatic aberration slightly
appears inside and blue outside (reference value:
1~3mm) within the cross-hatch pitches specified
in next table. When the red chromatic aberration
appearing at both sides of the bright line is not
equal, observe the side with larger chromatic
aberration when adjusting.
G!
S@9
8CSPH6UD8
.ebalt
67@SS6UDPI
TGDBCU`8SDHTPI
8CSPH6UD867@SS6UDPI
Set Size
50"
55"
60"
Pitch between L
7. In case of B lens, set to the position where the

chromatic aberration changes from purple to
green. As shown below, observe the vertical
bright line at the center and set to the position
where green chromatic aberration slightly appears
inside and purple outside (reference value:
1~3mm) within the cross-hatch pitches specified
in next table.
CONVERGENCE
G
QVSQG@8CSPH6UD8
TGDBCU`BS@@I
67@SS6UDPI
8CSPH6UD867@SS6UDPI
Set Size
50"
55"
60"
Pitch between L
NOTES:
1. Fixing screw
2. Color aberration
ADYDIBT8S@X
8PGPS
67@SS6UDPI
/(16
8SPTTC6U8C
3. Since the G light is very important for picture

quality and performance, pay special attention
in its adjustment.
NOTE: Be careful not to touch the lens with
your fingers when adjusting.
4. For red, setting to the center between red and
crimson is optimum.
5. For blue, setting to the center between purple
and green is optimum.
DCU PHASE DATA SETTINGS
Adjustment Preparation
1. Cut off adjustment should be finished
2. VIDEO CONTROL: Factory Preset Condition
PROGRESSIVE MODE
1. Receive any NTSC signal (Set is in Progressive
mode)
2. Push SERVICE ONLY SW on Deflection
PWB (Enter to DCU ADJ. Mode)
3. Push (?) key on R/C. (Green cross hatch is
displayed). Then push (QUIT) key on R/C.
(Character pattern is displayed. This is the
PHASE setting mode)
4. Set PH-H phase data as shown below using (4)
and (6) key.
5. Set PH-V phase data as shown below using (2)
and (5) key.
6. Set CR-H phase data as shown below using (<)
and (>) key.
7. Set CR-V phase data as shown below using (up)
and (down) arrow keys.
8. Push (?) key on R/C to exit from the PHASE
mode.
9. Push (-)* key on R/C 2 time to write the phase
data to the E2PROM.
10.When Green dots are displayed, push (MUTE)
key to return to DCU ADJ. mode.
11. Push SERIVCE ONLY SW to return to RF
or VIDEO mode.
HD MODE
12. Receive any HD signla (Set is in HD Mode)
13. Repeat (2)~(11) procedure again.
PROGRESSIVE MODE
PHASE MODE:
PH-H: BB
PH-V: OC
CR-H: 4C
CR-V: 00
HD MODE
PHASE MODE:
PH-H: BB
PH-V: O7
CR-H: 4C
CR-V: 0C
CHASSIS HORIZ PHASE (COARSE) ADJUSTMENT

Adjustment Preparation:
1) Cut Off, DCU Phase adjustments should be finished.
2) Video Control: Brightness 90%, Contrast Max.
17
CONVERGENCE
Adjustment Procedure
PROGRESSIVE MODE
1) Receive any NTSC crosshair signal.
2) Screen Format is PROGRESSIVE.
3) Press the SERVICE ONLY switch on the deflection PWB and display the Digital Convergence
Crosshatch pattern.
4) Mark the center of the Digital Convergence Crosshatch Pattern with finger and press the SERVICE
ONLY switch to return to normal mode.
5) Enter the I2C Bus alignment menu and select Item
[12] H POSI and adjust the data so that the center of Video matches the location of the Digital
Crosshatch pattern noted in step {4}.
6) Exit from the I2C Menu.
HD Mode Adjustment
1) Receive any 2.14H signal.
2) Screen Format is HD.
3) Press the SERVICE ONLY switch on the deflection PWB and display the Digital Convergence
Crosshatch pattern.
4) Mark the center of the Digital Convergence Crosshatch Pattern with finger and press the SERVICE
ONLY switch to return to normal mode.
5) Enter the I2C Bus alignment menu and select Item
[12] H POSI and adjust the data so that the center of Video matches the location of the Digital
Crosshatch pattern noted in step {4}.
6) Exit from the I2C Menu.

2. Input the single cross test signal.
3. Set video conditions to factory reset.
4. The lens focus adjustment should have been
completed, screen format should be progressive.
5. The electric focus should have been coarse
adjusted.
6. The digital convergence RAM should be cleared
(uncorrected state). With the TV set off, press
and hold the service switch located on the Power/
Deflection PWB and then press the power
button.
7. Start adjustment 20 minutes or more after TV is
turned on.
1. Apply covers to the R and B lenses and project
only green light or short 2P plug on R & B.
2. Turn the G deflection yoke and adjust the vertical
raster inclination.
3. Then, remove the cover of R or B lens and
project red or blue light together on the screen.
4. Turn the deflection yoke of R or B and set so that
the inclination of R or B with respect to the green
light is as shown below on the top and bottom
sides.
5. After raster inclination adjustment, fixing screw of
DY should be screwed with 12+2kg-cm torque.
7@APS@
68UDW@
WD9@P
RASTER INCLINATION ADJUSTMENT

(DEFLECTION YOKE)
VT@8VSTPS
8@IU@S
F@`TUPHPW@
ASPH
9PUU@9GDI@T
TU@Q$
7@UX@@I7@IU
GDI@TADSTU
@ 1!
Brr
Srq
7yr
UC@IVT@IVH7@SF@`TUPH6U8CDIU@SI6G
8SPTTC6U8C8@IU@SUP68UDW@WD9@P8@IU@S
6AU@S
@!
8uhpuBrr
18
CONVERGENCE
Notes:
1. If internal cross-hatch does not appear after
clearing RAM data, press service switch again,
on POWER/DEFLECTION PWB.
2. To restore old RAM data, turn TV off and on.
6. If image position does not shift when Green (G)

static focus (Focus Pack) is turned. Green (G)
beam alignment has been completed.
7. If image position shifts when Green (G) static
focus (Focus Pack) is turned, repeat (2)-(6).
BEAM ALIGNMENT
8. Conduct beam alignment for Red (R) focus:

Focus Pack UFPK, Blue (B) focus: Focus Pack
UFPK.
1. Adjust at least 30 minutes after turning on power

switch.
9. Upon completion of adjustment, fix beam alignment magnets with white paint.
2. Raster inclination, centering, horizontal and

vertical amplitudes, and optical focus adjustment
should be completed.
VERT & HORIZ PICTURE POSITION

ADJUSTMENT
3. Set video conditions, Brightness to 90% and

Contrast MAX.
1. Select signal on main picture.
4. Receive cross-hatch signals. (Use of internal

cross-hatch signals allowed.) Raster Tilt should
be finished.
5. Screen format should be Progressive.

1. Green (G) tube beam alignment adjustment.
Short-circuit 2P subminiature connector plug pins
of Red (R) and Blue (B) on the CPT boards and
project only Green (G) tube.
2. Put Green (G) tube beam alignment magnet to the
cancel state as shown below.
3. Turn the Green (G) static focus (Focus Pack)

counterclockwise all the way and make sure of
position of cross-hatch center on screen. (Halo
state.)
4. Turn the Green (G) static focus (Focus Pack)
clockwise all the way. (Blooming state.)
5. Turn two magnets forming alignment magnet in
any desired direction and move cross-hatch
center to position found in (3).
2. Video settings have to be at normal condition.

1. Press the SOURCE and POWER button on
Control Panel at same time to access VIDEO
CHROMA ADJUST mode.
2. Select H POSI and V POSI using 56 buttons.
3. Adjust the H POSI (HORIZONTAL) and
VPOSI (VERTICAL) position using 34 buttons.
4. Press MENU button to exit VIDEO CHROMA
ADJUST mode.
5. Select single PINP mode and move the sub
picture, using the MOVE button. Distance
between PINP and edge of screen should be
equal when moved. If it is not, repeat (1) ~ (5).
NOTE: For ZP94/95 Models check the position
of MULTI PINP mode. Check the right edge
of the sub pictures for MV-4 to make sure there
is no separation between the MULTI PINP and
the edge of the screen.
HORIZONTAL SIZE
Digital Convergence RAM should be cleared. With
Power Off, press and hold the Service Only
Switch on the Deflection PWB, then press Power.
Adjustment Prerparation
1. The set can face east or west
19
CONVERGENCE
2. Set video conditions to factory preset.
3. The electric focus should have been coarse adjusted.
turned on.
PROGRESSIVE MODE
1. Receive any NTSC signal.
2. Press the SERVICE ONLY SW on DEFLECTION PWB.
3. Locate the horizontal size VR (R683). Adjustable
the horizotal size to the table below.
HD MODE
1. Input 1080i (fH=33.75kHz) component signal to
VIDEO 1 or 2.
3. Locate the horizontal size VR (R686). Adjustable
the horizotal size to the following table.
Size
50"
60"
Adjustment Prerparation
1. The set can face east or west
2. Set video conditions to factory preset.
3. The electric focus should have been coarse adjusted.
turned on.
PROGRESSIVE MODE
1. Receive any NTSC signal.
3. Locate the vertical size VR (R630). Adjustable the
vertical size according to the table below.
Size
50"
60"
O
670mm
775mm
Adjust Vertical Size until the size matches the chart

below.
Progressive Mode HD Mode

1050mm
1050mm
1200mm
1200mm
Adjust Horizontal Size until the size matches the

chart below.
BEAM FORM
1. The beam alignment should have been completed.
2. The raster inclination, centering, horizontal/

vertical amplitude and optical focus adjustments
should have been completed.
3. Set video conditions to Brightness to 90 %
andContrast to MAX.
VERTICAL SIZE
Digital Convergence RAM should be cleared.
With Power Off, press and hold the Service Only
Switch on the Deflection PWB, then press Power.
20
4. Input the dot signal.

1. Green CRT beam shape adjustment. Shortcircuit 2P sub-mini connectors on Red and Blue
CRT P.W.B.s to project only the Green beam.
CONVERGENCE
2. Turn the green static focus fully clockwise.
(Blooming.)
ADYDIBT8S@X
3. Make the dot at the screen center a true circle

using the 4-pole magnet as shown below.
4. Also adjust the Red and Blue CRT beam shapes
according to the steps (1) to (3).
/(16
5. After the adjustment has been completed, return

R,G and B static VRs to the just focus point.
QSUTshprTvqr
#Qyr7rh
6yvtr
Hhtr
arAvryq
ThprI
!Qyr7rh
6qwr
6yvtr
Hhtr
Ur8vpyr9rtrr)hi
Trpvsvphv)(
h
LENS FOCUS ADJUSTMENT

Preparation for adjustment
1. Receive the Cross-hatch pattern signal.
2. The electrical focus adjustment should have been
completed.
3. Deflection Yoke tilt should have been adjusted.
4. Brightness = 50%
5. Contrast = 60% to 70%
6. Short the 2 pin sub-miniature connector on the
CRT P.W.B. TS, to produce only the color being
adjusted and adjust one at a time. (The adjustment order of R, G and B is just an example.)
7. (See Figure below) Loosen the fixing screw on
the lens assembly so that the lens cylinder can be
turned. (Be careful not to loosen the screw too
much, as this may cause movement of the lens
cylinder when tightening.)
8. Rotate the cylinder back and forth to obtain the

best focus point, while observing the Cross-Hatch.
(Observe the center of the screen).
Hint: Located just below the screen are the two
wooden panels. Remove the panels to allow
access to the focus rings on the Lenses.
9. After completing optical focus, tighten the fixing
screws for each lens.
10. When adjusting the Green Optical focus, be very
careful. Green is the most dominant of the color
guns and any error will be easily seen.
11. Repeat Electrical Focus if necessary.
STATIC FOCUS ADJUSTMENT
1. The lens focus should be finished.
2. Set video conditions to Contrast to MAX and
birightness to 50%.
3. Receive the cross-hatch pattern signal.
4. Apply covers to the lenses of colors other than
the color to be adjusted and project a single
color.
1. Red (R), Green (G) and Blue (B) static focus
adjustment. Vary the static focus VR(focus pack
UFPK) and make the center of the cross-hatch
pattern clearest.
2. Observe the corners of the picture and check that
the focus does not get conspicuously worse.
21
CONVERGENCE
P7T@SWDIBQPDIUTPAUC@
8PSI@SPAUC@QD8UVS@
6FUHHQ 95
P7T@SWDIBQPDIUT
*
)RFXV 95
)2&86 3$&.
BLUE DEFOCUS ADJUSTMENT

WHITE BALANCE ADJUSTMENT

1. Screen adjustment
1. Optical and electrical focus adjustment should

have been completed.
3. Low brightness balance
2. The convergence adjustment should have been

completed.
3. Set Video conditions to factory reset.
1. Input a Crosshatch Signal to VIDEO input.
2. Short-circuit 2P sub-mini connectors on the red
and green CPT P.W.B.s to display only the blue
beam.
3. Turn the B Focus VR(Focus Pack) fully clockwise.
4. Adjust BLUE defocus according to the following
specifications. 1mm on each side equaling 2mm
total
See figure Below.
Blue Defocus Sticking Out
Center of Blue crosshatch line
22
2. High brightness white balance
Screen Adjustment VRs

Red: on Focus Pack
Green: on Focus Pack
Blue: on Focus Pack
Drive Adjustment VRs

Red:
R873 on CPT P.W.B.
Green: R842 on CPT P.W.B.
Adjustment VRs:
Screen adjustment VRs on Focus Block
Drive adjustment VRs on CRT P.W.B.
Red Drive = R829R
Green Drive = R879G
Preparation for adjustment
1. Start adjustment 20 minutes or more after the
power is turned on.
2. Turn the brightness and black level OSD to
minimum by remote control.
3. Receive a tuner signal, (any channel, B/W would
be best).
4. Set the drive adjustment VRs (Red R829R and
Green R879G) to their mechanical centers.
1. Go to I2C ADJ. Mode. (With power ON, press
DTV/SAT and Cursor Down buttons at the
same time. Service Menu is displayed.)
2. Choose SERVICE item Number [2] of I2C
ADJ. Mode. (Select ON by Cursor Right and
the Vertical will collapses).
3. Gradually turn the screen adjustment VRs (red,
green, blue) clockwise and set them where the
red, green and blue lines are equal and just
barely visible.
CONVERGENCE
sure that the other conditions are center.
Directly observe the screen by eye without
using a mirror.
Fade to black
4. Return Service item on I2C ADJ to Off by

Cursor Right. Number [2].
Adjust the Sub Brightness Number [1]
SUBBRT using I2C Bus alignment procedure so
only the slightest white portions of the raster can
be seen.
5. Input a gray scale signal into any Video input
and select that input using the INPUT button on
the remote or front control panel.
6. Turn the Brightness and Contrast OSD all the
way up.
7. Make the whites as white as possible using the
drive adjustment VRs (Red R829 and Green
R879).
8. Set the Brightness and Contrast to minimum.
(10800 Kelvin)
9. Adjust the low brightness areas to black and
white, using screen adjustment VRs (red, green,
blue).
10. Check the high brightness whites again. If not
OK, repeat steps 6 through 9.
11. Press the MENU key on remote to Exit
Service Menu.
2. Then adjust Sub Brightness using 34 buttons to

increase or decrease the value, according to
figure. (Visually adjust).
18 HORIZONTAL POSITION (FINE)

Adjustment Preparation:
1. Video Control: Brightness 90%, Contrast Max.
PROGRESSIVE MODE:
1. Receive any NTSC crosshatch signal.
2. Screen Format is PROGRESSIVE
3. Enter the I2C Bus alignment menu and select Item
[12] HPOSI
4. Adjust the data so that the Left and Right hand
side are equal.
5. Press the MENU button to exit from the Service Menu.
HD Mode Adjustment:
1. Receive any 2.14H 33.75kHZ signal.
2. Display Format is HD mode.
3. Enter the I2C Bus alignment menu and select Item
[12] HPOSI
4. Adjust the data using the left and right cursor keys
and balance the Left and Right hand side.
5. Press the MENU button to exit from the Service Menu.
3. After adjustment, press MENU button to exit

VIDEO CHROMA ADJUST mode. (Data is
stored in memory).
DIGITAL CONVERGENCE ADJUSTMENT

NOTE: When selecting SUB-BRIGHTNESS

mode, the microprocessor sets the CONTRAST
and COLOR to MIN. automatically, but make
2. Set controls to factory preset.
SUB BRIGHTNESS ADJUSTMENT

1. Start adjustment 20 minutes or more after the
power is turned ON. Receive the color bar
signal.
2. Set the contrast and color controls to minimum.
1. Go to Sub Brightness adjustement in VIDEO
CHROMA ADJUST mode (press Source and
Power button on Control panel at the same time),
using 56 buttons and then 4 button.
1. Receive an RF or video signal.

3. Install jig screen on the set.
23
CONVERGENCE
4. Note the center of the video pattern displayed.
This is necessary to match dotted lines (adjustment point viewed) and actual point that is
adjusted and displayed by the video signal.
Press the MENU button to see all colors if the

center cross is other than White.
5. Press the service only switch (on POWER/

DEFLECTION PWB). The pattern displayed is
now the digital convergence mode.
6. When performing a complete digital convergence
adjustment CLEAR DATA in RAM. See 2.6 (1)(7).
7. To clear data turn TV set off. Press and hold the
service switch and then press POWER on.
$'-8670(17 32,17
NOTE: If only minor adjustments to convergence are needed, the jig screen is not necessary. Use digital data stored in memory and
one color as a reference(red,green or blue).
DO NOT CLEAR DATA and WRITE to
ROM memory.
Advanced convergence Adjustment Procedure
WARNING: Advanced Convergence Adjustment
Procedure is to be performed only when
replacement of the Small Signal Main
Module or one or more the the CRTs is
replaced.
RASTER CENTERING
1. Press the service button SKO1 to enter the
Convergence setup mode.
2. Press the FREEZE button to enter the Raster
Phase Adjustment Mode. Two additional lines
appear, one near the top, and one near the bottom
of the screen.
3. Press the Cursor Keys to match the selected color

to the green at the geometric center of the screen.
4. Press the RECALL, 0, or SOURCE buttons to
select the next color to be adjusted.
0= Red / Green (Yellow)
SOURCE= Green / Blue (Cyan)
DISPLAY= Green Only
5. Press Freeze button to exit the Raster Phase Mode.
(The two lines disappear)
6. Press SKO1 to exit Convergence Service Mode.
CONVERGENCE 3X3
Green 3x3 Mode Alignment
1. Start with power off, press the service button SKO1
and hold, then press the front panel POWER button
at the same time. Set should come on with misaligned convergence.
Note: Mis-aligned convergence will appear, DO
NOT ACTIVATE ROM WRITE (MOVE
button twice). If you do so, you will save this
un-adjusted convergence data.
2. Press DISPLAY button 5 times to access 3x3
Mode.
3. Press the MENU key to project the RED +
GREEN cross- hatch colors only. Then press
DISPLAY to project the GREEN only.
4. Use the 2,4,5, and 6 keys (up, left, down, and right,
respectively) to select the adjustment point. Start
at center adjustment point, then move to top and
bottom, then left and right, and finally the corners.
$
G -On ly S creen
Thvt6qwrQv
"
GphvDrrpvs
7yvxvt8
24
&
'
CONVERGENCE
5. Press the CURSOR KEYS at the selected
adjustment point to match the GREEN horizontal
and vertical lines to the Screen Jig lines.
(Call Zenith Parts @ 1-800-3-ZENITH to order
the Screen Jig)
Gvrrvphyyhyvtrqhur
6qwrQv
Red and Blue 3x3 Mode Alignment

6. Press the 0 key to project the RED + GREEN
internal cross-hatch colors.
8iyvx
ryrprqpy
Internal cross-hatch is Yellow when the Red and

Green lines match, and Cyan when the Blue and
Green Match
adjustment point to match the RED horizontal/
vertical lines to the Green cross-hatch lines.
8. Press the SOURCE key to select the BLUE +
GREEN cross-hatch colors. Perform step 7 for
the BLUE.
9. Press the MENU button to display all 3 colors.
10. In order to Save settings (WRITE to ROM),
press the MOVE key 2 times. When the data is
stored Green dot will appear on the screen. Press
MOVE once to continue with 7x5 adjustment
mode.
CONVERGENCE 7X5
Green 7X5 Mode Alignment
1. Press the 0 button 5 times to enter the 7X5
Adjustment Mode.
2. Press the MENU button and then the DISPLAY
button again to project the Green color only.
G -On ly Screen
Red 7X5 Mode Alignment
5. Press the 0 key to select the RED + GREEN
internal cross-hatch signal.
6. Repeat steps 3 and 4 for the Red 7X5 adjustment.
Blue 7X5 Mode Alignment
GREEN colors.
8. Repeat steps 3 and 4 for the Blue 7X5 mode
adjustments.
9. In order to Save settings (WRITE to ROM), press
the MOVE key 2 times. When the data is stored
Green dot will appear on the screen. Press MOVE
once to continue with 13x9 adjustment mode.
Srq6yvtr
Yellow Cross-hatch
7yr6yvtr
M agenta Cross-hatch
CONVERGENCE 13X9
Green 13X9 Mode Alignment
1. Press the SOURCE button 5 times to enter the
13X9 Mode.
2. Press the MENU button and then the DISPLAY
button again to project the GREEN only.
25
CONVERGENCE
Red 13X9 Mode Alignment

5. Press the 0 key to select the RED + GREEN
internal cross-hatch signals.
6. Repeat steps 3 and 4 for the Red 13X9 mode
adjustments.
Red Alignment
Yello w Cro ss-hatch
Blue Alignment
M agenta Cross-hatch
Blue 13X9 Mode Alignment

GREEN colors.
8. Repeat steps 3 and 4 for the Blue 13X9 mode
adjustment.
9. In order to Save settings (WRITE to ROM), press
the MOVE key 2 times. When the data is stored
Green dot will appear on the screen. Hit MOVE
to continue.
When complete, press the service mode button SKO1
to exit the Convergence setup mode.
26
CONVERGENCE
DIGITAL CONVERGENCE REMOTE CONTROL
PHASE
AUXILLIARY
BLUE
(13X9 ADJUSTMENT)
CURSOR UP
CURSOR RIGHT
CURSOR LEFT
ROM WRITE
CURSOR DOWN
GREEN
(3X3 ADJUSTMENT)
RED
(7X5 ADJUSTMENT)
ADJUSTMENT
CROSSHATCH /
VIDEO MODE
REMOVE COLOR
INITIALIZE
RASTER
POSITION
ROM READ
MBR3475Z
924-10092
27
CIRCUIT DESCRIPTION
Sub-Power Supply Circuit Description
Figure 1 is a simplified diagram of the main Power Supply used in the ZP94/95 series Projection Television
Chassis. The primary control element of the power supply is I901 (the Switching Regulator IC), in conjunction with switching transformer T901. These two components, along with the supporting circuitry, comprise
a closed loop regulation system. Unlike previous Pulse Width Modulated (PWM) Switch Mode Zenith
power supplies, the regulation system in the this chassis utilizes Frequency Control Modulation with an
operational frequency of 85KHZ to 100KHZ, corresponding to full load and no load conditions, respectively. Primary regulation is provided by Q902, I902 and Q910, regulating the switching frequency at pin (3)
of I901 via pin 1, the regulation input to the IC.
B+ Generation for the Sub Power Supply Driver IC (see figure2)
Vcc for the Driver IC is first generated by the AC input. This voltage is called Start-Up Voltage. I901
requires 21V DC to operate normal. However, it will begin operation at 14.5V DC on pin (4) of I901.
When AC is applied, AC is routed through the main fuse F901 (a 5 Amp fuse), then through the Line filters
L901, 902, 903 and 904 to prevent any internal high frequency radiation for radiating back into the AC
power line. After passing the line filters it arrives at the bridge rectifier D901 where it is converted to Raw
150V DC voltage to be supplied to the power supply switching transformer T901 pin (1). However, one leg
of the AC is routed to a half wave rectifier D902 where it is rectified, routed through R905 and R906 (both
a 5.6K ohm resistor), filtered by C907, clamped by a 30V Zener D904 and made available to pin (4) of
I901 as start up voltage. The Red LED D903 is illuminated by this power supply. When this voltage reaches
14.4Vdc, the internal Regulator of I901 is turned on and begins the operation of I901. When the power
supply begins to operate by turning on and off the internal Switch MOSFET, the Raw 150V DC routed
through T901 (in on pin 1 and out on pin 2), is connected to pin (3) of I901 which is the Drain. The Source
of the internal Switch MOSFET is routed out of pin (2) through three low ohm resistors to hot ground. This
on and off action causes the transformer to saturate building up the magnet field. When the internal Switch
MOSFET turns off, the magnet field collapses and the EMF is coupled over to the secondary windings, as
well as the drive windings. The drive windings at pin (8 and 9) produce a run voltage pulse which is rectified
by D905, filtered by C908 then routed through R908, clamped by D904 and now becomes run voltage
(22V) for I901.
AC
Raw 150V
4
Drain
I901
Switch
Mode
IC
Reg
T901
Switch Mode
Transformer
Q910
Buffer
Q914
SCR
28V
I902
Opti-Coupler
Q902
Buffer
I903
Opti-Coupler
Q905
SCR
Shutdown
Input
<Figure 1>
28
ZP94/95 SERIES CHASSIS STBY POWER SUPPLYCIRCUIT

AC
S902
Relay
17
+29V
D902
D912
G
+29 to
Audio
Circuit
PQU1
S901
AC Relay
T901
Switch Mode
Transformer
4
Vin
Drain
Regulate
SBY+7
PQS2
D927
G
11 +28V
I906
D949
G
Q910
I902
OptiCoupler
OCP
I907
D931
G
Q902
I908
Q901
SW+35
PQS1
Protect
To Main Power
Supply PQD1
S903
Relay
I905
Gnd
D903
R
+35V
SBY+11
PQD2 &
PQS1
SW+5
PQS2
SW+12
PQD2
I903
OptiCoupler
CAS
Q905
Common-Action
Shutdown
Input
29
CIRCUIT DESCRIPTION
<Figure 2>
I901
Switch
Mode
IC
14
CIRCUIT DESCRIPTION
Three primary voltages are developed that are needed to sustain run, maintain regulation, and support the
Shutdown Circuitry. They are Run Voltage generated from pin (8 and 9) of T901, +28V used for regulation,
and STBY +11V, respectively. The STBY represents always on; designating a supply that is active
when the unit is connected to AC power. The Power Supply utilizes a Shutdown circuit that can trigger
Q905 from 16 input sources. (6 of these are not operational in Stand by mode). I903 is activated by Q905,
applying gate voltage to Q901, which grounds out the Vcc at pin (4) of I901, disabling the power supply.
Audio Front 29V Regulator SW+29V Indicated by D912
The Audio Front 29V supply is generated from pin (17) of T901. This output is protected by E992, rectified by D910 and filtered by C918. This supply is routed to the Rear Audio Output IC IC01. This voltage is
what illuminates the Green Visual Trouble Shooting LED, D912.
Audio Rear and Center 29V Regulator SW+29V Indicated by D913
The Audio 29V supply is generated from pin (16) of T901. This output is protected by E993, rectified by
D911 and filtered by C917. This supply is routed to the Rear Audio Output IC IS16 and Center Audio
Output IC IC15. This voltage is what illuminates the Green Visual Trouble Shooting LED, D913.
STBY+11V Regulator I906 Indicated by D949
The STBY+11V supply is generated from pin (11) of T901. This output is rectified by D918 and filtered by
C928. This supply is routed to the Stand By +11 Regulator I906 pin (1). This voltage is what illuminates the
Green Visual Trouble Shooting LED, D949. The use of the power supply creating the SBY+11V supply
eliminates the need for a Stand-By transformer. The following explanation will describe the Turning ON and
OFF of the projection television.
STBY+7V Regulator I905 Indicated by D927
The STBY+7V supply is generated from pin (11) of T901. This output is rectified by D918 and filtered by
C928. This supply is routed to the Stand By +7 Regulator I905 pin (1). This voltage is what illuminates the
Green Visual Trouble Shooting LED, D927.
Power Supply Frequency of Operation during Run
The sub power supply in the ZP94/95 chassis works very similar to the previous models. This power supply
runs at 50% efficiency when the AC is applied with the set OFF. When the Horizontal deflection is in
operation, the power supply frequency fluctuates in accordance to current demands. The normal operational
range for the power supply is between 80 kHz to 100 kHz. The lower the frequency, the higher the current
supplied to the load. During Stand-By, it operates at 200KHz.
Power Supply Operational Frequency during Stand-By:
When the Horizontal deflection is defeated, the power supply no longer has a deflection load. The three
resistors connected to the source of the internal Switch MOSFET inside I901 via pin (2) detect this low
current demand. Pin (1) of I901 is the over current detection pin, however it is also the current demandsensing pin. When the current demand is low due to horizontal defeat, pin (1) will be less than 1.4V and the
internal frequency will switch to 200Khz. This is caused by the Quasi Resonant circuit operation. This
reduction of power supply frequency will move the frequency above the Bell of the power supply transformer and all secondary voltages will reduce to approximately 1/2 of their normal voltage. Due to the fact
that the power supply is still operating at 1/2 voltage output, the Green LEDs used for visual trouble sensing
will reduce in intensity, however they will remain lit, with the exception of the SW+12V and SW+5V
regulator. Which are turned off in Stand By.
30
CIRCUIT DESCRIPTION
Sw+9v and Sw+5v Regulator Operation in Stand-By:
Both of these ICs as well as the STY+11V and the STY+7V regulator ICs are DC to DC converters just
like last year. This is because of the wide range of input voltages from Stand-By to Normal operation of the
Power Supply. The SW+12V regulator (I908) and the SW+5V regulator (I907) are shut off during StandBy mode. Q002 and Q903 accomplish this. When the High for the power On/Off pin (53) of the Microprocessor is inverted by the relay driver Q002, and routed through the PQS1 connector pin (8). This is
detected by Q903, and its collector will go low. This will pull pin (5) of I907 and I908 low, turning off the
two DC to DC converters.
Some Shut-Down Detection Circuits Shut Off During Stand-By:
During Stand-By, all of the secondary voltages are reduced to approximately 50% of their normal voltage,
except the STBY voltages. This could cause a potential problem with the Short Detection circuits for
shutdown. To avoid accidental shut down, Q903 also controls the activity of Q908 and Q909. During
Stand-By, Q903 is turned on. This allows the Base of Q908 to be pulled through D945. This action turns
off Q908. When Q908 is off, it doesnt supply emitter voltage to the collector of Q909. The base of Q909
is connected to 6 Low Detection in-puts, (See the Sub Power Supply Shut Down Circuit explanation and
diagram for further details). When the power supply operates at 50%, the Short Detection circuit could
activate. By turning off Q909, no accidental shut down operation can occur.
ZP94/95 Chassis Has 4 Green and 1 Red LED On Sub Power Supply PWB.
This chassis utilizes 4 Green LEDs in the power supply cold side and a Red LED in the HOT side. The
power supply operates it two different modes, Standby and Projection on mode.
ZP94/95X CHASSIS L.E.D. (VISUAL TROUBLE DETECTION) DIODES
SUB POW ER SUPPLY PW B 4 GREEN L.E.D.s and 1 RED L.E.D.
Stby
+11V
Audio
Ft. 29V
Sw
+5V
Stby +7V
R930
R933
R936
D949
G
D912
G
Start U p
R905
D931
G
D927
G
ALL GREEN L.E.D.s
R906
Run
Osc B +
24.2V
D 903 is a RED L.E.D .

Off = N o I901 B+
B linking = Shutdown
24.2V
R908
I901 D river/
Output IC
R907
100% D ead T ime &
IC B+ D etection
D 903
R
V cc
I903
3
1.9V
1
2
I903 Shutdown
Photocoupler
16 Shut D own
Inputs
Q905
Shutdown
SCR
Q 901
Shutdown
SCR
31
CIRCUIT DESCRIPTION
Standby Mode:
4 Green LEDs and the Red LED are lit in the standby mode with the AC applied and the TV OFF;
D903 Indicating Vcc applied to the Power Supply Driver IC Color RED
Audio Front 29V Regulator SW+29V indicated by D912 Color GREEN
Audio Rear and Center 29V Regulator SW+29V indicated by D913 Color GREEN
STBY+11V Regulator I906 indicated by D949 Color GREEN
STBY+7V Regulator I905 indicated by D927 Color GREEN
Power On Mode:
When the Power is turned ON, the other LED lights and the Red LED remains lit as well;
SW+5V Regulator I907 indicated by D931
LED USAGE:
The Visual LEDs are very useful in Trouble Shooting. Without removing the back cover, some diagnostics
can be made. By observing the operation of the Red and Green LEDs, the technician can determine if the
Sub Power Supply is running or not. The following will examine each LED and how they are lit.
This LED indicates any of four different scenarios,
1. Is there B+ (Vcc) available to the Sub Power Supply Driver IC? LED will be ON
2. Is the B+ (Vcc) available to the Sub Power Supply Driver IC missing? LED will be OFF
3. Is the Start Up Vcc to the Sub Power Supply Driver IC available, but the Run Voltage is not? LED will
be BLINKING.
4. Is the Set in Shut Down? LED will be OFF
As can be see there are two different scenarios that can cause D903 to be off, Missing Start up voltage for
the Driver IC and/or the Sub Power Supply is in Shut Down.
Power Supply Shutdown Explanation
This chassis utilizes I901 as the Osc.\Driver\Switch for the sub power supply, just as the previous chassis
have done. This IC is very similar to the previous versions, however it does differ in frequency, (described
previously) and in Stand-By detection. The Shutdown circuit, cold ground side detection, is routed to I901
via Q905 (the Shutdown SCR). I903 (the Photo Coupler), which isolates the Hot ground from the Cold
ground and couples the Shutdown signal to the Hot Ground side, Q901 the hot ground side SCR and I901
pin (4) (the Vcc pin).
The Power Supply utilizes a Shutdown circuit that can trigger Q905 from 16 input sources. (6 of these are
not operational in Stand by mode). I903 is activated by Q905, applying gate voltage to Q901, which
grounds out the Vcc at pin (4) of I901, disabling the power supply.
All of the Power Supply Shutdown circuitry can be broken down into the following groups;
Voltage Missing Detection
Excessive Current Detection
Voltage Too High Detection
In the following explanation, the Shutdown circuits will be grouped. This will assist the Service Technician
with trouble shooting the Chassis, by understanding these circuits and having the associated circuit routs, the
technician can then Divide and Conquer.
32
CIRCUIT DESCRIPTION
ZP94/95 STBY POWER SUPPLY (Low Voltage) SHUT-DOWN CIRCUIT
D902 R905
R906
T901
D905 8 11 28V
R908
AC
D904
C908
Vin
I901
Power
IC
R960
C907
12
R945
D921
D936 D935
I903
D944
Sw +12V
R909
D933 D932
4
Q901
Sw +5V
R911
3
C910
D941
Stby +11V
R910
D938
Q905
Stby +7V
C947
R198
Sw +2.5V
PQS2
Protect 1
Pin 10
D957
R955
D958
D946
D943
D015
Sw +5V
Sw +9V
Q909
R960
D944
Sw +12V
D014
R959
Sw +5V
D016
Q903
Sw +3.3V
C949
Q908
D945
On/Off
R957
Off
On
Off
On
R014
Stby +3.3V
D032
Stby +5V
PQS2
Protect 2
Pin 11
R958
+28V
D959
D955
D960
D951
Q912
D007
D952
R960
Stby +9V
R969
R968
D954
R967
D953
C956
Stby +7V
D956
Stby +11V
33
CIRCUIT DESCRIPTION
Commonly Used Shutdown Detection Circuits
One very common circuit used in Zenith television products is the B+ Excessive Current Sensing circuit. In
this circuit there is a low ohm resistor in series with the particular power supply, (labeled B+ in the drawing).
The maximum current that is allowable within a particular power supply determines the value of this resistor.
In the case of Figure 1, the value is shown as a 0.47 ohm, however it could be any low ohm value. When
the current demand increases, the voltage drop across the resistor increases. If the voltage drop is sufficient
to reduce the voltage on the base of the transistor, the transistor will conduct, producing a Shutdown signal
that is directed to the appropriate circuit.
Voltage Loss or Excessive Load Detection
The second most common circuit used is the Voltage Loss Detection circuit. This is a very simple circuit that
detects a loss of a particular power supply and supplies a Pull-Down path for the base of a PNP transistor.
This circuit consists of a diode connected by its cathode to a positive B+ power supply. Under normal
conditions, the diode is reversed biases, which keeps the base of Q1 pulled up, forcing it OFF. However, if
there is a short or excessive load on the B+ line, the diode in effect will have a LOW on its cathode, turning
it ON. This will allow a current path for the base bias of Q1, which will turn it ON and generates a Shutdown Signal.
B+ Voltage Too High Detection.
In this circuit, a Zener diode is connected to a voltage divider or in some cases, directly to a B+ power
supply. If the B+ voltage increases, the voltage at the voltage divider or the cathode of the zener diode will
rise. If it gets to a predetermined level, the zener will fire. This action creates a Shutdown Signal.
Negative Voltage Loss Detection.
The purpose of the Negative Voltage Loss detection circuit is to compare the negative voltage with its
counter part positive voltage. If at any time, the negative voltage drops or disappears, the circuit will produce a Shutdown signal. In Figure 5, there are two resistors of equal value. One to the positive voltage,
(shown here as +12V) and one to the negative voltage, shown here as -12V. At their tie point, (neutral
point), the voltage is virtually zero (0) volts. If however, the negative voltage is lost due to an excessive load
or defective negative voltage regulator, the neutral point will go positive. This in turn will cause the zener
diode to fire, creating a Shutdown Signal.
ZP94/95 Shutdown Circuit
There are a total of 16 individual Shutdown inputs. In addition, there are also two Shutdown inputs that are
specifically detected by the main power driver IC, I901 that protect it from excessive current or over
voltage. The four previously described circuits can categorize all of the Shutdown detection circuits.
Voltage Loss Detection
Shorted SW+2.5V on Signal PWB through Protect 1 to (D957) on Sub Power Supply PWB
Shorted SW+9V (D015) on Signal PWB through Protect 1 to (D959) on Sub Power Supply PWB
Shorted SW+3.3V (D016) on Signal PWB through Protect to (D959) on Sub Power Supply PWB
Shorted Stby+3.3V on Signal PWB through Protect 2 to (D959) on Sub Power Supply PWB
Shorted Stby+5V (D032) on Signal PWB through Protect 2 to (D959) on Sub Power Supply PWB
Shorted Stby+9V (D007) on Signal PWB through Protect 2 to (D959) on Sub Power Supply PWB
Shorted Stby+3.3V (D016) on Signal PWB through Protect 2 to (D959) on Sub Power Supply PWB
34
CIRCUIT DESCRIPTION
SW+5V (D943)
SW+12V (D944)
Stby+7V (D955)
Stby+11V (D952)
Negative Voltage Loss Detection
SW-12V Loss Detection (D939, D940)
Not used in the Sub Power Supply.
SW+12V (D935, D936)
SW+5V (D932, D933)
Stby+11V (D941)
Stby+7V (D938)
If any one of these circuits activate the power supply will STOP, and create a Power Supply Shutdown
Condition.
SOME SHUTDOWN CIRCUITS ARE DEFEATED IN STANDBY MODE. (Set Off).
As indicated in the Power On/Off circuit diagram explanation, 6 of the 16 shut down inputs are not active
when the set is in standby.
Shorted SW+2.5V on Signal PWB through Protect 1 to (D957) on Sub Power Supply PWB
Shorted SW+3.3V (D016) on Signal PWB through Protect to (D959) on Sub Power Supply PWB
SW+5V (D943)
SW+12V (D944)
These SW voltage loss-sensing circuits are defeated because the SW (Switched) power supplies are turned
off in standby to prevent erroneous of the shutdown circuit. Q909 supplies the high for shutdown if any of
the voltage loss circuits become activated. Q909 requires emitter voltage to operate. Emitter voltage is
supplied from the emitter of Q908. Q908s base is connected to Q903, which in turn is connected to the
power on/off line. When the set is not on or turned off, the power on/off line goes high. This high is inverted
to a low by Q903 and pulls the cathode of D945 low, removing the base voltage of Q908 turning it OFF.
This removes the emitter voltage from Q909 and this circuit cant function.
SHUT DOWN CIRCUIT:
Shut down occurs when the shutdown SCR Q905 is activated by gate voltage. When Q905 receives gate
voltage of 0.6V, the SCR fires and give a ground path for the emitter of the LED inside I903. The light
produced by turning on this LED turns on the internal photo receiver and generates a high out of pin (3).
This high is routed to the gate of Q901 turning it on. This grounds pin (4) of I901 removing Vcc and the
power supply stops working. The reason for the photo sensor I903 is to isolate hot and cold ground.
35
CIRCUIT DESCRIPTION
TURNING ON THE DEFLECTION POWER SUPPLY: See Figure 5
When the Projection Television is turned on, the Microprocessor outputs a high for Pin (35), which is
inverted by Q002. This low is routed through the connector PQS1 pin (8) on the signal PWB to the Sub
Power Supply PWB. It is then routed to Q903, and its collector will go high. This will pull up pin (5) of
I907 and I908, turning ON the two DC to DC converters. The output of both DC to DC converters I907
and I908, are used by the relay which supplies AC voltage to the Deflection Power Supply on the Power/
Deflection PWB. The output of I907 SW+5V regulator supplies B+ for pin (3) of the relay S901. The
output of I908 SW+12V drives the base of Q911 turning it on and grounding pin (4) of the relay S901. The
relay now provides AC to the bridge rectifier on the Deflection Power Supply.
ZP-94/95 DEFLECTION Vcc PRODUCTION CIRCUIT
SUB POWER PWB
SIGNAL PWB
Turns on I009 SW +9V Reg and
IS13 +5V Reg on Surround PWB
DEFLECTION PWB
PQD2
From I906 Stby +11V Reg.
Q003
Q004
Stby +11V
STBY +11V
Start Up Power
I001
Micro
Processor
Power On/Off
PQS1
QP04
Q002
53
8
Power ON
Driver
(Relay Driver)
Power On by
Remote Control or
Front Power Key Press
1
DP21
Other Power
On/Off Circuits
DP35
DP36
I701
DVcc
SUB DEFLECTION PWB
B+ GENERATION FOR THE DEFLECTION POWER SUPPLY DRIVER IC See Figure 1

Vcc for the Driver IC is first generated by the AC input. This voltage is called Start-Up Voltage. IP01
requires 21V DC to operate normal. However, it will begin operation at 14.5V DC on pin (4) of IP01.
When AC is applied by the relay on the Sub Power Supply R901, AC is routed through the connector
PQD1. Then it arrives at the bridge rectifier DP01 where it is converted to DC voltage. One leg of the AC
is routed to a half wave rectifier DP02 where it is rectified, routed through RP02 and RP03 (both a 5.6K
ohm resistor), filtered by CP05, and made available to pin (4) of IP01 as start up voltage. The Red LED
DP37 is illuminated by this power supply. When this voltage reaches 14.4Vdc, the internal Regulator of
IP01 is turned on and begins the operation of IP01.
36
ZP-94/95 SERIES CHASSIS MAIN DEFLECTION POWER CIRCUIT

DP08
AC
1
PQD1
10
+220V
1
16
D902
220V
Heater
PDC1
IP02 2
3
+8V
Convergence
DCU
Convergence
DCU
B=120V 1
DEF.
DP09
DP03
T901
Switch Mode
Transformer
4
Vin
Drain
I901
Switch
Mode
IC
17
-8V
DP10
13
+120V
B=120V 2
HV
DP11
14
PDC1
-28V
Convergence
Amp
Convergence
AMP
DP12
OCP
15
DP07
Source
DP13
Gnd
IP04
Opti-Coupler
OCP
DP29
2
IP03 1
3
OFF
ON
DP37
R
Protect
PQD2
ON
QP01
OFF
X-Ray
Protect
37
CIRCUIT DESCRIPTION
+28V
CIRCUIT DESCRIPTION
Figure 2 is a simplified diagram of the main Power Supply used in the ZP94/95 series Projection Television
chassis. The primary control element of the power supply is IP01 (the Switching Regulator IC), in conjunction with transformer TP91. These two components, along with the supporting circuitry, comprise a closed
loop regulation system. Unlike previous Pulse Width Modulated (PWM) Switch Mode Zenith power
supplies, the regulation system in the this chassis utilizes Frequency Control Modulation with an operational
frequency of 85KHZ to 100KHZ, corresponding to full load and no load conditions, respectively. Primary
regulation is provided by IP03, IP04 and into IP01, regulating the switching frequency at pin (3) of I901 via
pin 1, the regulation input to the IC. Two primary secondary voltages are developed that are needed to
sustain run and maintain regulation; Run Voltage generated from pin (8 and 9) of TP91, +120V used for
regulation and powering the regulation circuitry.
POWER SUPPLY FREQUENCY OF OPERATION DURING RUN
When the Horizontal deflection is in operation, the power supply frequency fluctuates in accordance to
screen brightness, causing differing demands for High Voltage replacement. The normal operational range
for the power supply is between 80 kHz to 100 kHz. The lower the frequency, the higher the current
supplied to the load. During Stand-By, it operates at 200KHz.
GREEN LED:
120V Deflection B+ DP29
The Deflection B+ 120V supply is generated from pin (13) of TP91. This output is rectified by DP11 and
filtered by CP17. This supply is routed to the Horizontal Drive Circuit and the High Voltage generation
circuit. This voltage is what illuminates the Green Visual Trouble Shooting LED, DP29.
ZP-94/95 CHASSIS L.E.D. (VISUAL TROUBLE DETECTION) DIODES
DEFLECTION PWB 1 GREEN L.E.D.s and 1 RED L.E.D.
Start Up
24.2V
Run
Vcc
Osc B+
DP0
2
RP02
RP03
IP04
4
IP01
Driver/Output
IC
RP28
1
RP29
IP04 Regulator
Photocoupler
DP29
G
RP42
DP37 is a RED L.E.D.
Off = No I901 B+
On = I901 B+ OK
120V Deflection B+
DP37
R
IP03
ALL GREEN
L.E.D.s
IP03
Regulator
POWER SUPPLY SHUTDOWN EXPLANATION

This chassis utilizes IP01 as the Osc.\Driver\Switch for the Deflection power supply, just as the previous
chassis have done. This IC is very similar to the previous versions, however it does differ in Frequency,
(described previously). The Shutdown circuit, (cold ground side detection), is used to turn off the Relay
S901 via the following circuit, QP01 (the Shutdown SCR), Connector PQD2, Q911 the Relay Driver and
the Relay S901. The Power Supply utilizes a Shutdown circuit that can trigger QP01 from 14 input sources.
When any of these inputs cause a high on the gate of QP01, the relay disengages, disabling the deflection
power supply. All of the Power Supply Shutdown circuitry can be broken down into the following groups;
38
CIRCUIT DESCRIPTION
ZP-94/95 DEFLECTION POWER SUPPLY SHUTDOWN DIAGRAM
TP91
DP11
13
Deflection B+ (120V)
Excessive Current Det.
RP17
0.47
CP33
QP02
RP22
DP17
DP15
SW+5V
AC In
2
S12V
Vertical Circuit
Excessive Current Det.
28V
DP16
Q609
QP01
ShutDown
S.C.R.
5
Spot
AC for Def.
Power Supply Killer
Flyback
TH01
On
Off
D615
DH24
5
5CP
DH40
Excessive High
Voltage Det.
Doesnt
go to
CRTs
DH26
DH27
220V Short Det.

DP31
Pin 10
I601
R645
0.68
DP18
PQD2
Q911
PQD1
Deflection B+ (120V)
Excessive Voltage Det.
RP21
S-901
Def. Power
Supply Relay
Deflection B+ 120V
QH07
QP03
DP32
DP22
DP34
DH30
Heater Loss Det.
220V
DP33
SW+8V
QH08
X-RAY
PROTECT
SW+8V Short Det.
Prevents
Protect
Misoperation
DP30
28V
SW+12V
28V Short Det.

D753
DP24
DP29
DP28
DP23
DP28
DP27
D754
Q754
Side Pin Failure

High Det.
D760
RP27
RP31
-M28V
RP30
+28V
-28V Loss Det.
RP26
SW-8V
RP25
Heater from Def. Power Supply.
Goes to CRTs
SW+8V
SW-8V Loss Det.
Heater Too High Det.

D759
Deflection B+ 120V V1
Q777
6
1
7
8
Side Pin
Failure
Low Det.
D757 D756
C769
Deflection Transformer
Inoperative Det.
T752
H.Blk
39
CIRCUIT DESCRIPTION
Voltage Missing Detection
In the following explanation, the Shutdown circuits will be grouped. This will assist the Service Technician
with trouble shooting the Chassis, by understanding these circuits and having the associated circuit routs, the
technician can then Divide and Conquer.
COMMONLY USED SHUTDOWN DETECTION CIRCUITS
EXCESSIVE CURRENT DETECTION (See Figure 1)
One very common circuit used in many Zenith television products is the B+ Excessive Current Sensing
circuit. In this circuit is a low ohm resistor in series with the particular power supply, (labeled B+ in the
drawing). The maximum current allowable within a particular power supply determines the value of this
resistor. In the case of Figure 1, the value is shown as a 0.47 ohm, however it could be any low ohm value.
When the current demand increases, the voltage drop across the resistor increases. If the voltage drop is
sufficient to reduce the voltage on the base of the transistor, the transistor will conduct, producing a Shutdown signal that is directed to the appropriate circuit.
VOLTAGE LOSS OR EXCESSIVE LOAD DETECTION
(See Figure 2)
The second most common circuit used is the Voltage Loss Detection circuit. This is a very simple circuit that
detects a loss of a particular power supply and supplies a Pull-Down path for the base of a PNP transistor.
This circuit consists of a diode connected by its cathode to a positive B+ power supply. Under normal
conditions, the diode is reversed biases, which keeps the base of Q1 pulled up, forcing it OFF. However, if
there is a short or excessive load on the B+ line, the diode in effect will have a LOW on its cathode, turning
it ON. This will allow a current path for the base bias of Q1, which will turn it ON and generates a Shutdown Signal.
B+ VOLTAGE TOO HIGH DETECTION.
In this circuit, a Zener diode is connected to a voltage divider or in some cases, directly to a B+ power
supply. If the B+ voltage increases, the voltage at the voltage divider or the cathode of the zener diode will
rise. If it gets to a predetermined level, the zener will fire. This action creates a Shutdown Signal.
NEGATIVE VOLTAGE LOSS DETECTION.
The purpose of the Negative Voltage Loss detection circuit is to compare the negative voltage with its
counter part positive voltage. If at any time, the negative voltage drops or disappears, the circuit will produce a Shutdown signal. In Figure 5, there are two resistors of equal value. One to the positive voltage,
(shown here as +12V) and one to the negative voltage, (shown here as -12V). At their tie point, (neutral
point), the voltage is virtually zero (0) volts. If however, the negative voltage is lost due to an excessive load
or defective negative voltage regulator, the neutral point will go positive. This in turn will cause the zener
diode to fire, creating a Shutdown Signal.
ZP94/95 SHUTDOWN CIRCUITS FOR THE DEFLECTION POWER SUPPLY
There are a total of 14 individual Shutdown inputs. In addition, there are also two Shutdown inputs that are
specifically detected by the main power driver IC, IP01 that protect it from excessive current or over
voltage. The four previously described circuits can categorize all of the Shutdown detection circuits
40
CIRCUIT DESCRIPTION
VOLTAGE LOSS DETECTION
1. Shorted 220V (DP31 and DP32) Inverted by QP03 then through DP22
2. Shorted SW+8V (DP33) Inverted by QP03 then through DP22
3. Shorted 28V (DP30) Inverted by QP03 then through DP22
4. Shorted Side Pin Cushion Circuit (D760 and Q754) then through DP34
5. Shorted Deflection Transformer or Erroneous (D756 and Q754) then through DP34
6. Heater Loss Detection (DH26, DH27, QH07 and DP34) this voltage does not go to the CRTs.
NEGATIVE VOLTAGE LOSS DETECTION
7. -M28V Loss Detection (DP23, DP24)
8. SW-8V Loss Detection (DP28, DP29)
EXCESSIVE CURRENT DETECTION
9. 120V Deflection Power Supply (RP17, QP02, DP15, DP16 and DP18)
10. 28V Vertical IC I601 Power Supply (R645, Q609, D615, and DP34)
11. Excessive High Voltage Detection (DH31, RH54, RH55 and DH24) Sensed from the Heater Voltage
generated from pin (5) of the Flyback Transformer TH01. Also, (DH42) sends a high command to the
Horizontal Driver IC IH02, to defeat Horizontal Drive Output.
12. Side Pincushion failure generating a High. (D754, and D753).
13. Deflection B+ Too High. (DP17, RP21 and RP22)
14. Heater Voltage from the Deflection Power Supply Too High Detection. (DP27 and DP28)
If any one of these circuits are activated, the power supply will STOP, and create a Power Supply Shutdown Condition.
SHUT DOWN CIRCUIT:
Shut down occurs when the shutdown SCR QP01 is activated by gate voltage. When QP01 receives gate
voltage of 0.6V, the SCR fires and give a ground path for the pin (5) of Connector PQD2 called PROTECT. This low is routed to the Sub Power Supply PWB and is impressed on the base of the Relay Driver
Transistor Q911 turning it off. When Q911 turns Off the Relay S901 will disengage and remove the AC
source from the Deflection Power Supply.
DESCRIPTION OF EACH SHUT DOWN CIRCUIT:
Please use the Commonly Used Shutdown Detection Circuits for the description of how the circuit works.
VOLTAGE LOSS DETECTION
1. Shorted 220V (DP31 and DP32) Inverted by QP03 then through DP22
The cathode of DP31 is connected directly to the 220V line. If it shorts this circuit is activated and pulls the
base of QP03 low. This output high is routed through DP22 to the gate of the Shut down SCR QP01.
2. Shorted SW+8V (DP33) Inverted by QP03 then through DP22
The cathode of DP33 is connected directly to the SW+8V line. If it shorts this circuit is activated and pulls
the base of QP03 low. This output high is routed through DP22 to the gate of the Shut down SCR QP01.
3. Shorted 28V (DP30) Inverted by QP03 then through DP22
41
CIRCUIT DESCRIPTION
The cathode of DP30 is connected directly to the 28V line. If it shorts this circuit is activated and pulls the
base of QP03 low. This output high is routed through DP22 to the gate of the Shut down SCR QP01.
4. Shorted Side Pin Cushion Circuit (D760 and Q754) then through DP34
The Side Pin Cushion circuit is comprised of I651, Q652 through Q657 If a problem occurred in this circuit
that creates a Low on the cathode of D760, the low will be routed to the base of Q754, turning it Off. This
output high is routed through DP34 to the gate of the Shut down SCR QP01.
5. Shorted Deflection Transformer or Erroneous (D756 and Q754) then through DP34
The Deflection circuit generates the actual Drive signal used in the High Voltage section. If a problem occurs
in this circuit, the CRTs could be damaged or burnt. D757 is connected to D759, which is normally rectifying pulses off the Deflection Transformer T753. This rectified voltage is normally sent through D757, D756
to the base of Q754 keeping it on and its collector Low. If the Deflection circuit fails to produce the pulses
for rectification, the base voltage of Q754 disappears and the transistor turns off generating a High on its
collector. This output high is routed through DP34 to the gate of the Shut down SCR QP01.
6. Heater Loss Detection (DH26, DH27, QH07 and DP34) this voltage does not go to the CRTs.
The Flyback Transformer TH01 generates a pulse called Heater. (Note: This does not go to the CRTs as
heater voltage, its used for Excessive High Voltage Detection. If a problem occurs in this circuit, the Excessive High Voltage Detection circuit wouldnt operate. So it would be possible for there to be High Voltage
but the circuit detecting Excessive High Voltage couldnt work. DH26 is connected to DH24, which is
normally rectifying pulses off the Flyback Transformer TH01. This rectified voltage is normally sent through
DH26, DH27 to the base of QH07 keeping it on and its collector Low. If the Heater Pulse fails to produce
the pulses for rectification, the base voltage of Q754 disappears and the transistor turns off generating a
High on its collector. This output high is routed through DH30 to the anode of DP34 to the gate of the Shut
down SCR QP01.
NEGATIVE VOLTAGE LOSS DETECTION
7. -M28V Loss Detection (DP23, DP24)
RP31 (18K ohm) is connected to the negative M28V line and RP30 (22K ohm) is connected to the
positive +29V line. The Cathode of DP23 monitors the neutral point where these two resistors are connected. If the negative voltage disappears, the zener DP23 fires. This high is routed through DP24 to the
gate of the Shut down SCR QP01 and Shut Down occurs.
8. SW-8V Loss Detection (DP28, DP29)
RP26 (3.3K ohm) is connected to the negative SW-8V line and RP25 (3.3K ohm) is connected to the
positive SW+8V line. The Cathode of DP28 monitors the neutral point where these two resistors are
connected. If the negative voltage disappears, the zener DP28 fires. This high is routed through DP29 to the
gate of the Shut down SCR QP01 and Shut Down occurs.
EXCESSIVE CURRENT DETECTION
42
CIRCUIT DESCRIPTION
9. 120V Deflection Power Supply (RP17, QP02, DP15, DP16 and DP18)
If an excessive current condition of the Deflection B+ were detected by RP17, a 0.47 ohm resistor, the
base of QP02 would drop. This would turn on QP02 and the high produced at the collector would fire
zener DP15. This High would be routed through DP16 through DP18 to the gate of the Shut down SCR
QP01 and Shut Down occurs.
10. 28V Vertical IC I601 Power Supply (R645, Q609, D615, and DP34)
If an excessive current condition of the Vertical B+ were detected by R645, a 0.68 ohm resistor, the base of
Q609 would drop. This would turn on Q609 and the high produced at the collector would be routed
through D615 through DP34 to the gate of the Shut down SCR QP01 and Shut Down occurs.
VOLTAGE TOO HIGH DETECTION
11. Excessive High Voltage Detection (DH31, RH54, RH55 and DH24) Sensed from the Heater
Voltage generated from pin (5) of the Flyback Transformer TH01. Also, (DH42) sends a high command to the Horizontal Driver IC IH02, to defeat Horizontal Drive output, the Flyback Transformer TH01
generates a pulse called Heater. (Note: This does not go to the CRTs as heater voltage, it is used for Excessive High Voltage Detection). If this voltage goes too high indicating an excessive High Voltage condition, the
voltage divider comprised of RH54 and RH55 would impress a high on the cathode of DH31. This high is
routed through DH34 to the gate of the Shut down SCR QP01 and a Shut Down occurs.
12. Side Pincushion failure generating a High. (D754, and D753)
The Side Pin Cushion circuit is comprised of I651, Q652 through Q657 If a problem occurred in this circuit
that creates a High on the cathode of D754, the High will be routed through D753 to the gate of the Shut
Down SCR QP01.
13. Deflection B+ Too High. (DP17, RP21 and RP22
RP21 and RP22 form a voltage divider. The top side of RP22 is monitored by DP17. If this voltage goes
too high, the zener DP17 will fire. This high is routed through DP18 to the gate of the Shut down SCR
QP01 and Shut Down occurs.
14. Heater Voltage from the Deflection Power Supply Too High Detection. (DP27 and DP28)
The Heater Voltage for the CRTs filament is generated in the Deflection Power Supply. This voltage is
monitored by DP27. If this voltage goes too high, the zener DP27 will fire. This high is routed through DP28
to the gate of the Shut down SCR QP01 and Shut Down occurs.
43
CIRCUIT DESCRIPTION
Use the ZP94/95 Series Power On and Off Diagram along with this explanation:
The power supply in the ZP94/95 chassis works very similar to the previous models, with only a few
exceptions. This power supply runs all the time when the AC is applied. The use of the power supply to
create Stand by Voltage supplies eliminates the need for a Stand-By transformer. The following explanation
will describe the Turning ON and OFF of the projection television. The Microprocessor I001 generates the
ON-OFF control signal from pin (53). The logic states of this pin are High = On and Low = Off. When the
set is turned On, the high from pin (53) is routed to the Relay Driver Q002 base. This turns on Q002 and
its collector goes low.
This On/Off from the Relay Driver Q002 will perform the following:
Turns on the SW5+V I907 and SW+12V I908 regulators. Which do not operated in Standby.
Turns on the Shut down Power Shorted detection circuit, Q908 and Q909.
Turns on the Horizontal Vcc supply to the Horizontal and Vertical drive IC, I701.
Turns on the Relay providing AC to the Deflection Power Supply on the Power/Deflection PWB.
HORIZONTAL B+ ON AND OFF CIRCUIT: (See Figure 1)
When the power supply goes into Stand-By mode (TV Off), the Horizontal Drive signal for deflection is
shut off. Q002 and QP04 accomplish this. The Low out produced from the Power On/Off pin 53 of the
Microprocessor routed through Q002 located on the Signal PWB. This low is sent through the PQS1
connector, pin (8) to the Sub Power Supply PWB and then through PQD2 connector, pin (1) and sent to
the Deflection PWB. This Low is detected by the base of QP04 turning it ON and the SBY +11V connected to its emitter is made available at its collector. The collector is connected to the Deflection B+ pin
(22) of the Horizontal and Vertical Drive IC, I701 via pin (8). This action stops I701 from producing a
horizontal deflection drive signal.
ZP94/95 SERIES "POWER ON & OFF" DIAGRAM

I001
Microprocessor
Power
On/Off
53
SBY11V
QP04
PQS1
DP36
3
RP36
Q002
ON = Hi
OFF
= Lo
Power
On/Off
ON = Hi
OFF = Lo
Signal PWB
I701
H Drive IC
PQD2
RP37
Def.
B+
8
HVcc
L701
DP21
Sub Power
Supply PWB
DP35
RP38
Hoz.
Out
15
CP44
C964
C544
Deflection PWB
44
ZP-94/95 SERIES "POWER ON & OFF" DIAGRAM
I001
Microprocessor
VDD
5V
61
Power
On/Off
53 PQS1
Reset
54
+28V
3.3V
3.3V
D928
Q002
Q903
Off
On
2.5V
5
D945
D948
R053
R951
R957
I907
SW+5V
Reg IC
I908
SW+12V
Reg IC
SW+5V
3
SW+12V
R950
I006
Reset
R958
Q909
To Gate of Q914
(Shutdown SCR)
Q908
R949
3.3V
C949
R959
I906
STY+11V
2
L004
Q026
D946
+28V
Sub Power PWB

6 Shutdown
Inputs,
Active Low
D947
STBY+5V
C074
3.9V
PQD2
R029
QP04
SBY11V
I701
H Drive IC
Hoz. Out
Def.B+
8
15
DP35
D034
DP36
RP36
RP38
C075
D035
Signal PWB
DP21
Power On/Off
3
I008
STBY
+5V
PQS2
Off
HVcc
RP37
1
L701
On
CP44
2
3
SYB
+7V
I905
STY+7V
C544
C964
Power/Deflection PWB
Signal Sub PWB
45
CIRCUIT DESCRIPTION
C948
C032
CIRCUIT DESCRIPTION
ZP94/95 MICROPROCESSOR DESCRIPTION EXPLANATION:
The ZP94/95 Microprocessor is a Duel In-Line 64 pin chip. The Microprocessor is responsible for many
different operations related to the control of the Projection Television. Some of these controls are automatic
and some require customer intervention, either by the Remote control or front panel keys and/or by the
customers menu. When power is first applied, the Microprocessor receives its B+ voltage. This Microprocessor utilizes a 3.3V power supply instead of the usual 5V as in past chassis. As the 3.3V is rising, the
Reset IC (I006) holds the reset pin (54) low long enough for the main B+ to stabilize. After stabilization, the
Reset IC brings pin (54) high. During the Reset condition, the Microprocessor is initiated into is start up
state. At the same time this is happening, the Microprocessor Oscillator is generating the Microprocessors
internal clock. The Crystal responsible for this is X001 (4Mhz) connected to pins (52 and 53). When
trouble shooting a Microprocessor for problems, its very important to remember the sequence described
above. Always examine the process before looking for any other problem area.
The order is;
1. Vcc Applies. Generated from the Always Voltage (STY+7V I905) on the Sub Power Supply then
through a 3.3V regulator (STBY +5V I008 on the Signal PWB).
2. Ground is available. Look for open traces, etc.
3. The Reset circuit is working (I006). It should hold the Reset pin on the Microprocessor low until main
Vcc becomes stabled.
4. The Oscillator is running. Be careful here because a low resistance probe will kill the Oscillator or give a
false reading.
After checking for the preliminary functionality of the circuits described above, then check for active clock
pulses leaving data port pins. (See the Data Communications Circuit Diagram for details). If some other IC
is grounding the data or clock pins, the Microprocessor will not work. This usually requires a pull-up
resistor. If no pull-up resistor is noted in the schematic, then the responsibility for pull-up lies within the
Microprocessor. Unloading the pin is a good way to investigate for pull-up. When Remote Control, Front
Keys or some internal process enters a command, the Microprocessor runs a set of predetermined routines.
These routines are hard programmed into the Microprocessor RAM and are unchangeable. There are
routine instructions that can be modified by either the customer or the Servicer and involve pre-programmed
routines and variables entered by the customer or technician. These would include such things as changing
the channel, audio set-ups, on/off timer, auto-link, etc...
CONTROL OF THE PROJECTION TELEVISION:
Receiving Inferred Remote Control Commands
Receiving Key Input Commands
Controlling the On and Off state of the High Voltage Power Supply
Interaction between the Customers Menu and Chassis controls
Outputting of On Screen Display information
Interaction between the Service Menu and Chassis I 2 C Data Bus controls
Automatically Scanning the Tuners searching for Active Channels when requested by the Customer from
the Menu
Automatically Controlling the Tuners when Channels are changed for the Main and PinP Tuners
Automatically Controlling the Video Processor (Rainforest IC) when directed by the Customer
Controlling the Audio Circuits when directed by the Customer.
Controlling Switching between Tuner (Main), AVX 1, 2, 3 and 4, Component 1, 2, and Tuner 2 (AUX) or
In From Converter.
The following section will explain the controls listed above.
46
CIRCUIT DESCRIPTION
ZP-94/95 SYSTEM CONTROL PORT DESCRIPTION
I001
VDD (3.3V)
61
CLOCK
U201
Dimmer
DATA
POO
41
MAIN
TUNER
VSS (Gnd)
29
DSP Reset
19
AC In
23
OSD X1
48
OSD Xo
47
OSD B
FE Enable1 44
Main/Sub AFC
ENABLE
AFC
FE Enable2 43
DATA
U202
CLOCK
PinP
TUNER
ENABLE
Key In
AFC
39
Clock
20
Clock
OSD R
37
Data
21
Data
OSD G
38
FC Enable
46
Enable
OSD B
39
OSD Blk
51
Power On/Off
53
VRef
36
B+Fail
Half Tone
40
DSP SI 17
DSP Err Mute 18
I014
Level
Shift
U205
Flex Conv & PinP
Unit
DSP SI
DSP Err
Audio DSP
AC3/ProLogic
DSP Sck
DSP Sck 16
DSPSS
DSPSS 15
DSPRST
DSPRST 19
DSP S0 13
EEPROM
DAC 1
SCL
DSP Busy 12
SDA
SCL2 60
SCL
SCL
SDA2 59
SDA
I002
I003
SDA
SCL
SO Select 50
DAC 2
SCL
SCL1
SDA
SDA1
I004
Rear Audio
Control
IS11
SDA
57
SDA3
SCL
56
SCL3
I701
SCL
35
28
Sub CCD
30
OSC In
62
OSC Out
63
BVCOI 42
Rainforest
IC
IS03
Front Audio
Control
IS05
Front EQ
IS10
Cent EQ
IS08
Cent/LFE/PinP
Audio Control
IS01
DAC3
SCL
AVDD 3.3V 33
SCL
Test 52
SDA
SCL
CLL 32
SDA
Sub FV Det 11
SCL
Main FV Det 10
VSS (Gnd)
64
IRIn
Deflection
IX01
SDA
SDA
Main CCD
3D/YC
Comb Filter
SDA
Reset 54
IRef
U204
SDA
Comp 34
SCL
G+Reset
VRefHS
27
CLH
26
Ft. Panel Control Keys
N/C
SDA
VMute 45
AD
KeyIn
VSync 55
47
CIRCUIT DESCRIPTION
Pin
1
2
ID
IRIN
SDA1
SCL1
Dimmer
5
6
AD Key In
Main/Sub
AFC
Key In
7
8
9
10
Function
Receives Remote Control Inferred pulses.
Serial Data Sent and Received from the EEPROM, A/V Selector, DAC1, DAC2.
Function of I2C.
Serial Clock Synchronization Sent to the EEPROM, A/V Selector, DAC1,
DAC2. Function of I2C.
Receives DC voltage generated from the Photo Receiver on the Front Panel
monitoring Room Light. For AI
Receives Level Shifted DC voltage from Front Panel Key presses.
Receives the Main Tuner AFC or Sub AFC DC Voltage switched by I005. Used
during channel change.
When the Power switch is pressed, Clock data from pin 21 is routed through
Q014 back to this pin. Power is toggled On or Off.
Not Used
Not Used
Receives Composite 1 V Sync from I015 pin 4 for OSD Positioning.
Not Used
Not Used
Main FV
Det
11 Sub FV Det Receives Composite 2 V Sync from I016 pin 4 for OSD Positioning.
12 DSP Busy Receives the Busy command from the Digital Surround Processor on the
Surround PWB.
13 DSP SO Control command to the DSP Unit for controlling Modes.
14 DSP Dir Receives Digital Surround Processor Error information from the DSP unit on the
Surround PWB.
15 DSP SS Control command to the DSP Unit for controlling Modes.
16 DSP SCK Digital Surround Processor Clock.
17 DSP S1 Control command to the DSP Unit for controlling Modes.
18 DSP ERR Mutes Audio when a DSP Dir input is detected. (DSP Error).
Mute
19 DSP Reset Resets the DSP module on the Surround PWB
20
Clock
Sent to the Level Shift I014 then to both Tuners and the Flex Converter as a
timing signal. Also see pin 7.
21
Data
Sent to the Level Shift I014 then to both Tuners and the Flex Converter to
control each unit.
22 Comp 1/2 Either Component One or Two Horizontal Input from I005 through Q046. Used
FH Det for OSD Display. And Auto Link
23
AC In
Receives Timing pulses for advancing the Clock. Received from the Smitt Amp
Q008 and Q009
24 Main/Sub Station Detection. Used during Auto Programming and when channels are
SD Det changed to open AFC Loop. Switched by I005.
25
VDD
Stby +3.3V generated by 0029. Main Microprocessor B+.
26
CHL
Clamp level High
27 VRefFHS Use as a reference signal within the Microprocessor High Frequencies.
28
CVBS0 Composite Sync used for Closed Caption Detection for the Main Tuner.
29
VSS
Ground
30
CVBS1 Not Used. Composite Sync used for Closed Caption Detection for the PinP
Tuner.
31 VREFLS Reference Signal used within the Microprocessor Low Frequencies.
32
CLL
Internal function of the Microprocessor.
Active
Data
Data
Data
DC
DC
DC
Data
N/A
N/A
Sync
Sync
DC
Data
Data
Data
Data
Data
DC High
DC High
Data
Data
DC
60Hz.
Sync
DC
DC
DC
Sync
N/A
N/A
N/A
N/A
48
CIRCUIT DESCRIPTION
Pin
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
ID
AVDD
COMP
IREF
VREF
OSD R
OSD G
OSD B
HALF
TONE
PDO
BVC0I
FE
ENABLE 2
FE
ENABLE 1
V.MUTE
Function
Stby +3.3V generated by 0029.
Outputs Red characters for the Service Menu.
Outputs Green characters for the Service Menu.
Outputs Blue characters for the Service Menu.
Controls the Translucency of the Main Menu Background. Low = Clear, Mid =
Transparent, Hi = Gray.
Front End Enable. Enables the reception of data from the Microprocessor by the
PinP Tuner.
Front End Enable. Enables the reception of data from the Microprocessor by the
Main Tuner.
Mutes Audio and Video through Q008 and Q010 to Sub Video and Surround
PWB during channel change. High = Mute
FC
Flex Converter Enable Line. Allows the Flex Converter to receive commands
ENABLE from the Microprocessor.
OSD X0 Reference Frequency for OSD. Determines the OSD Size.
OSD X1 Reference Frequency for OSD. Determines the OSD Size.
H SYNC Receives Horizontal Blanking pulses 3.3Vp/p for OSD positioning. Generated
from H Blk through Q006
SD
Sent through Q030 to I015 for setting the internal selection switches. Hi = Main,
SELECT Lo = Sub
OSD BLK Outputs a pulse slight wider and in time with the OSD characters to clean up
video where character will be displayed.
TEST
Use by the factory for internal test of the Microprocessor and to place in a
specific set of criteria.
Power
This output goes high when the Power Button is pressed for ON and Low for Off.
ON/OFF
RESET Low when Power first applied then rises to a high of 3.3V. Received from I006.
Resets the Microprocessor.
VSYNC Receives Vertical Blanking pulses 3.3Vp/p for OSD positioning. Generated from
V Blk through Q005
P BLK
Sent to the Rainforest IC IX01. Used to Mute the Video during Channel change,
Child Lock, AVX selected with no input. Hi = Mute
SDA3
Serial Data Sent to the Rear Audio Output IC IS11 on Surround PWB. Controls
Volume, Bass, Treble, and Bal. Function of I2C.
SCL3
Serial Clock Sent to the Rear Audio Output IC IS11 on Surround PWB. Used for
Timing of Data. Function of I2C.
SDA2
Serial Data Sent to U204, I701, IX01, IS03, IS05, IS10, IS08, IS01, I201 and
I403. Function of I2C.
SCL2
Serial Clock Sent to U204, I701, IX01, IS03, IS05, IS10, IS08, IS01, I201 and
I403. Function of I2C.
VDD
Stby +3.3V generated by 0029. Main Microprocessor B+.
OSC In OSC In (4MHz)
Active
DC
DC
DC
DC
Data
Data
Data
Data
DC
DC
Data
Data
DC
Data
Data
Data
H Blk
DC
Data
DC
DC
DC
Data
DC
Data
Data
Data
Data
DC
Data
49
CIRCUIT DESCRIPTION
Receiving Inferred Remote Control Commands:
Whenever the Customer utilizes the Infer-red Remote, the IR receiver will detect these 38Khz inferred pulse
train and amplify them. These pulses are delivered to the Microprocessor at Pin (1). The Microprocessor
decodes this data train and sets off the internal routine related to the command.
There is a time when the Microprocessor ignores the remote commands and that is when the Digital Convergence Unit, (DCU here after) is in operation. The Microprocessor receives a BUSY notification that the
DCU is in operation and simply doesnt respond to remote commands. (See the Digital Convergence
Interconnect Diagram and explanation for complete details.) The BUSY signal is generated from the DCU
at pin (10). Then out pin (1) of the PSD1 connector to pin (10) of I004 DAC2. I004 sends the information
via SCL1 and SDA1 lines from Pin (14 and 15) to the Microprocessor pins (2 and 3).
Receiving Key Input Commands:
The front panel function keys are detected by the Microprocessor via R2 ladder style circuit. In other
words, inside the microprocessor is a group of comparators. The function keys are strung together and each
one has a different resistor value to ground. When the key is pressed, the comparators detect the change is
resistance to ground at pin (20) Clock and convert the related DC value into data the Microprocessor can
understand.
The following shows the resistor value to ground from pin (20) of the Microprocessor, though pin (7) of the
PFS connector to the individual keys.
Channel Up = ground
Channel Down = 1K
Volume Up = 1K + 1.5K or 2.5K
Volume Down = 1K + 1.5K + 2.7K or 5.2K
AVX = 1K + 1.5K + 2.7K + 4.7K or 9.9K
Menu = 1K + 1.5K + 2.7K + 4.7K + 10+ or 19.9K
Controlling the On and Off state of the High Voltage Power Supply.
The Power On/Off function switch has STBY+3.3V applied for the Sub Power Supply, via pin (8) of the
PFS connector through a 1K resistor. The output of the Power On/Off switch is sent through pin (6) of the
PFS to Q014. Q014 is turned on at this time and connected to its Emitter is the Data from the Microprocessor pin (21). The Data is routed from Q014s Collector to Key in pin (10) of the Microprocessor. When
the Microprocessor receives this data at pin (10), it knows to turn on or off the television. This function is
performed by and output from pin (53), which controls Q002. This output from this pin is High when the set
is On and Low when the set is Off.
(For more details related to Power On/Off, see the Power On & Off Circuit Diagram Explanation and
Diagram).
Interaction between the Customers Menu and Chassis controls.
When the Customer accesses the Main Menu, selections can be made by scrolling up and down or left to
right. Each item selected will activate a set of instructions within the Microprocessor and determine the
output state of the related pins.
Outputting On Screen Display information
When its necessary, the Microprocessor generates 1uSec pulses from pins (37 Red, 38 Green and 39
Blue) that are sent to the Rainforest IC (IX01) pins (37 Blue, 38 Green and 39 Red) as OSD signals. When
the OSD signals are high, they turn on the output of the Red or Green or Blue amps inside the Rainforest IC
and output a pulse to the CRTs to generate that particular character in the particular color.
50
ZP94/95 CHASSIS MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT DIAGRAM

PYC1
Sweep Control
PSD2
IOO1
16
I701
SDA2
17
SCL2
SCL2
SDA2
Deflection PWB
SDA2
59
SCL2
60
U204
3DY/C
34
SDA2
33
SCL2
I201
Main Video
Chroma
U202
Enable Tuner 2
17 Pinp
FEENABLE2 43
Data
Clock
Data
Clock
26 SCL2
27 SDA2
IX01
Rainforest
RGB
Processor
PSU1
PST1
U201
Enable Tuner 1
FEENABLE1 44
6 Main
2H Video PWB
PSZ2
34
33
16
34
15
I403
Sub
SCL2 Video
Chroma
SDA2
SDA2
SCL2
SDA
1 I401
33 SCL1 A/V Select
SDA
2
5 SCL2
4
SDA2
SCL2
SDA1
SCL1
SDA1
I003
DAC1SCL1
SDA1
IOO2
SCL1 EEPROM
SDA2
SCL2
58
SDA3
57
SCL3
3
SDA3 4
IS11
Rear
Audio Control
5
4
PFC1
Clock
20
18
Data
21
17
FCENAble
46
16
DSPSS
I014
3.3V -> 5V
Level Shift
15
DSPSCK
16
DSPERR Mute
18
13
DSPI
17
12
DSPRST
19
15
14
11
10
FCEN
DSPSS
17
16
IS10
Center
Equalizer
SCL1 I004
SDA1 DAC2
SDA2
SCL3
16
IS05
Front
Equalizer
SCL2
SDA2
Clock
11
Data
12
Enable
U205
FLEX
&
PinP
SCL2
PSU2
DSPSS
DSPSCK
DSPSCK
DSPERR Mute
DSPERR Mute
DSPI
DSPI
DSPRST
DSPRST
51
Signal PWB
4
5
14
15
IS08
Center/LFE/
PinP
Audio Control
IS01
DAC3
PMU1
12
11
13
DSP
Unit
HC4051
Surround PWB
CIRCUIT DESCRIPTION
Terminal PWB
17
IS03
Front
Audio
Control
CIRCUIT DESCRIPTION
Interaction between the Service Menu and Chassis I 2 C Data Bus controls
When it becomes necessary for the Service Technician to adjust the set, the Service Menu must be entered.
This is accomplished with the TV turned off, then by pressing and holding the INPUT Key and then the
POWER SWITCH. The Adjustment Menu will be displayed at this time. With the Service Menu activated,
the Technician moves up and down to the desired adjustment using the Remote control or front panel Up or
Down cursor keys. To make the adjustment, the Technician uses the Remote control or front panel Left and
Right cursor keys to change the data values for the particular adjustment. The Microprocessor controls the
individual IC related to the adjustment using I2C technology. I2C technology allows the Microprocessor to
control and IC using only two pins, (SCL and SDA). The following pins on the Microprocessor and the ICs
that it controls are described in the following table.
PINS
2 SDA1 and 3 SCL1
59 SDA2 and 60 SCL2
57 SDA3 and 58 SCL3
CONTROLLED ICs
I401 AV Selector, I002 EEPROM, I003 DAC 1, I004 DAC 2
U204 3D/YC, I701 Deflection Drive, IX01 Rainforest, IS03 Front
Audio Control, IS05 Front EQ, IS10 Center EQ, IS08 Center/
LFE/PinP Audio Control, IS01 DAC3, I201 1H Main Video, and
I403 H Sub Video.
IS11 Rear Audio Control.
Automatically Scanning the Tuners searching for Active Channels when requested by the Customer from the Menu.
When the Projection is first installed, the active channels must be scanned and memorized in the Channel
Scan List. This list is actually stored within the EEPROM and the Microprocessor uses the information to
Scan up or down. Held within the Microprocessor is the Initial FCC Lookup table. This table gives information related to all the channels frequency, band, and channel number. The frequency is actually a given
value for the Phase Lock Loop circuit within the tuner. Then band is data to tell the band selection circuit in
the tuner where the particular channel is located and the channel number is given to the microprocessor to
indicate what OSD outputs to pro-duce. When the set is first opened, its in what is called Factory Reset
Condition. For the Tuner, this means that the signal source is AIR, and channels 2 through 13 are in the
channel scan list. Before the customer runs Auto Program, they must set the signal source to the type they
are using, Air, Cable 1 or Cable 2. After the source is set, the customer then proceeds with Auto Programming. When Auto Programming is initiated, the Microprocessor has a specific program to run. This program
starts by placing the tuner in the lowest channel in the lowest band. That would normally be channel 2. Then
the program instructs the Microprocessor to look for Sync. To do this, the Microprocessor actually need
Horizontal Blanking (H.Blk) at pin (49) which is labeled H.Sync and Video Sync (24) labeled Main/Sub SD
Det. Horizontal Blanking is use as a gate pulse for the coincidence detector. Within the coincidence detector
there is a circuit that monitors the timing of the Sync pulse in relationship to (H.BLK). If the signal being
checked is not in time with (H.Blk) the signal is ignored. However, if the signal being monitored is in coincidence with (H.Blk), the signal is deemed to be true Video Sync and that particular channel is stored as an
active channel in the EEPROM Scan List. Then the Microprocessor sends information to the tuner to move
up one channel and the whole process begins again. This is repeated until every channel is checked. After
completion of the scan, the microprocessor retrieves information from the EEPROM concerning the first
channel in the lowest band that appears in the scan list and directs the tuner to tune to that channel.
52
CIRCUIT DESCRIPTION
Automatically Controlling the Tuners when Channels are changed.
MAIN TUNER:
When channels are changed, the Microprocessor runs another routine. This routine detects the command if
the Remote Control or the Front keys input it. Whether its Scan Up/Down or direct access, and begins to
control the Tuner. First, the Microprocessor output a Mute command to blank the video, then data is sent to
the tuner to move it to the desired channel. After that, the Microprocessor again checks the coincidence
detector for active sync. If active sync is detected, the Microprocessor opens what is called the AFC Loop.
The AFC Loops comprises two cycles trying to lock the tuner to the specific IF frequency of 45.5 Mhz. A
DC voltage is sent from either the Main Tuner U201 pin (10) or the PinP Tuner U202 pin (21) back to the
Microprocessor pin (6). This DC voltage indicates the error between the IF detected and the IF frequency
reference. This error voltage tells the Microprocessor to do one of two things. First, if the error is large, the
Microprocessor changes the Programmable Dividers division rate to a larger or smaller degree to get
closer to the actual IF frequency desired. Second, move the Pulse Swallow division rate to either 1/32 or 1/
33. The Pulse Swallow tuning circuit is a second divider that is on the output from the Prescaler. The main
Prescaler takes the very high frequency output from the tuners mixer circuit which is produced when the
tuners main oscillator is beat against the incoming RF frequency. The Programmable Divider is instructed by
the Microprocessor exactly what division rate to apply to the Beat Frequency generating the IF frequency.
The IF frequency is then sent through the Pulse Swallow circuit which again divides the IF frequency at a
much smaller rate. This allows the IF output frequency to become much more finite and can correct for
much smaller errors between the Phase comparators reference frequency. The error voltage is routed back
to the main internal Oscillator in the front end to correct for Tuning errors.
(See the Microprocessor Data Communications Circuit Diagram Explanation for Details related to Data
Communication for controlling the Main Tuner).
Automatically Controlling the Tuners when Channels are changed.
PinP TUNER:
As far as the internal function of the PinP Tuner, it is the same as the Main Tuner. When the customer
presses the PinP button on the Remote Control, the Microprocessor outputs Clock, Data and Enable
controls to the Flex Converter. The Flex Converter also has the PinP circuit inside. The Clock, Data and
Enable pins on the Microprocessor are pins (20 Clock, 21 Data and 46 FCENABLE) These are routed to
the Level Shift IC, I014 pins (2, 3 and 4). They are output on pins (18, 17 and 16) to the Flex Converter
U205 connector PFC1 and input on pins (10, 11 and 12). The Flex Converters PinP unit is then switched
on and insertion is made into the regular Main Video line. This process controls the position of the PinP
window, the PinP window itself and other different display conditions. When SWAP is pressed on the
remote control, the channel or input that the PinP tuner was on, now becomes the Main Videos source and
the channel or input that the Main signal was on, now becomes the PinP source.
Automatically Controlling the Video Processor (Rainforest IC) when directed by the Customer.
The Rainforest IC has many enhancement circuits built in. These would include the Black Peak Expansion
circuit, the Dynamic Noise Reduction circuit, Time Compression and of course Sharpness, Black Level and
Contrast adjustments as well.
Black Peak Expansion Circuit:
This circuit is utilized to increase the contrast ratio. The standard video signal is 1-Volt Peak to Peak; the
actual video (Y) content is 730mVp/p. The Standard video signal is divided into units called IRE. The units
are equal to 140 total for the 1Vpp signal. Sync occupies 40IRE, which are negative and the Luminance
represents 100 IRE units. Each unit represents 7.1428mVp/p of information. The Black Peak Expansion
53
CIRCUIT DESCRIPTION
circuit monitors the 1/2 way point of luminance, (50 IRE or 357mV) and pulls the signal towards pure black
or the 7.5 IRE level. This increases the distance from Black Peak to White Peak, which is contrast.
Dynamic Noise Reduction Circuit:
This circuit again monitors the area from 50 IRE down and subtracts noise. This circuit is dynamic meaning
that it characteristics change. In other words, the subtraction process is greater near black level that it is
near 50 IRE. The subtraction is 6dB at maximum, meaning that there would be some frequency loss near
black, but the noise, which is seen as white speckles, would be reduced.
Time Compression Circuit:
Any time an analog signal is passed through a capacitor, its high frequencies are reduced. To replace these
high frequencies, Zenith uses Time Compression. This circuit is on the order of Aperture Compensation,
however it differs in the fact that it uses 5 delay lines. The actual signal should look like Figure 2. Figure 3,
however after passing through a capacitive circuit, it looks like Figure 4. After Time Compression takes
place, the beginning rise is advanced. Just before white peak, the signal is delayed. Just before the signal
falls the signal is advanced and just before the signal reaches black peak the signal is delayed. This causes
the signal to appear more like the actual signal and thus restores the high frequencies lost through capacitance.
Sharpness:
During the Time Compression process, switching pulses that are detected at the transition point, (A transition is the point at which the luminance signal goes for black to white or white to black) are used in the
sharpness circuit. This signal is the routed through a sort of variable resistor and according to how much
sharpness the customer has selected, determines how much of the transition signal is added to the original
signal. The greater the sharpness setting, the greater the transition signal added.
Controlling the Audio Circuits when directed by the Customer.
The customer has control over how the set accesses audio information for all of its inputs. The tuner for
example is an integrated type. This not only means that held within the Main Tuner is all the necessary
components for Reception and Video detection. It also has a built in audio and MTS decoder. The Main
Tuner outputs Left Total and Right Total signals. (Left Total and Right Total means that the encoding for
Pro-Logic is held within the individual signal.) The customer can select first, how the Tuner decodes its
audio. Stereo, Mono, or SAP can be selected. The Main Tuner must tell the Microprocessor what signal it
is receiving. The Main Tuner has a ST LED output at pin (19), which tells the Microprocessor it is receiving
MTS Stereo and a SAP LED output at pin (20), which tells the Microprocessor it, is receiving Second
Audio Program. How these are selected by the consumer via the Main Menu determines the output from
the Microprocessor.
ST LED is routed from the Main Tuner at pin (19), through Q204, to the DAC1 I003 pin (10). The DAC1
outputs Clock and Data via pins 15 SCL1 and 14 SDA1 signals to the Microprocessor input on pin 3
SCL1 and pin 2 SDA2. The Microprocessor knows how to switch the tuner decoder circuit by making
judgment upon these inputs. Then the Microprocessor can us Clock, Data and Enable lines to control the
Tuner.
SAP LED is routed from the Main Tuner at pin (20), through Q203, to the DAC1 I003 pin (9). The DAC1
outputs Clock and Data via pins 15 SCL1 and 14 SDA1 signals to the Microprocessor input on pin 3
SCL1 and pin 2 SDA2. The Microprocessor knows how to switch the tuner decoder circuit by making
54
CIRCUIT DESCRIPTION
judgment upon these inputs. Then the Microprocessor can us Clock, Data and Enable lines to control the
Tuner. Clock, Data and Enable lines for the Main Tuner are output from the Microprocessor at pins (20, 21
and 44) respectively. Pin (44) FEENABLE1 goes directly to the Main Tuner at pin (6), where as the Clock
and Data lines must be routed through the Level Shift IC I014 to be brought up to 5V. Clock and Data
arrive at I014 at pin 2 and pin 3 and are output at pin18 and pin17. They arrive at the Main Tuner at pins (4
and 5). The PinP Tuner doesnt have MTS capability. It only output mono audio, so no switching takes
place for the PinP Tuner U202 audio circuit. The only difference for the PinP tuner control lines is related to
the PinP Enable line. This is output from the Microprocessor pin (43 FEENABLE2) to the PinP Tuner at pin
(17). Clock and Data are the same as for the Main Tuner.
Controlling Switching between Tuner (Main), AVX 1, 2, 3 and 4, Component 1, and 2, and Tuner 2
(AUX) or In From Converter.
The Remote Control or the Front Panel switches can select the different inputs. This is accomplished by the
INPUT button. Each time the Input button is pressed, the different inputs are sequentially selected. The
sequential order is, Main Tuner, AVX 1, AVX 2, AVX 3, AVX 4, 2nd Antenna and back to Main Tuner. In
addition, if there are S-Inputs on AVX1, 2 or 4, an internal mechanical switch inside the S-Jack tells the
Microprocessor an S-Jack is inserted. Then when that particular input is selected, it automatically selects S
as its source. The same thing holds true for Component inputs. The set should never have Component
inputs and S-Jack inserted at the same time. This will cause a black and white picture will be displayed.
PAGE 02-11
Use this explanation in conjunction with the Microprocessor Data Communications circuit diagram.
The Microprocessor must keep in communication with the Chassis to maintain control over the individual
circuits. Some of the circuits must return information as well so the Microprocessor will know how to
respond to different request. The Microprocessor uses a combination of I 2 C Bus communication and the
Standard Data, Clock and Load lines for control. The I 2 C communication scheme only requires 2 lines for
control. These lines are called SDA and SCL. System Data and System Clock respectively. The Microprocessor also requires the use of what are called Fan Out IC or DACs, (Digital to Analog Converters). This
allows the Microprocessor to us only two lines to control many different circuits. In addition, because this
Microprocessor operates at the new 3.3Vdc voltage, it requires a Level Shift IC to bring up the DC level of
the control lines to make it compatible with the connected ICs. The Microprocessor communicates with the
following ICs:
ON THE SIGNAL PWB:
Main Tuner U201
PinP Tuner U202
EEPROM I002
Flex Converter U205
DAC1 I003
DAC2 I004
Level Shift I014
3D Y/C U204
Main Video Chroma I201
55
CIRCUIT DESCRIPTION
ON THE TERMINAL PWB:
A/V Selector I401
Sub Video Chroma I403
ON THE DEFLECTION PWB:
Sweep Control I701
ON THE SUB VIDEO PWB (2H VIDEO):
Rainforest IX01
ON THE SURROUND PWB:
Front Audio Control IS03
Center/LFT/PinP Audio Control IS08
Surround Board DAC3 IS01
Front Equalizer IS05
Center Equalizer IS10
Rear Audio Control IS11
Audio DSP (Digital Signal Processor) DSP Unit HC4051
The following explanation will deal with the communication paths used between the Microprocessor and the
respected ICs.
ON THE SIGNAL PWB:
Main Tuner U201
The Microprocessor controls the Main Tuner by Clock, Data and Enable lines. Clock, Data and Enable
lines for the Main Tuner are output from the Microprocessor at pins (20 Clock, 21 Data and 44
FEENABLE1) respectively. Pin (44) FEENABLE1 goes directly to the Main Tuner at pin (6), where as the
Clock and Data lines must be routed through the Level Shift IC I014 to be brought up to 5V. Clock and
Data from the Microprocessor arrive at I014 (Level Shift) at pins 2 and pin 3 and are output at pin18 and
pin17. They arrive at the Main Tuner at pins (4 and 5).
PinP Tuner U202
The only difference for the PinP tuner control lines is related to the PinP Enable line. This is output from the
Microprocessor pin 43 (FEENABLE2) to the PinP Tuner at pin 17. Clock and Data are the same as for the
Main Tuner.
EEPROM I002
The EEPROM is ROM for many different functions of the Microprocessor. Channel Scan or Memory List,
Customer set-ups for Video, Audio, Surround etc are memorized as well. In addition, some of the
Microprocessors internal sub routines have variables that are stored in the EEPROM, such as the window
for Closed Caption detection. Data and Clock lines are SDA1 from pin (2) of the Microprocessor to pin
(5) of the EEPROM and SCL2 from pin (3) of the Microprocessor to pin (6) of the EEPROM. Data
travels in both directions on the Data line.
56
CIRCUIT DESCRIPTION
Flex Converter U205
The projection television is capable of two different horizontal frequencies. 31.75Khz for everything except
HD and 33.75Khz for HD. (High Definition). The Flex Converter is responsible for receiving any video
input and converting it to the related output. This output is controlled by the input sync and by the
customers menu. The set up can be 4X3 or 16X9 sometimes called letterbox. The Flex Converter can take
any NTSC, S-In, Component in NTSC, Progressive or Interlaced, and 480I, 720P, 1080I signal. Control
for the Flex Converter is Clock, Data and Enable lines. Clock, Data and Enable lines for the Flex Converter
are output from the Microprocessor at pins (20 Clock, 21 Data and 46 FCENABLE). FCENABLE Clock
and Data lines must be routed through the Level Shift IC I014 to be brought up to 5V. They arrive at I014
at pins (2 Clock, 3 Data and 4 FCENABLE) and are output at pins (18, 17 and 16) respectively. DAC1
I003 This Digital to Analog converter acts as an extension of the Microprocessor sometimes called an
Expansion IC. The purpose of this IC is to reduce the number of pins, (fan out) of the Main Microprocessor
I001. The Main Microprocessor sends Clock and Data via I2C bus to the DAC1 IC. The output from the
Microprocessor is pin (2 SDA1 and 3 SCL1) which arrives at the DAC1 IC at pins (5 and 6) respectively.
The following is a list of the input and output pins on DAC1.
PIN
1. IR Det.
2. YN Det.
3. Blk Main
4. MTS
5. F Mono
6. Ant
7. Blk Sub
8. Gnd
9. SAP Det
10. ST Det
11. SAD0
12. SAD1
13. SAD2
14. SDA
15. SCL
16. Vcc
FUNCTION
The IR pulse from the Remote Control is monitored when Auto Link is set. (See
Auto Link in Index).
Active Low. This pin monitors for active sync when Auto Link is set. (See Auto
Link in Index).
Normal High, Blanking Low. Blanks Y-Cb/Cr into Flex Converter.
Places the Main Tuner pin (21 mode) into MTS Stereo. If Tuner receiving MTS
signal. See pin 10.
Places the Main Tuner pin (22 mono) into forced Mono Mode.
Switches the antenna block into Antenna A or Antenna B when selected.
Normal High, Blanking Low. Blanks PinP Sub Y-Cb/Cr on Terminal PWB before
going into Flex Converter.
Ground
The Main Tuner outputs an SAP LED signal when SAP is detected. Active Low.
The Main Tuner outputs an ST LED signal when Stereo is detected. Active Low.
Ground Not Used
Ground Not Used
Ground Not Used
Data I 2 C communications between DAC1 and Microprocessor
Clock I 2 C communications between DAC1 and Microprocessor
IC B+. (STBY +5V)
57
CIRCUIT DESCRIPTION
DAC2 I004
This Digital to Analog converter acts as an extension of the Microprocessor. Sometimes called an Expansion
IC. The purpose of this IC is to reduce the number of pins, (fan out) of the Main Microprocessor I001. The
Main Microprocessor sends Clock and Data via I2C bus to the DAC2 IC. The output from the Microprocessor is pin (2 SDA1 and 3 SCL1) which arrives at the DAC2 IC at pins (5 and 6) respectively.
PIN
1. YUV Det1
2. YUV Det2
3. FH Det Out 1
4. Sel5
5. F Mono
6. FH Det Out 1
7. 31/33
8. Gnd
9. CS Sel
10. Busy
11. SAD0
12. SAD1
13. SAD2
14. SDA
15. SCL
16. Vcc
FUNCTION
Detects activity on Component Input number 1.
Detects activity on Component Input number 2.
Test Point 1 (TP1).
Controls IX02 on 2H PWB. Selects either Y Cb/Cr or Y IQ to com
pensate for Chroma Phase angle used in Auto Color.
Places the Main Tuner pin (22 mono) into forced Mono Mode.
Test Point 2 (TP2).
Notifies the DCU related to Horizontal Frequency. Either 31.75Khz
for everything but HD or 33.75Khz for HD. The DCU uses two sets
of memory. One for everything but HD and one for HD. This relates
to both Digital Convergence adjustment data and for Magic Focus
memory. Also notifies the Dynamic Focus Horizontal Parabolic
generator to compensate for phase distortion. Also, notifies I701
Horizontal Drive generation IC concerning the Horizontal operation
frequency.
Ground
Not Used.
Informs the Microprocessor that the DCU is in the Digital Conver
gence Adjustment Mode. The Micro. Ignores IR pulses.
Ground Not Used
Ground Not Used
IC B+. (STBY +5V).
IC B+. (STBY +5V).
Level Shift I014

The Microprocessor operates at 3.3Vdc. Most of the Circuits controlled by the Microprocessor operate at
5Vdc. The Level Shift IC steps up the DC voltage to accommodate.
3D Y/C U204
The 3D Y/C module is a Luminance/Chroma separator, as well as a 3D adder. Separation takes place
digitally inside the module. Using advanced separation technology, this module separates and doesnt
produce dot pattern interference or dot crawl. The 3D effect is a process of adding additional signals to the
Luminance and Chroma. These signals relate specifically to transitions. Transitions are the point where the
signal goes from dark to light or vice versa. The 3D adds a little more black before the transition goes to
white and a little more white just before it gets to white. It also adds a little more white just before it goes
58
CIRCUIT DESCRIPTION
dark and a little more dark just before it arrives. This gives the impression that the signal pops out of the
screen or a 3D effect. The Microprocessor communicates with the 3D Y/C module via I 2 C bus data and
clock. The communications ports are from the Microprocessor pins (59 SDA2 and 60 SCL2) to the 3D Y/
C PYC1 connector pins (2 and 3) respectively. The Microprocessor also is able to turn on and off circuits
within the 3D Y/C module determined by customer menu set-up.
Main Video Chroma I201
The Main Video Chroma IC processes the video and chroma from the 3D Y/C module for the main picture.
It converts video into Y and chroma into Cr/Cb (NTSC Only). Communication from the Microprocessor
via pins (59 SDA2 and 60 SCL2) to I201 pins (34 and 33) respectively.
ON THE TERMINAL PWB:
A/V Selector I401
The A/V Selector IC is responsible for selecting the input source for the Main Picture as well as the source
for the PinP or Sub picture. Communication from the Microprocessor via pins (2 SDA1 and 3 SCL1) to the
PST1 connector pins (5 and 6) respectively then to I401 pins (34 and 33) respectively.
Sub Video Chroma I403
The Sub Video Chroma IC processes the video and chroma for the Sub or PinP picture. It converts video
into Y and chroma into Cr/Cb (NTSC Only). Communication from the Microprocessor via pins (59 SDA2
and 60 SCL2) to connector PST1 pins (1 and 2) I403 pins (34 and 33) respectively.
ON THE DEFLECTION PWB:
Sweep Control I701
The Sweep Control IC is responsible for generating Horizontal Drive and Vertical Drive signals. The Microprocessor must tell the IC when certain things are done in the Service Menu. When Cut Off is performed,
the Vertical is collapsed. The Microprocessor tells I701 to stop producing Vertical Drive. At the same time,
I701 must stop the Spot Killer circuit from operating. This is accomplished by placing pin (24 DAC3) high
which activates QN07 which inhibits spot killer high. In addition, when H.Phase is adjusted, the Microprocessor controls the H. Drive signals phase in relationship to H.Blk, which is timed with video sync. This
gives the appearance that the horizontal centering is being moved. Communication from the Microprocessor
via pins (59 SDA2 and 60 SCL2) to the PSD2 connector pins (2 and 3) and then to I701 pins (16 and 17)
respectively.
ON THE SUB VIDEO PWB (2H VIDEO):
Rainforest IX01
The Video Processing IC (Rainforest) is responsible for controlling video/chroma processing before the
signal is made available to the CRTs. Some of the emphasis circuits are controlled by the customers menu.
As well as some of them being controlled by AI, (Artificial Intelligence). Communication from the Microprocessor via pins (59 SDA2 and 60 SCL2) to the PSZ2 connector pins (1 and 2) and then to IX01 pins (27
and 26) respectively.
59
CIRCUIT DESCRIPTION
ON THE SURROUND PWB:
Surround Board DAC3 IS01
This Digital to Analog converter acts as an extension of the Microprocessor. Sometimes called an Expansion
IC. The purpose of this IC is to reduce the number of pins, (fan out) of the Main Microprocessor I001. The
Main Microprocessor sends Clock and Data via I 2 C bus to the DAC3 IC. The output from the Microprocessor is pins (59 SDA2 and 60 SCL2) then through the connector PSU1 pins (2 and 1) which arrives
at the DAC3 IC at pins (14 and 15) respectively.
PIN
1. SW Sel 1
2. DSP CSI
3. Opti/Coax Sel
4. RSPOFF
5. CSPOFF
6. FSPOFF
7. SWSEL 2
8. Gnd
9. P. Vol.
10. DSPREQ
11. SAD0
12. SAD1
13. SAD2
14. SDA2
15. SCL2
16. Vcc
FUNCTION
Turns on/off QS01 which either adds or doesnt add Sub Woofer to Front L and
Front R for 3 way audio set up.
Digital Surround Module signal. If the Coax Audio input is noisy, the DSP tells
DAC3 to 2X invert the signal.
Controls IS17. Determines if the signal is 2X inverted due to noise.
Turns off the Rear Speaker outputs. Controlled by the customers menu.
Turns off the Center Speaker outputs. Controlled by the customers menu.
Turns off the internal Front Speaker outputs. Controlled by the customers menu.
Controls QS25 to add Front Left and Right to Sub Woofer.
Ground
Perfect Volume On/Off controlled by the customers menu. Note, when in ProLogic mode, Perfect Volume is Off.
DSP Request Input.
Ground Not Used
Ground Not Used
Ground Not Used
IC B+. (STBY +5V)
Front Audio Control IS03

The Front Audio Control IC has the ability to adjust balance, treble, bass, volume and mute. This mute is
the one that is activated when the mute button is pressed on the remote control. Communication from the
Microprocessor via pins (59 SDA2 and 60 SCL2) then through the connector PSU1 pins (2 and 1) which
arrives at the IS03 at pins (4 and 5) respectively.
Center/LFE/PinP Audio Control IS08
This IC has the ability to adjust balance, treble, bass, volume and mute for the Center channel. This mute is
the one that is activated when the mute button is pressed on the remote control. It also adjusts the volume
for the PinP audio sent to the transmitter outputs as well as the volume for the Sub Woofer called LFE (Low
Frequency Effects). Communication from the Microprocessor via pins (59 SDA2 and 60 SCL2) then
through the connector PSU1 pins (2 and 1) which arrives at the IS08 at pins (4 and 5) respectively.
60
CIRCUIT DESCRIPTION
Front Equalizer IS05
The Front Audio can be frequency adjusted to suite the particular room environment. The individual frequency notches are adjusted via the customers menu. The following frequency notches are adjusted by this
IC. 60HZ,
250HZ, 1KHz, 3KHz, and 10KHz. Communication from the Microprocessor via pins (59 SDA2 and 60
SCL2) then through the connector PSU1 pins (2 and 1) which arrives at the IS05 at pins (17 and 16)
respectively.
Center Equalizer IS10
The Center Audio can be frequency adjusted to suite the particular room environment. The individual
frequency notches are adjusted via the customers menu. The following frequency notches are adjusted by
this IC. 60HZ, 250HZ, 1KHz, 3KHz, and 10KHz. Communication from the Microprocessor via pins (59
SDA2 and 60 SCL2) then through the connector PSU1 pins (2 and 1) which arrives at the IS05 at pins (17
and 16) respectively.
Rear Audio Control IS11
The Rear Audio Control IC has the ability to adjust balance, treble, bass, volume and mute. This mute is the
one that is activated when the mute button is pressed on the remote control. Communication from the
Microprocessor via pins (57 SDA3 and 58 SCL3) then through the connector PSU1 pins (4 and 3) which
arrives at the IS11 at pins (4 and 5) respectively.
Audio DSP (Digital Signal Processor) DSP Unit HC4051
The Digital Signal Processor is responsible for decoding Dolby Pro-Logic, AC-3 audio and selecting the
output of the audio determined by the customers menu. Such as Off, Matrix, Hall, etc Control for the
DSP is routed from the Microprocessor pins (15 DSPSS DSP Surround Sound Mode, 16 DSPSCK DSP
Clock, 17 DSPI DSP Mode 1, 18 DSPERR Mute DSP Error Mute, and 19 DSPRST DSP Re-set). Then
to the Level Shift, IC I014 pins (5, 6, 8, 7, and 9) respectively. These signals are then routed to the PSU2
connector pins (5, 2, 3, 6, and 1) respectively to the DSP module via the PMU1 connector pins (9, 12, 11,
8 and 13) respectively.
OSD Genaration
The Microprocessor is responsible for generating On Screen Display (OSD) related to the Main Menu,
Volume Control, Channel Number, Closed Caption Display, Clock, etc It also generates the OSD for the
Service Menu. However there are actually two different sources for generating OSD, the Microprocessor
and the Digital Convergence Unit, (DCU).
MICROPROCESSOR AS THE SOURCE FOR OSD
The Microprocessor receives information related to timing for H. Blanking and V. Blanking. These arrive at
pins (49 and 55) respectively. The Microprocessor determines the position for each display using these
signals as a timing pulse. When necessary, the Microprocessor generates 1uSec pulses from pins (37 Red,
38 Green and 39 Blue) that are routed through the PSZ1 connector pins (14 Red, 16 Green and 18 Blue).
These are then routed through (QX07 Red, QX08 Green and QX09 Blue) and sent to the Rainforest IC
IX01 pins (39 Red, 38 Green and 37 Blue) as OSD signals. When the OSD signals are high, they turn on
the output of the Red or Green or Blue chroma amps inside the Rainforest IC and output a pulse to the
CRTs to generate that particular character in the particular color.
61
ZP-94/95 CHASSIS "On Screen Display, OSD" SIGNAL CIRCUIT DIAGRAM

I001
Main uP
Signal PWB
OSD B
Sync for Closed Caption 28 Main
OSD G
Sync2 for Closed Caption 30 Sub
OSD R
I004 15
DAC
14
SCL1
DAL1
Half Tone
P Blk
10
OSD Blk
IX01
Rainforest
PSZ1
OSD Blue
39
38
37
OSD Green
OSD Red
OSD YM
40
56
OSD YS
Q013
Q007
18
16
14
QX09
37
38
QX07
39
QX08
Analog B In
Analog G In
Analog R In
20
47
YM
19
36
YS1
51
PDG
10
UKDG
HC2151
13
12
Digital
Convergence
Unit
"DCU"
"Mounted on
Deflection
PWB"
11
1
2
3
4
5
6
7
PSD1
BUSY
QK08
Dig B
QK07
Dig G
QK06
Dig R
26
12
QX03
B Out
41
G Out
42
R Out
43
32
YS2
33
Analog B In
34
Analog G In
35
Analog R In
QX02
10
26
QX01
-5V
+5V
+5V SRAM
H Blk
D Size
V Blk
62
Deflection PWB
Signal SUB PWB
QX41
QX36
QX31
CIRCUIT DESCRIPTION
BUSY
PZC
CIRCUIT DESCRIPTION
Half Tone Pin (40)
This pin is responsible for controlling the background transparency of the Main Menu. When the customer
calls up the Main Menu, they can select the CUSTOM section. Within the CUSTOM section is MENU
BACKGROUND. There are three selections for this, GRAY, SHADED, and CLEAR.
CLEAR:
SHADED:
Selection turns off any background for the Menu and video is clearly seen behind the Menu.
Selection adds a transparent background, which makes the Menu and some of the video
behind the Menu easier to see.
GRAY:
Selection generates a GRAY background for the MENU blocking video behind the Menu.
This is accomplished by outputting any one of three different pulses from pin (40) of the Microprocessor.
This signal is then routed through the PSZ1 connector pin (20) to the Rainforest IC IX01 pin (47) as YM
signal which does the following:
CLEAR:
No output during the display of the Menu.
SHADED:
1/2 Vcc pulse equal to the timing of the Menu background.
GRAY:
Full Vcc equal to the timing of the Menu background.
OSD Blanking Pin (51)
This pin is responsible for muting the video behind each character produced by the Microprocessor. This
pulse is in exact time with the character, however it is slightly longer. In other words, just before any
character is produced, this pin goes high and just after any character turns off, this pin turns off. This clears
up the video behind the OSD character to make it easier to read. OSD Blk is produced from pin (51) of the
Microprocessor. This signal is then routed through Q013, then through Q007, through the PSZ1 connector
pin (19) to the Rainforest IC IX01 pin (36) as YS1 signal which mutes the video.
P Blk Picture Blanking Pin (56)
This pin is responsible for muting the video when the Microprocessor deems it necessary. This would be
during power up or power off, child lock, channel change, or selecting a video input with no video input
available. P Blk is produced from pin (56) of the Microprocessor. This signal is then routed through Q007,
through the PSZ1 connector pin (19) to the Rainforest IC IX01 pin (36) as YS1 signal which mutes the
video.
Closed Caption Display From The Microprossessor Source
The Microprocessor is also responsible for stripping the Closed Caption Display (CCD) from within the
Vertical Sync on horizontal line 21. It receives the composite video signal at pin (28). This signal is tapped
off the main video path before it arrives at I005 pin (5). See Video Path Circuit Diagram and Explanation
for Details. The tapped video is routed through Q021 to the Microprocessor at pin (28). See Sync Signal
Path Circuit Diagram and Explanation for Details.
DCU As The Source
The DCU (Digital Convergence Unit) generates its own OSD patterns and text. The DCU generates these
characters in the same fashion as the Microprocessor. The DCU generates Digital Red from pin (11), Digital
Green from pin (12) and Digital Blue from pin (10) output from the PDG and then through (QK06 Dig Red,
QK07 Dig Green and QK08 Dig Blue). The DCU characters are then routed through the PSD1 connector
pins (2 Red, 4 Green and 6 Blue). These are then routed through (QX01 Red, QX02 Green and QX03
Blue) and sent to the Rainforest IC IX01 pins (35 Analog Red In, 34 Analog Green In and 33 Analog Blue
In) as Digital Convergence graphic signals. When the DCU is activated by pressing the Service Only switch
on the Deflection PWB, the DCU outputs a BUSY signal. This signal does two things.
63
CIRCUIT DESCRIPTION
First, it tells the Microprocessor to ignore Inferred Remote commands. It does this by outputting the BUSY
signal from pin (10) of the PDG connector and then through the PSD1 connector pin (1). Then to I004 the
Analog to Digital converter. The Analog to Digital converter outputs this information in digital form through
the I2C bus to the microprocessor. The I2C data is output from pin 14 SDA1 and 15 SCL1 and arrives at
the Microprocessor I001 pins (2 and 3). When the Microprocessor receives this BUSY signal, it ignores all
Inferred Remote commands. Second, tt blanks video so that the DCU graphics can be see easily. This is
accomplished by the same BUSY signal being routed from pin (10) of the PDG connector and then through
the PSD1 connector pin (1). It is then routed through the PSZ1 connector pin (7) to the Rainforest IC IX01
pin (32) as YS2 signal which mutes video.
GRAPHICS PRODUCED BY THE DCU
Cross hatch grid, 3X3, 5X7 or 13X9.
Colored Cursor which blinks indicating the adjustment point
Different text such as, Read from ROM? Write to ROM?
Light pattern for Sensor Initialization
Light pattern for Magic Focus.
The DCU can also turn off individual colors during adjustment. Everything except Green. This is accomplished by not producing the particular colors characters from the DCU.
V MUTE 1 EXPLANATION
There are certain times when the Microprocessor or other circuits must Mute the video or audio. The
Microprocessor is responsible for Muting the Audio/Video during Channel Change, Power On/Off, Child
Lock, and AVX Selected with no input, etc. This is accomplished via pin (45) of the Microprocessor.
When V Mute is activated, a high is routed through D028 to the base of Q022 turning it ON. The collector
goes low and pulls the base of Q023 low turning it ON. The emitter of Q023 is connected to STBY +11V,
so when it turns ON, its collector output goes HIGH. This high is now called V Mute 1. V Mute 1 is routed
to two circuits, for Video Mute and for Audio Mute.
FOR VIDEO MUTE
There are three different signals used to mute video on the Rainforest IC, (IX01 pin 25 FBP In). First, V
Mute 1 high is routed through the PSZ2 connector pin (6) to DX08. DX08 sends this high to the base of
QX18 turning it OFF. The emitter of QX18 is connected to the SW +9V line and when it turns OFF the
emitter pulls up HIGH. This pulls up pin (25) of IX01 the rainforest IC and Mutes the Video. Oddly
enough, this high is sent into the same pin as the Flyback Pulse used for horizontal blanking. So it can be
thought of as an extremely long blank pulse. Second, H Blk FC, which is generated by the Flex Converter
U205 at, pin (12 H.BLK). This positive going blanking signal generated in time with Horizontal Sync from
the main picture is routed through the PSZ2 connector pin (12) to DX09 to the base of QX18 turning it
OFF with each positive going pulse. The emitter of QX18 is connected to the SW +9V line and when it
turns OFF the emitter pulls up HIGH. This inputs positive horizontal blanking signals into pin (25) of IX01
the rainforest IC and Mutes the Video. This signals is used for horizontal blanking. Third, V Blk FC, which
is generated by the Flex Converter U205 at, pin (11 V.BLK). This positive going blanking signal generated
in time with Vertical Sync from the main picture is routed through the PSZ2 connector pin (13) to DX10 to
the base of QX18 turning it OFF with each positive going pulse. The emitter of QX18 is connected to the
SW +9V line and when it turns OFF the emitter pulls up HIGH. This inputs positive vertical blanking signals
into pin (25) of IX01 the rainforest IC and Mutes the Video. This signals is used for vertical blanking.
64
ZP-94/95 Series Chassis AUDIO and VIDEO MUTE Circuit

(See also Surround Mute Circuit)
From I904
Pin 3
AC Photo
Coupler
AC Sig
RN15
DN09
D030
C070
R190
D027
R191
2H Video PWB
SW+9V
Q024
PSZ2
R192
R195
R193
R194
D029
C008
DN08
Q023
PSD2
Q022
R010
D031
R198
Q001
R008
R011
PQS1
10
SBY +11V
"HV PROTECT"
Horizontal Sweep Loss Det.
Vertical Sweep Loss Det.
(From Deflection PWB)
R196
V Blk FC
H Blk FC
V Mute 1
V. Mute 1
R007
12
6
Signal PWB
I001
V MUTE
45
ERRMute
18
25 FBP
In
DX08
DX08
QX18
D028
Micro Processor
RX57
V Mute 2
R029
A5V
I014
Level Shift
PSU2
Audio
DSP
DC04
13
DC03
14
QC03
Mute = Lo
RC09
RC07
VMute
ERR Mute
RC08
PSU1
14
9
8
From IS01 Pin 6 6

Mute 7
65
Surround PWB
FRONT
L&R
Audio
Output
CC09
CC08
V Mute 2
Right Ft. Audio
CC02
Left Ft. Audio
CC01
F. Spk Off
DC02
RC03
QC01
RC04
ERRMute
DC01
CC04
QC02
IC01
11 Mute
CC03
R In R Out
L In L Out
12
CIRCUIT DESCRIPTION
C009
13
IX01
RX52
DX09
CIRCUIT DESCRIPTION
V Mute 1 FOR AUDIO MUTE
The V Mute 1 signal is also routed to the base of Q024 turning it ON. The high produced on its emitter is
now called V Mute 2 which is routed to two places. First, to the anode of DC04, to the base of QC03
which turn ON and grounds pin (11) of IC01 placing the Front Audio output IC into Mute. Second, to
PSU1 connector pin (14), which mutes the Center and Rear audio, output ICs. See the Surround Mute
ERRMUTE pin (18) of the Microprocessor
When the Microprocessor deems it necessary to mute the audio, it outputs a ERRMute signal from pin (18)
to I014 pin (7) the Level Shift IC. This IC outputs the high from pin (13) to three places. First, to the Audio
DSP circuit via the PSU2 connector pin (6) to mute the internal functions of the DSP. Second, to the
Surround PWB via the PSU1 connector, pin (7) called Mute. Here the audio outputs for out to Hi-Fi,
Transmitter out and Sub woofer are muted. Third. to the anode of DC01, then to the base of QC01 and
QC02 which grounds the audio input to pin (4 Right audio in and 2 Left audio in) of IC01.
F.Spk Off FRONT SPEAKER OFF
When the customer accesses the Main Menu and selects the Front Speaker Off selection, DAC IS01 on
the Surround PWB outputs a high from pin (6). This high is routed through the PSU1 connector pin (6) to
the anode of two diodes. First, to the anode of DC03, to the base of QC03 which turn ON and grounds
pin (11) of IC01 placing the Front Audio output IC into Mute. Second, to the anode of DC02, then to the
base of QC01 and QC02, which grounds the audio input to pin 4 Right audio in and 2 Left audio in) of
IC01.
AC LOSS DETECTION:
AC is monitored by the AC Loss detection circuit. The AC input from PQS1 pin (10) is rectified by DN09.
This charges up C009 and through DN08, it charges C008. When AC is first applied, C008 charges slightly
be-hind C009 preventing activation of Q001. If AC is lost, C009 discharges rapidly pulling the base of
Q001 low, however DN08 blocks C008 from discharging and the emitter of Q001 is held high. This action
turns on Q001 and produces a high. This high is routed through D029 to the base of Q022 turning it ON.
The collector goes low and pulls the base of Q023 low turning it ON. The emitter of Q023 is connected to
STBY +11V, so when it turns ON, its collector output goes HIGH. This high is now called V Mute 1. V
Mute 1 is routed to two circuits, see V Mute 1 explanation on the previous page.
SPOT:
SPOT is generated from the deflection PWB when either Horizontal or Vertical deflection is lost. This is to
pre-vent a horizontal or vertical line from being burnt into the CRTs. See Horizontal and Vertical Sweep
Loss Detection circuit and explanation for details. This high is input from PSD2 pin (6), through D027 to the
base of Q022 turning it ON. The collector goes low and pulls the base of Q023 low turning it ON. The
emitter of Q023 is connected to STBY +11V, so when it turns ON, its collector output goes HIGH. This
high is now called V Mute 1. V Mute 1 is routed to two circuits, see V Mute 1 explanation on the previous
page.
66
CIRCUIT DESCRIPTION
ZP-94/95 SWEEP & AC LOSS DETECTION CIRCUIT
SW+12V
RN05
Vertical
Blanking
From
Pin 11 I601
RN03
QN02
RN04
See Deflection Power

Supply Circuit
Diagram
DN01
QN01
RN01
CN02
V. Blk.
DN02
CN01
SPOTPROTECT
DN03
RN02
DN14
24V P/P
DN15
RN10
SW+12V
RN07
RN10
Stby 11V
RN09
Horizontal
Blanking
From
Q755 Emitter
QN04
DN04
DN05
CN03
CN04
RN06
QN03
QN05
RN11
DN13
RN15
DN06
H. Blk.
High Voltage
Driver IC
IH02
RN08
RN13
14 Stops
Drive
RN12
PSD3
11.6V P/P
SPOT
Prevents CRT Burn
DN11
DN12
1 Drive
2
RN14
DN09
Horizontal
and
Vertical
Drive IC
QN08
H Drive
I701
QN08
DAC3 24
RH60
Stops High Voltage Drive

Signals From being
produced
when Sweep Loss is
detected.
QN07
When Vertical Drive is
turned Off during
adjustment, I2C.
Spot Inhibit
HVcc
R718
67
CIRCUIT DESCRIPTION
MUTE SIGNAL PATH DESCRIPTION
V Mute 2 FOR SURROUND MUTE:
The V Mute 1 signal explained in the Audio Video Mute signal path explanation is also routed to the base of
Q024 turning it ON. The high produced on its emitter is now called V Mute 2 which is routed to the
Surround PWB via the PSU1 connector pin (14). V Mute 2 is labeled VMute on the Surround PWB. This
high arrives at the anode of the following diodes;
1. DS27, which puts a high on the base of QS06 turning it ON which grounds pin (11) of IC15 placing the
Center Audio output IC into Mute.
2. DS49, which puts a high on the base of QS20 turning it ON. This grounds the Sub Woofer audio output.
3. DS45, which puts a high on the bases of QS17 and QS16 turning them ON. This grounds the Out to HiFi outputs.
4. DS37, which puts a high on the base of QS10, turning it ON. This grounds the Rear audio output
ERRMUTE PIN 7 of the PSU1 CONNECTOR:
The ERRMute signal explained in the Audio Video Mute signal path explanation is routed to the Surround
PWB via the PSU1 connector pin (7). See the Audio Video Mute Signal Path explanation and diagram for
details concerning the generation of the ERRMute signal. ERRMute is labeled Mute on the Surround PWB.
This high arrives at the anode of the following diodes;
1. DS24 which puts a high on the base of QS04 and QS05 turning them ON. This grounds the audio input
to the Center audio output IC, IS15 at pins (4 and 2).
2. DS48 which puts a high on the base of QS20, turning it ON. This grounds the Sub Woofer audio output.
3. DS44 which puts a high on the bases of QS17 and QS16 turning them ON. This grounds the Out to HiFi outputs.
to the Rear audio output IC, IS16 at pins (4 and 2).
ERRMUTE PIN 14 of the PSU2 CONNECTOR:
The ERRMute signal explained in the Audio Video Mute signal path explanation is routed to the Surround
PWB via the PSU2 connector pin (6). ERRMute places the DSP Audio Module into Mute when the
Microprocessor deems it necessary. See the Audio Video Mute Signal Path explanation and diagram for
details concerning the generation of the ERRMute signal.
RSpkOff (REAR SPEAKER OFF) IS01 PIN 4:
The Rear Speaker Off signal is output from IS01 pin (4). This high arrives at the anode of the following
diodes;
1. DS36 which puts a high on the base of QS10 turning it ON which grounds pin (11) of IC16 placing the
Rear Audio output IC into Mute.
CSpkOff (CENTER SPEAKER OFF) IS01 PIN 4:
The Center Speaker Off signal is output from IS01 pin (5). This high arrives at the anode of the following
diodes;
1. DS26 which puts a high on the base of QS06 turning it ON which grounds pin (11) of IC15 placing the
Center Audio output IC into Mute.
68
PSU2
PMU1
14
ERR Mute
PSU1
F. Spk Off
Surround
DSP
Module
Mute = Lo
IS01
QS06
DS27
VMute
6 F. Spk Off
DS26
CSpkOff
RSpkOff
6
QS04
DS24
QS05
C In C Out
C In C Out 12
CSJ5
RS04
ERRMute 7
RSpkOff
Mute = Lo
Sub Woofer
QS20 SD50
QS10
DS49
DS37
DS35
DS45
QS17 SD47
69
QS16 SD46
CSM9
REAR L
RSJ6
DS44
DS34
CSM3
CSM1
CSM2
QS09
RSJ5
Mute
REAR
Audio
Output
CSM8
REAR R
HiFi L
HiFi R
RSJ8
IS16
11 Mute
RSJ7
DS36
DS48
RSJ9
QS08
CSM4
R In R Out
L In L Out
12
CIRCUIT DESCRIPTION
Mute
CSJ4
CSJ2
CSJ3
RS03
CENTER
Audio
Output
CSJ9
CENTER
DS25
V Mute 2 14
Mute
CSK01
RSF6
IS15
11 Mute
RSF5
VMute
RSF7
FSpkOff (FRONT SPEAKER OFF) IS01 PIN 6:

The Front Speaker Off signal is output from IS01 pin (6). This high is routed out the PSU1 connector pin
ZP-94/95 Series Chassis SURROUND MUTE Circuit

(See also Audio Video Mute Circuit)
CIRCUIT DESCRIPTION
(6) and sent to the Signal PWB into the V Mute Circuit. See the Audio Video Mute Circuit Signal Path
Explanation and Diagram for more details.
ZP94/95 MEMORY INITIALIZATION PROCEDURE
(EEPROM RESET)
Disconnect Power to Television.
Remove the Back Cover.
Remove the two screws holding the Main chassis to the Cabinet if necessary.
Disconnect wiring harness clips to free up the chassis if necessary.
Reconnect Power to the Television and turn the set ON.
Locate PP1 and add a jumper between pins 1 and 2 of the PP1 connector as shown below.
Hold jumper in place for 5 seconds. (A beep will NOT be heard).
Remove the jumper.
Confirm EEPROM reset, Input source is now set to Air and not to Cable 1 or 2. No Child
Lock, and only channels 2 through 13 are in memory.
Reassemble Chassis and reinstall PTV back. Set is now ready to operate.
NOTE: All customersAuto Programming and Set-Ups are returned to factory settings.
WARNING: This should only be done in extreme cases. I2C Data will be reset as well. Be sure and write
down all data values before continuing.
Jumper
1
D024
R100
PP1
Connector
R0C5
20
KEY-IN1
CLOCK
I001
MicroProcessor
70
ZP-94/95 SERIES CHASSIS VIDEO SIGNAL PATH (Main & Terminal)

Lum/Audio Selector IC
3V
Avx 3 In
V3V
S Det.
Aux Input 3
S-Y3
S-C3
S-3 In
Signal PWB 1 of
2
U201
Main Tuner
18
15
5
3
17
19
32
TV1V
14
Q206
23
TV2V
19
Q405
PinP Yout2
Q406
PinP
Vide
o
63
PinP C
Q404
VOut1
53
4 V In
YIn1
49
1 Y Out
CIn1
51
3 C Out
Main
Video
NTSC
Monitor Out
Q409
60
Vout3
PinP VY
PinP C Cout2
Q403
Terminal
PWB
PST1
Q205
10
56
2
Line
Comb
Filter
I403
40
6
Q408
Sub Video Route
37 Y
46 R-Y
47 B-Y
See Component Signal Flow
Diagram for Continuation
41
Main C
Q410
Yout3
V1
S Det.
S-1 In
S-Y1
S-C1
8
10
12
S-Y2
S-C2
1
3
5
Aux
Inputs
V2
S Det.
S-2 In
Q411
39
Main Y/Video
Y/S Monitor Out

Cout3
37
Q402
V/Yout2
44
Cout2
47
PST2
Main Y
/Video
5
7
Main C
Q401
Terminal PWB
Q216
Main Y
/Video
Main C
Q213
3 Line Comb Filter
IJ01
8
25
25
QJ06
QJ08 QJ07
QJ05
IJ02
8
10
PYC1
1
QJ03
7
Main
Video/
Chroma
13
QJ10
9
QJ09
QJ12
Q214
40
S-CIn
QJ02
QJ01
QJ04
I201
Q235
QJ11
71
Video In
11
Signal PWB 2 of 2
CIRCUIT DESCRIPTION
U202
PinP TUNER (Mono)
Always PinP
I401
PFT
Front Control PWB
CIRCUIT DESCRIPTION
Video Circuit Block Diagram
I401 - Luminance Audio Selector IC
Main Tuner (TV1V) in
Sub Tuner (TV2V) in
Video 1 in from Terminal PWB
S-Video 1 (Y) from Terminal PWB
S-Video 1 (C) from Terminal PWB
Video 2 in from Terminal PWB
S-Video 2 (Y) from Terminal PWB
S-Video 2 (C) from Terminal PWB
Video 3 in from Front Control PWB
S-Video 3 (Y) from Front Control PWB
S-Video 3 (C) from Front Control PWB
Yin1 PinP Luminance from 2L Comb filter
Cin1 PinP Chroma from 2L Comb filter
VOut1 PinP Video to 2L Comb filter
YOut1 PinP (Y) to Sub video processor
COut1 PinP (C) to Sub video processor
V/YOut2 Main Video or S-Video (Y) to 3DYC
COut2 S-Video (C) to 3DYC
VOut3 Video out to Monitor
YOut3 S-Video (Y) out to Monitor
COut3 S-Video (C) out to Monitor
pin 63
pin 60
pin 8
pin 10
pin 12
pin 1
pin 3
pin 5
pin 15
pin 17
pin 19
pin 49
pin 51
pin 53
pin 56
pin 58
pin 44
pin 47
pin 41
pin 39
pin 37
I201 - Main Video Chroma Processor IC

Main video in (Y)
Main video in (C)
Y out
R-Y Out
B-Y Out
pin 40
pin 6
pin 37
pin 48
pin 47
I403 - Sub Video Chroma Processor IC

Sub video in (Y)
Sub video in (C)
Y out
R-Y Out
B-Y Out
pin 40
pin 6
pin 37
pin 48
pin 47
2 Line Comb Filter (PinP)

Video In
Y Out
C Out
pin 4
pin 1
pin 3
72
CIRCUIT DESCRIPTION
3DYC Comb Filter (Main)
Video/Y in
C in
Y Out
C Out pin 7
pin 11
pin 13
pin 9
I401 - Luminance/Audio Select IC

VIn4 Comp 1 (Y) When component video is 480i this is used for CCD, as well as the Auto Link function.
VIn5 Comp 2 (Y) When component video is 480i this is used for CCD, as well as the Auto Link function.
I406 - Main Component 1 / Component 2 Select IC
Selects either Component 1 or Component 2 (Y/CbPb/CrPr).
Outputs to I205.
I205 - Main Video / Component Select IC
Selects either Component 1 or 2 (Y/CbPb/CrPr) from I406 and Main (R-Y/B-Y/Y) from I201.
Outputs to Flex Converter Main inputs.
I407 - Sub Component 1 / Component 2 Select IC
Selects either Component 1 or Component 2 (Y/CbPb/CrPr).
Outputs to I404.
I404 - Sub Video / Component Select IC
Selects either Component 1 or 2 (Y/CbPb/CrPr) from I407 and Sub (R-Y/B-Y/Y) from I403.
Outputs to Flex Converter Sub inputs.
Flex Converter
Receives Main R-Y/B-Y/Y from I205 and Sub R-Y/B-Y/Y from I404.
Combines the two sets of signals (Main and Sub).
Converts output signals to 2H (31.75kHz) YCbCr unless signals are already 31.75kHz or higher.
YCbCr to YIQ Converter
Level/phase shifts color difference signals.
IX02 - YCbCr / YIQ Select IC
Selects either YCbCr or YIQ color difference signals.
YIQ is selected by microprocessor via I004 DAC2 sensing NTSC input on Comp 1 or 2.
Outputs to IX01.
IX01 - Rainforest IC
Receives the three color difference signals from IX02.
Outputs to the three CRT PWBs.
73
ZP-94/95 SERIES CHASSIS COMPONENT SIGNAL PATH (Main & Terminal)

Component 2
Inputs
I401
U205
Terminal PWB
Q439
Cr/Pr
Cr/Pr2
1
16
Cr/Pr1
Q438
Cb/Pb2
Cb/Pb
Comp 2 for
Auto Link
14
11
30
Y2
Y
Q437
Y1
Q434
1
16
Cb/Pb
14
11
Cr/Pr
Q436
Q414
48
5
2
1
11
3
9
5
11
Q426
Q425
8
9
Cr/Pr
PZC
1
Q442
7
1
IX01
2
1
Q228
Q226
15
42
I201
MAIN
PICTURE
47
37
Q416
Sub R-Y Cr Out
19
21
Q417
2
1
Q419
Sub B-Y Cb Out
19
17
Q420
2
1
19
Q418
Q422
Sub Y Out
15
15
Q423
Rain
forest
CB/Q
52
51
18
Q421
17
Q424
PSZ2
QX21
53
CR/I
41
Signal PWB
48
2H Video PWB
Y2 In
QX41
5
Q227
I404
43
Q231
PST2
Q441
11
5
QX36
3
Q230
5
2
1
9
3
QX31
R
Q234
Q229
Main Y Out
Q440
Cb/Pb
2
1
Sub Y Out
37
233
19
Main B-Y Cb Out
Sub B-Y Cb Out
Q412
21
2
1
Main R-Y Cr Out
Sub R-Y Cr Out

Q413
47
To CRT PWB
Cb/Pb
1
7
15
PFC2
2H Y
16
2H Y
18
2H B
See Chroma After Flex Converter Sig. Diagram

IX02
YCBCR/YIQ
SELECTOR
SUPER
MATRIX
IX03, 04
YCBCR to YIQ
CONVERTER
Q22~27 & 54,55
17
2H CB
2H R
19
2H CR
20
74
CIRCUIT DESCRIPTION
Q435
I403
2
1
13
Q427
I407
22
Terminal PWB
SUB PICTURE
Cr/Pr
Y
Comp 1for
Auto Link
PFC1
Q232
FLEX CONVERTER
Component 1
Inputs
8
9
I205
PST2
I406
Signal PWB
CIRCUIT DESCRIPTION
Component Video Circuit Block Diagram Explanation
75
ZP-94/95 SERIES CHASSIS CHROMA AFTER FLEX CONVERTER SIGNAL PATH

SW9V
Signal PWB
2H VIDEO PWB
U205
2H CB
17
18
2H CB
IX03
QX27
PSZ2
QX25
PFC2
2H B
SUPER MATRIX
YCBCR YIQ
CONVERTER
2H CR
QX24
I
QX23
QX55
2H CB
QX26
2H CR
5
3
2H CR
1 16
52
QX53
2H CB
QX52
51
2
1
CB/Q
U/Q In
14 11
CR/I
QX54
IX02
2H CB
IX01
V/I In
IX04
19
20
2H R
QX22
2H CR
Rainforest IC
RGB
Processor
YCBCR/YIQ
Selector
SW9V
76
CIRCUIT DESCRIPTION
FLEX CONVERTER
CIRCUIT DESCRIPTION
Chroma After Flex Converter Block Diagram Explanation
U205 - Flex Converter
Receives Main R-Y/B-Y/Y from I205 and Sub R-Y/B-Y/Y from I404.
Combines the two sets of signals (Main and Sub).
Converts output signals to 2H (31.75kHz) Y/Pb/Pr unless signals are already 31.75kHz or higher.
YCbCr to YIQ Converter
Consists of QX22-QX27, QX52-QX55
Level/phase shifts color difference signals.
IX02 - YCbCr / YIQ Select IC
Selects either YCbCr or YIQ color difference signals.
YIQ is selected by microprocessor via I004 DAC2 sensing NTSC input on Comp 1 or 2.
Outputs to IX01.
IX01 - Rainforest IC
Receives the three color difference signals from IX02.
Outputs to the three CRT PWBs.
Note: Three Color Difference signals can be:
RGB
R-Y/B-Y/Y
CrCbY
PrPbY
YIQ
YUV
CHROMA ROTATION CIRCUIT EXPLANATION
QUESTION:
What is the function of QX22, QX23, QX24, QX25, QX26 and QX27 on the output of the 3D Y/C
Combfilter.
ANSWER:
The RGB Processor IX01 (TA1298AN) has a function called Skin Tone correction. This circuit is also
named Auto Color or Auto Flesh Tone. The Auto Color function works only with Y/I-Q signals. The
YUV signal out of the Comb filter must be converted to YIQ before entering IX01 (Rainforest IC) in order
to use Auto Color. Y Pr/Pb YUV signals must be converted. IQ signals are made from UV signal by
giving them a 33 degree phase shift.
The Switching IC IX02 shown on the Chroma After Flex Converter Diagram selects either the NTSC Y/IQ
signal without rotation or the Y Pr/Pb with rotation as determined by the control signal Select 5 (SEL5).
Select 5 logic: High = Y/IQ (NTSC) and Low = YUV (Y/Pr/Pb).
Not shown is the input pin for Select 5 (SEL5) control signal. This control signal is in-put via pin (5 and
12).
77
ZP-94/95 SERIES CHASSIS SYNC SIGNAL PATH

Aux Input 3
Composite 3
V3V
3V
S Det.
Avx 3 In
S-Y3
S-C3
S-3 In
10
15
17
19
PST2
VOut1
Q205
U201
Main Tuner
18
63
TV1V
Main
Video
NTSC
Q206
VOut2
44
Q208
Q402
Q018
Lo
5
Q017
Main Y
/Video
TV2V
60 PinP
19
Q019
I001
Sub for CCD
Video
Q031
Main Sub
SD Det
30
Main for CCD
Composite 1
V1
Q021
Aux Input 1
S Det.
S-1 In
Aux
Inputs
Composite 2
8
S-Y1
10
S-C1
12
S Det.
S-2 In
S-Y2
S-C2
PST1
1
3
5
Q434
I015
1
78
Also, see Main/Component Sync

Separation Circuit Diagram
SCL1
I016
1
11
Q431
I003
2
Q437
10
Q016
Component 2 Y
SDA1
Sync Sep Comp 1
Sync Sep Comp 2
9
Component 1 Y
28
Aux Input 2
V2
Micro
Processor
Q433
Y In Det
Terminal PWB
SCL1
15
SDA1
14
CIRCUIT DESCRIPTION
23
Z1
Z0
U202
PinP TUNER (Mono)
Always PinP
Hi
Sub Video
PST1
14
53
Lo = MAIN
Hi = SUB
I005
Q210
Q403
Front Control PWB

Signal PWB 2 of 2
SIGNAL PWB 1 of 2
I401
PFT
CIRCUIT DESCRIPTION
Sync Circuit Block Diagram Explanation
I401 - Luminance Audio Selector IC
VOut1 PinP (Sub) Video to I005 Main/Sub Select IC and also to I001 microprocessor for Sub CCD.
V/YOut2 Main Video or S-Video (Y) to I005 Main/Sub Select IC and also to I001 microprocessor for
Main CCD.
VIn4 Component 1 Y in for CCD (480i only) and Auto Link.
VIn5 Component 2 Y in for CCD (480i only) and Auto Link.
Component Inputs (Y)
Component 1 (Y) to I015 Component 1 Sync Separator IC.
Component 2 (Y) to I016 Component 2 Sync Separator IC.
I015 - Component 1 Sync Separator IC
Vertical sync out goes to I001 microprocessor IC Comp 1 VFDet.
Horizontal sync out goes to I005 Main/Sub Select IC.
I016 - Component 2 Sync Separator IC
Vertical sync out goes to I001 microprocessor IC Comp 2 VFDet.
Horizontal sync out goes to I005 Main/Sub Select IC.
I005 - Main/Sub Select IC
Select control from I001 microprocessor SD Sel (Station Detect) Low = Main, High = Sub
Three separate sets of inputs/outputs, (only first two shown in graphic)
pin 3 Sub Video (In)
pin 5 Main Video (In)
pin 4 Sub/Main SD Det (Out)
pin 2 Comp 1 H sync (In)
pin 1 Comp 2 H sync (In)
pin 15 Comp 1/2 HFDet (Out)
pin 12 Sub AFC (In)
pin 13 Main AFC (In)
pin 14 Sub/Main AFC (Out)
I001 - Microprocessor IC
Sub video in on pin 30 for CCD.
Main video in on pin 28 for CCD.
Component 1 vertical frequency detect on pin 10, from I015.
Component 2 vertical frequency detect on pin 11, from I016.
Component 1/2 horizontal frequency detect on pin 22, from I005.
SD Select out on pin 50 to control I005 during Sub picture changes; example PinP CH up or down.
Main/Sub SD detect in on pin 24 from I005.
I406 - Main Component 1 / Component 2 Select IC
Selected Y output on pin 6.
79
ZP-94/95 SERIES CHASSIS MAIN/COMPONENT SYNC SEPARATION SIGNAL PATH

I207
I202
V.Sync Out
2
13
1
2
10 Select 3
I201
40
Q223
1
Main
Video/
Chroma
See Video
Signal Path
9
14
3
5
SIGNAL PWB
Select 3
4
2
Select 3
Hi : Main NTSC
Lo : Main Component
Q224
I203
H.Sync Out
18
20
Flex Converter
16
10
11
12
13
Select 4
Hi : Sub NTSC
Lo : Sub Component
MHW
8
See
Component
Signal Path
MVW
7
I405
PTS2
SHW
15
SVW
14
Sub H. Sync
Sub V. Sync
15
4
TERMINAL PWB
Q425
1
10 Select 4
Sub
Sync
Sel.
PTS2
9
I409
2
1
2
Q428
H.Out
I403
14
9 Select 4
3
V.Out Sub Video/ 40

Chroma
13
5
2
I406
I407
See Component
Signal Path (Main)
See Component
Signal Path (Sub)
Q442
1
Q415
I408
1
Sync
Sep.
V.Out
4
2
H.Out
See Video
Signal Path
80
CIRCUIT DESCRIPTION
U205
CIRCUIT DESCRIPTION
Component Sync Separation Block Diagram Explanation
I207 - Main Component Sync Separator
Y in on pin 1
H out on pin 2
V Out on pin 4
I203 - Sync Inverter
H sync from I207 is inverted and applied to I202.
I201 - Main Video Chroma Processor (NTSC)
Main Video in (Y) on pin 40
Vertical sync out on pin 13
Horizontal sync out on pin 14
I202 - Main Sync Selector
Selects either Main NTSC H and V sync or Main Component H and V sync.
Select 3 controlled by DAC2 line from I201 Main Video Chroma Processor IC.
Outputs selected H and V sync to I203 Sync Inverter IC.
I407 - Sub Component 1 / Component 2 Select IC
Selected Y output on pin 6.
I408 - Sub Component Sync Separator
Y in on pin 1
H out on pin 2
V Out on pin 4
H sync from I408 is inverted and applied to I405.
I403 - Sub Video Chroma Processor (NTSC)
Main Video in (Y) on pin 40
Vertical sync out on pin 13
Horizontal sync out on pin 14
I405 - Sub Sync Selector
Selects either Sub NTSC H and V sync or Sub Component H and V sync.
Select 4 controlled by DCOut line from I401 Luminance Audio Select IC.
Outputs selected H and V sync to I203 Sync Inverter IC.
81
CIRCUIT DESCRIPTION
Inverts incoming signals
Outputs (Main H, Main V, Sub H, Sub V) go to Flex Converter for PinP timing purposes.
Main H labeled MHW at Flex Converter
Main V labeled MVW at Flex Converter
Sub H labeled SHW at Flex Converter
Sub V labeled SVW at Flex Converter
DP-05 & DP-05F COMPONENT SYNC SEPARATION BLOCK DIAGRAM
82
CIRCUIT DESCRIPTION
ZP-94/95 COMPONENT SYNC SEPARATION BLOCK DIAGRAM EXPLANATION
Refer to the DP-05 and DP-05F Component Sync Separation Circuit Diagram
The only difference between the DP-05 & DP-05F and the DP-06 or DP-07 Component Sync Separation
Circuit Diagram is;
The DP-05 and DP-05F PinP circuit doesnt route the Component inputs to the PinP Signal route into the
Flex Converter. Therefore, the PinP in the DP-05 and DP-05F only produces NTSC inputs routed through
the
Selector IC.
The Sub Component Selector IC (I407) is not used.
The Sub Component Sync Separator IC (I408) is not used.
The Sub Component or Main NTSC Sync Selection IC (I405) is not used.
All else remains the same.
(See Next page for diagram).
83
ZP94/95 CHASSIS A.B.L. CIRCUIT DIAGRAM
RX32
SW +9V
QX13
RX34
PSZ2
RX33
RX35
DX02
ABL
45
IX01
Rainforest
IC
RX37
CX31
CX32
RX36
DX03
PSZ1
CX19
CX34
27 28
16 17
SDA2
SCL2
See uP
Data
Signal
Path
SDA2
SCL2
TH01
To Anodes
B+
High Voltage B+ 120V V2
ABL RH67
LH03
3
ABL Pull-Up
Resistors
RH58
Deflection B+ 120V V1
PSD3
Sw +12V
[ Current Path ]
Deflection PWB
DH33
CH25
RH59
RH56
Clamp
CH31
1
As Brightness goes Up, ABL Voltage goes Down. (Inverse Proportional)
84
CIRCUIT DESCRIPTION
To
Focus
To QH01
Collector of Horz.
Output Transistor
Signal
PWB
2H Video
PWB
or
Signal Sub
PWB
CIRCUIT DESCRIPTION
Automatic Brightness Limiter (ABL) Circuit Block Diagram Explanation
The ABL voltage is generated from the ABL pin of the Flyback transformer, TH01. The ABL pull-up
resistors are RH58 and RH59. They receive their pull up voltage from the B+ 120V(V2 ) for Deflection line
generated from the Power Supply via TP91 pin 13, rectified by DP11, filtered by CP33 and then routed
through the excessive current sensing resistor RP17.
ABL VOLTAGE OPERATION
The ABL voltage is determined by the current draw through the Flyback transformer. As the picture brightness becomes brighter or increases, the demand for replacement of the High Voltage being consumed is
greater. In this case, the flyback will work harder and the current through the Flyback increases. This in turn
will decrease the ABL voltage. The ABL voltage is inversely proportionate to screen brightness.
Also connected to the ABL voltage line is DH33. This zener diode acts as a clamp for the ABL voltage. If
the ABL voltage tries to increase above 12V due to a dark scene which decreases the current demand on
the flyback, the ABL voltage will rise to the point that DH33 dumps the excess voltage into the 12 line.
ACCL TRANSISTOR OPERATION
The ABL voltage is routed through the PSD3 connector, through the PSZ2 connector, to the base of QX13.
Under normal conditions, this transistor is nearly saturated. QX13 determines the voltage being supplied to
the cathode of DX05, which is connected to pin 45 of the Rainforest IC, IX01. During an ABL voltage
decrease, due to an excessive bright circumstance, the base of QX13 will go down, this will drop the
emitter voltage which in turn drops the cathode voltage of DX05. This in turn will pull voltage away from pin
45 of the Rainforest IC, IX01. Internally, this reduces the contrast and brightness voltage which is being
controlled by the I 2 C bus data communication from the Microprocessor arriving at pin 27 and 28 of the
Rainforest IC and reduces the overall brightness, preventing blooming.
SUB BRIGHTNESS ADJUSTMENT - I 2 C Alignment
The purpose for the Sub Brightness Adjustment alignment is to set up the Lowest DC level to which the
Brightness control voltage can be set. Again, this voltage is controlled internally within IX01 via I 2 C bus
data. The adjustment is performed within the Service Menu. To enter this adjustment menu, with the set
turned off, press and hold the Input button, then press the Power button. This will bring up a Service Menu.
Under the P.01 menu, the 1st selection is Sub Bright Adj. Selection is made using the pq buttons and
adjusting the data values are made using the tu buttons.
Sweep Loss Detection Block Diagram Explanation
The key component in the Sweep Loss Detection circuit is QN04. This transistor is normally biased off.
When the base becomes more negative, it will be turned on, causing the Standby 11V to be applied to two
different circuits, the Spot circuit and the High Voltage Drive circuit.
SPOT CIRCUIT
When QN04 is turned on, the 11V standby will be applied to the anode of DN11, forward biasing it. This
voltage will then pass through DN11, get zenered by DN09, and go to pin 2 of PSD3, where it will activate
the Video Mute circuitry Q022 - Q024 on the Signal PWB. This is done to prevent CRT burn. Another
input to this circuit is the I701 DAC3 line. This will activate when accessing certain adjustment parameters in
the service mode; i.e. turning off vertical drive for making CRT drive or cut-off adjustments.
85
CIRCUIT DESCRIPTION
ZP-94/95 SWEEP & AC LOSS DETECTION CIRCUIT
SW+12V
RN05
Vertical
Blanking
From
Pin 11 I601
RN03
QN02
RN04
See Deflection Power

Supply Circuit
Diagram
DN01
QN01
RN01
CN02
V. Blk.
CN01
DN02
SPOTPROTECT
DN03
RN02
DN14
24V P/P
DN15
RN10
RN07
RN10
SW+12V
Stby 11V
RN09
Horizontal
Blanking
From
Q755 Emitter
QN04
DN04
DN05
CN03
CN04
RN06
QN03
QN05
RN11
DN13
RN15
DN06
H. Blk.
High Voltage
Driver IC
IH02
RN08
RN13
14 Stops
Drive
RN12
PSD3
11.6V P/P
SPOT
Prevents CRT Burn
DN11
DN12
1 Drive
2
RN14
DN09
Horizontal
and
Vertical
Drive IC
QN08
H Drive
I701
QN08
DAC3 24
RH60
Stops High Voltage Drive

Signals From being
produced
when Sweep Loss is
detected.
QN07
When Vertical Drive is
turned Off during
adjustment, I2C.
Spot Inhibit
HVcc
R718
86
CIRCUIT DESCRIPTION
HIGH VOLTAGE DRIVE CIRCUIT
When QN04 is turned on, the 11V standby will also be applied to the High Voltage Drive IC IH02 pin 14
via RN15 and DN13. When this occurs, the IC will stop generating the drive signal that is used to produce
High Voltage via QH08, the High Voltage Driver. Again, this is done to prevent CRT burn, especially during
sweep loss.
CONCERNING QN04
There are several factors that can affect the operation of QN04; namely loss of vertical or horizontal blanking and spot killer or spot protect from a shutdown in the deflection power supply.
Loss of Vertical Blanking
When the 24Vpp positive vertical blanking pulse is missing from the base of QN01, it will be turned off,
which will cause the collector to go high. This in turn will cause QN02 to turn on, creating an increase of
current flow from emitter to collector and up through RN07, (which is located across the emitter base
junction of QN04), to the 11V standby supply. This increase of current flow through RN07 will bias on
QN04 and the events described previously will occur.
Loss of Horizontal Blanking
When the 11.6Vpp positive horizontal blanking pulse is missing from the base of QN05, it will be turned off,
which will cause the collector to go high. This in turn will cause QN03 to turn on, creating an increase of
current flow from emitter to collector, through RN06, and up through RN07. Again, this increase of current
flow through RN07 will bias on QN04 and the events described previously will occur.
SPOT PROTECT or SPOT KILLER
As mentioned earlier, when the deflection power supply goes into shutdown for whatever reason, a low
potential will be felt at the cathode of DN14, forward biasing it and causing current flow through RN07.
Once again, this increase of current flow through RN07 will bias on QN04 and the events described
previously will occur.
87
Troubleshooting
MAIN CHASSIS (POWER / DEFLECTION P.W.B.)
CONVERGENCE
HEAT SINK
SK01:
SERVICE
SWITCH
Digital
Convergence Unit
IK04
IK05
PSD1
IK01
QK01
PCR
PCG
PCB
PDF
QF06
QH01
TH01
YOKE PLUGS
REAR
VIEW
PMR
R630
V.Size
Adj.
PMB
D752
D656
RH44
D657
R686
H.Size
Adj. HD
R683
H.Size
Adj.
FBT
PMG
High Voltage ADJ.

RH44
Q657
Q777
DP37
Red LED
DP29
+B 120V Green LED
DP01
PQD2
PDC1
Q701
I601
PSD1
88
PSD2
PSD3
TP91
IP01
PQD1
Troubleshooting
SMALL SIGNAL P.W.B. DIAGRAM
MICROPROCESSOR
PFS
IC01
PR
I001
PP1
PL
2H
VIDEO
PWB
SURROUND PWB
I012
I011
DIGITAL BOARD
HC4051
I007
LINE COMB
PWB
I010
U201
Main
Tuner
U205
FLEX
Conv.
and
PinP
Unit
U202
PinP
Tuner
U204
3D/
YC
QS4
TERMINAL PWB
REAR
VIEW
89
Troubleshooting
CRT AND CONTROL P.W.B. DIAGRAM
PGV
P851
R879
DAG
GND
PTSG
SHORT TO
KILL THE
COLOR
P852
Cathode
E831
GREEN
P801
W801
PRV
PTSR
SHORT TO
KILL THE
COLOR
PTSB
SHORT TO
KILL THE
COLOR
R829
DAG
GND
P802
Cathode
E801
RED
P8A1
W801
PVB
DAG
GND
E8A1
P8A2
CATHODE
BLUE
90
Troubleshooting
CHASSIS SUB POWER P.W.B.
10
PQS1
PQU1
I905
D912
Audio F SW +29V
GREEN
D927
STBY +7V
GREEN
D931
SW +5V
GREEN
I907
D949
STBY +11V
GREEN
I906
PQU2
11
PA
PQD1
PQD2
PQS2
1
1
2
F901
6 Amp
PQS4
9 1
S901
3
1
D901
REAR
VIEW
D903
IC POWER
MONITOR RED
I901
T901
S904
SWITCHING
TRANSFORMER
S903
S902
= RED or GREEN LED USED FOR VISUAL TROUBLESHOOTING
91
Troubleshooting
CONTROL P.W.B.
MENU
PFJ
SOURCE
VOL VOL +
CH CH +
POWER
PFV
SM09
92
Troubleshooting
No Raster
Is Power LED on Control Panel on?

No
Is Red LED Blinking on SMPS?
Yes
No
Turn off power wait (3) seconds, turn ON carefully

inspect all Green LEDs on SMPS.
Did all 5 LEDs turn off at the same time?
Yes
Yes
Find which LED fails to light or dims first on SMPS.

D949-SMPS STBY +11v
Check D918,I906,I007,I009
D931-SMPS SW +5v
Check D918,I907,I011,I012
D927-SMPS STBY +7v
Check D918,I905,I008,I010
D912-SMPS SW +29v (Audio)
Check E992,D910,IC01
Is voltage at pin(4) of I901 14v-18v?

No
Yes
Check D904,R905,R906,C907,F901,R902
No
Has protector E991 blown?

Yes
Check I901,D961,R918,R919,Q901
Replace E991
No
Replace I901
Check R918,R919
Does raster appear with G and K of

Q905 shorted?
Yes
Replace Q905
No
Check Q905,D921,D908,I902,Q902,D923
Is Click of Relay heard

No
Is the voltage at pin(51) and (33) of I0013.3v?

Yes
No
Is Voltage at pin(53) of I001 low?
Is the voltage at PQS2 pin(1) 7volts?
Yes
Yes
Check Q003,Q004,D922,S901,Q002
Yes
No
Check Q029,D035,L004
No
D927-SMPS STBY +7v

Check D918,I905,I008,I010
Is voltage at pin(23) of I001"AC Clock" in?

No
Check Q008,Q009,I904,D909
Yes
Check I001 pin(54)

Does reset occur?
Yes
Check I001 pin(62)

is 4mhz present?
Yes
Check I002
Replace I001
No
Check I001 pin(63)

Is 1.6v present?
No
No
Replace I001
Yes
Replace X001
Replace I006
To page ____
Inspect Red LED (DP37) on Deflection, Blinking?
Yes
Turn off power wait (3) seconds, turn ON ,carefully

inspect Green LED.
Does the Green LED tun off at the same time?
Yes
No
Is voltage at pin(4) of IP01 14v-18v?

No
Yes
Check EP98,DP11,Q777,QH01,TH01,DH11, on
deflection module.
Has protector EP01 blown?

No
Does raster appear with G and K of

QP01 shorted?
Yes
Yes
Check QP01/ Replace QP01
Check IP01,
RP10,RP11,RP12
No
Check IP01,DP04&5
RP10,RP11,RP12
Replace EP91
No
Is the base of Q751 normal?

Check PQD1 for 120vac
No
Yes
Check I701 pin(15) H-out,pin(8) Hvcc,

QP04,DP35,DP36
Yes
Check DP04&5, Rp02&3,CP05

RP10,RP11,RP12
Are voltages of both ends of T751(primary side)

normal?
No
Yes
Check Q777,QH01,T751,T752
No
CheckVR923 on SMPS
Check T751,R754,R755
93
Appendix 1
Zenith D3 Flexcoverter Description
Analog TVs use interlaced scanning and Digital TVs use progressive scan. The 94/95 series TVs are
Digital TVs, so therefore they use progressive scan.
Zeniths new D3 FLEXCONVERTER allows the 94/95 Series TVs to accept and display NTSC signal
sources plus all ATSC digital to analog converted signal sources. The flexconverter looks at the signal
coming into the TV set and converts it to best fit the TVs display area or allows it to pass through unaffected. Thus, the very best possible picture can be displayed on the screen from any signal source. The new
D3 Flexconverter is smart enough make the input source signal best fit the 4:3 display aspect ratio of the 94/
95 series RPTVs, since it must make the proper display decision it is much more than a line doubler; it is a
video processor. A line-doubled picture would simply be compressed in the 16:9 format thus causing the
lines to thicken, overlap and distort the picture.
In Diagram A, a DTV signal of 4:3 and 480p is allowed to pass through unaffected, since 480p is the native
format for the 95/95 series RPTV. A standard broadcast or cable signal at 270i will be processed by the
D3 Flexconverter and upconverted to be displayed at 1080i in a 4:3 aspect ratio. The 480i signal from a
converted digital to analog source such as a DVD or DBS is processed and converted to 480p.
In Diagram B, the DTV signals output by a digital STB of 480i, 480p and 720p with an aspect ratio of 16:9
are changed to 480p, but, as a result of the smaller vertical displayed image size of the 16:9 picture, the
actual viewable scan lines are 360p AVSL (Active Video Scan Lines).
In Diagram C, the 16:9 by 1080i is processed and displayed at 810i in the vertically compressed picture
image area of the 4:3 screen. The 810i of AVSL meets the CEA requirements to be labeled HDTV Monitor
(HD Capable).
So therefore, the NEW D3 Flexconverter makes the 94/95 series RPTVs perform at optimum levels on
either analog or D to A converted signals.
94
Appendix 1
DIAGRAM A
Signal
ACCEPTED
*AVSL:
Active Video
Scan Lines
DTV at 480p
in 4:3 Aspect Ratio
4:3 ASPECT RATIO

OF IMAGE DISPLAY
IN 4:3 SCREEN
480p
NTSC at 270i
in 4:3 Aspect Ratio
(Broadcast or Cable)
D3
FC
NTSC at 480i
in 4:3 Aspect Ratio
(DVD)
D3
FC
1080i
Signal
ACCEPTED
DTV at 480i
480p
720p
in 16:9 Aspect Ratio
*AVSL of
1080i Lines
*AVSL of
480p Lines
480p
DIAGRAM B
480i
480p
720P
Image
DISPLAYED
16:9 ASPECT RATIO OF

IMAGE DISPLAY IN 4:3
SCREEN
D3
FC
480p
DIAGRAM C
Signal
ACCEPTED
480p
Lines
*AVSL OF 360p
Lines
Watchable Picture
Image
DISPLAYED
16:9 ASPECT RATIO OF

IMAGE DISPLAY IN
4:30SCREEN
1080i
DTV AT 1080i IN
16:9 ASPECT RATIO
Image
DISPLAYED
D3
FC
1080i
1080i
Lines
*AVSL of 810i
Lines
Watchable Picture
95

LG Zenith C-Line Zp94 95 Projection TV Training Manual 2000 (Et)

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

LG Zenith C-Line Zp94 95 Projection TV Training Manual 2000 (Et)

Uploaded by

Copyright:

Available Formats

2000 C-Line Projection TV

Zp94 & ZP95

7HFKQLFDO 7UDLQLQJ 0DQXDO

201 JAMES RECORD ROAD HUNTSVILLE, AL. 35824

Good earth ground

The exclamation point within an equilateral triangle is intended

Only factory-specified CRT anode connectors must be used.

It is essential that the service personnel have available an accurate and

The lightning flash with arrowhead symbol within an equilateral

When the high-voltage circuitry is operating properly, there is no possibility

When troubleshooting and making test measurements in a product with a

Refer to HV, B+, and shutdown adjustment procedures described in the

The pictorial representation of a fuse and its rating within an

FIRE AND SHOCK HAZARD

Place this probe

Be sure that all components are positioned to avoid a possibility of

Use only the recommended factory replacement tubes.

TIPS ON PROPER INSTALLATION

Never install any receiver in a closed-in recess, cubbyhole, or closely

Soldering must be inspected to discover possible cold solder joints,

Avoid conditions of high humidity such as: outdoor patio installations

Check for physical evidence of damage or deterioration to parts and

Avoid placement where draperies may obstruct venting. The customer

Wall- and shelf-mounted installations using a commercial mounting kit

Caution customers against mounting a product on a sloping shelf or in a

A product on a roll-about cart should be stable in its mounting to the cart.

Caution customers against using extension cords. Explain that a forest of

Verify that all protective devices such as insulators, barriers, covers,

No lead or component should touch a receiving tube or a resistor rated at

After re-assembly of the set, always perform an AC leakage test on all

Add JIG to check Hi

CHASSIS HIGH VOLTAGE LIMITER

CHASSIS FLYBACK PROTECTION

Perform the following when the

3. Remove the connector slowly by pulling it away

/(66 7+$1 PP

470 mVrms, 47 k Ohm

Stere o Audio O utput:

470 mVrms, 1 k Ohm

60" Series Models

<<figure 2. Control Panel>>

<<figure 3 Rear Connection Panel>>

SETTING RANGE DESCRIPTIO N

3C-C3 Sub Brightness

Y Motion Detection Gain

Y Motion Detection Gain

T A1300 33.75khz M 3375

Characteristic Switch 0 = Low Frequency, 1 = High Frequency

(480i, 480p, 1080i, 720p)

Y Vertical Enhance Gain

(480i, 480p, 1080i, 720p)

Y Vertical Nonlinear Peaking

SETTING RANGE DESCRIPTIO N

SETTING RANGE DESCRIPTIO N

Sharpness (Center Adjustment)

Sharpness (Center Adjustment)

Sharpness (Center Adjustment)

Sharpness (Center Adjustment)

Sharpness (Center Adjustment)

Color (Center Adjustment)

Color (Center Adjustment)

Color (Center Adjustment)

/(66 7+$1 PP