Solar Report

ACKNOWLEDGEMENT
The satisfaction that accompanies a successful completion of any task would be

incomplete without the mention of the people who made it possible, whose constant guidance
and encouragement crowns all the efforts with success. We would like to express our sincere
gratitude to all who have been associated with this project and have stood by us at all times.
First of all I convey my gratitude for the valuable guidance and constant encouragement
by my project guide Mr. S N Prasad, Associate Professor, Dept of Electronics and
Commnication, who showed great interest in my project and gave me ample guidelines for the
proceedings to handle the project in a systematic manner..
I would like to thank Mr. Pras!ant " #os!i !"#oordinator, $%&' IT(, )angalore, for
helping in completing the project and guiding us to organi*e the report in a systematic manner
(y profound sense of gratitude to Dr. S.S.Man$i %OD, Dept. of Electronics and
Commnication, &E"A 'TM and other staff members and non teaching staff members of the
+ept. of %,# who provided me the knowledge throughout my course.
I express my sincere gratitude to the Principal, Dr. &anaPratap &edd(, Principal,
&E"A 'TM, and the Mana)ement of &E"A 'TM, who had given a chance in pursuing my
post graduation studies in their esteemed institution at $%&' IT(..
-ast but definitely not the least I would like to thank my parents and friends who have
always supported me in every path of life.
"is!*anat! c.
ii

Abstract

To explore integrated solar energy harvesting as a power source for low power systems, an array
of energy scavenging photodiodes based on a passive-pixel architecture for CMOS imagers has
been fabricated together with storage capacitors implemented using on-chip interconnect in a
0.35- m bulk process. Integrated vertical plate capacitors enable dense energy storage without
limiting optical efficiency. Tests were conducted with both a white light source and a green laser.
Measurements indicate that 225 W/mm. The combination of integrated solar energy scavenging
and storage can enable a new generation of low cost, long lifetime, small volume systems for
future wireless sensor networks or RFID applications. For a 25 mm total photodiode area
consisting of 3 diodes in series with the metal storage capacitances for each diode connected in
parallel, D1, D2, and D3 can supply enough energy for the DSP to produce 687, 745, and 903
output samples respectively. This paper describes an array of photodiodes, modeled after a
passive-pixel imager, integrated together with storage capacitors in a commodity CMOS process.
Also described is the potential of this approach to increase the lifetime of wireless sensor nodes.
To reduce system cost and volume it is desirable to integrate energy harvesting and storage with
data acquisition, data processing, and communication circuits.Recent advances in very low
power signal processing architectures for sensors has created the opportunity to use CMOS
photodiodes, similar to those used in digital cameras, for solar energy harvesting. Moreover, the
increase in interconnect capacitance as CMOS processes scale provides an opportunity to store
the harvested energy without requiring battery materials to be integrated on-chip.

List of Figures
Fig 1.1 Low power wireless system 2
Fig 2.1 Block Diagram of integrated solar energy harvesting and storage 12
Fig 2.2 Flowchart Diagram of integrated solar energy harvesting and storage 13
Fig 3.1 the emission of electron from metal plate 14
Fig 3.2 photovoltaic effect in different conditions 15
Fig 3.3 DC motor 21
Fig 3.4 DC motor forward-reverse control 23
Fig: 3.5 Typical Application Circuits 25
Fig: 3.6 LDR Circuits 25
Fig: 3.7 Resistance As Function Of Illumination 26
Fig 3.8 stepper motor 27
Fig: 3.9 Block Diagram Of ADC 29
Fig: 3.10 The Magnitude Of The Error Ranges From Zero To 1 LSB 31
Fig: 3.11 Pin diagram of ADC0803 32
Fig: 3.12 Functional Block Diagram Of ADC0803 32
Fig 3.13 Light dependent resistor 36
Fig 3.14 single axis solar panel 38
Fig 3.15 double axis tracker 38
Fig 4.1 Model Sim Simulation Environments 42
Fig 4.2 Basic simulation flow 45
Fig: 5.1 Launching ISE Text Editor to edit SOLAR.vhd 52
Fig: 5.2 Internal RTL Diagram of solar.vhd 52
Fig: 5.3 Mux Register Schematic Diagram 53
Fig: 5.4 Program Generation Report 53
Fig: 5.6 Simulation Results of solar module 54
Fig 5.7 Simulation results of LDR_sensor1 54
Fig 5.8 RTL block diagram of LCD_data out 55
List of Tables
Table 5.1 Model sim Modes of Operation 42

Table of Contents

Acknowledgements Error!
Bookmark not defined.
Abstract 1
List of Figures iii
List of Tables iv
Chapter 1
PREFACE 1-10
1.1 Introduction 1
1.2 Background of Project 4
1.3 Objective 5
1.4 Problem Definition 5
1.5 Problem Statement 6
1.6 Existing System 6
1.7 Proposed System 8
1.8 Project Plan 9
1.9 Organization of the Report 10
Chapter 2
BLOCKDIAGRAM & FLOWCHART 12-13
2.1 Block Diagram of Project 12
2.2 Flowchart of Project 13
Chapter 3
LITERATURE SURVEY 14-39
3.1 Fundamentals of Photovoltaic System 14
3.1.1 Photovoltaic cell 14
3.1.2 The Photovoltaic Effect 15
3.1.3 Efficiency 16
3.2 Types of photovoltaic System 17
3.3 Solar Position Algorithm for Solar Radiation Applications 18
3.3.1 Solar Azimuth angle 19
3.3.2 Solar zenith angle 20
3.3.3 Solar elevation angle 20
3.4 Dc Motors 21
3.4.1. Brushed Dc Electric Motor 21
3.5 Connection Types 22
3.5.1. Series Connection 22
3.5.2. Shunt Connection 22
3.5.3. Compound Connection 23
3.6 Dc Motor Forward Reverse Control 23
3.6.1 Circuit working Description 24
3.7 Function of LDR 24
3.7.1 Spectral Response 26
3.7.2 Sensitivity 26
3.8 Stepper motor 26
3.9 Analog to Digital Converter (ADC) 29
3.9.1 Quantization Error 30
3.10 Light-Dependent Resistor 35
3.10.1 ADC 36
3.10.2 Driver Circuit 36
3.11 Solar Cell Array 36
3.11.1 Active Solar Trackers 37
3.11.2 Types Of Solar Trackers 37
3.11.2.1 Single Axis Solar Trackers 37
3.11.2.2 Dual Axis Trackers 37
3.12 Battery 39
Chapter 4
TOOLS REQUIRED 40-51
4.1 Software Tools 40
4.1.1 Xilinx ISE 13.2i 40
4.2 ModelSim 6.3 C 42
4.2.1 Model Sim Library 44
4.2.2 Model Sim modes of operation 44
4.2.3 Basic simulation flow 45
4.3 Evolution of Programmable Logic Devices 46
4.3.1 Field Programmable Gate Array (FPGA) 47
4.3.2 Applications 47
4.3.3 General workflow when working with FPGAs: 48
4.3.4 Internal logic 49
4.3.5 Internal RAM 49

4.3.6 FPGA pins 50
4.3.7 IO banks 50
4.3.8 FPGA power 50
4.3.9 Clocks and Global lines 50
4.3.10 Features in common with FPGAs 51
Chapter 5
SIMULATION RESULTS 52
Chapter 6
CONCLUSION AND FUTURE SCOPE 56-58
6.1 Conclusion 56
6.2 Future Scope 56
6.3 Advantages 57
6.4 Project Limitations 57
6.5 Applications 57
BIBLIOGRAPHY 59
Design and implementation of solar robot controlling and storage of energy based on FPGA

Dept of ECE, REVAITM Page 1

CHAPTER 1
PREAMBLE
1.1 Introduction
The emerging application of wireless sensor networks continues to drive the need for ultra-low
power system design. Wireless sensors can enable a variety of applications including interactive
environments for medicine, environmental monitoring networks, military target tracking, and
detection of chemical and biological weapons. In many of these wireless systems, the power
source is a bottleneck that limits system lifetime and performance, adds manufacturing cost, and
increases system volume and maintenance expenditures. Delivering power to wireless sensor
network nodes is a significant system design challenge. Solar energy harvesting has been
proposed to extend the lifetime of these networks beyond the limitations which have been
previously imposed by batteries. In many of these wireless systems, the power source is a
bottleneck that limits system lifetime and performance, adds manufacturing cost, and increases
system volume and maintenance expenditures Prior works have successfully demonstrated
powering wireless systems through discrete photovoltaic cells together with separate energy
storage devices using board level designs.
To reduce system cost and volume it is desirable to integrate energy harvesting and
storage with data acquisition, data processing, and communication circuits. Recent advances in
very low power signal processing architectures for sensors has created the opportunity to use
CMOS photodiodes, similar to those used in digital cameras, for solar energy harvesting.
Moreover, the increase in interconnect capacitance as CMOS processes scale provides an
opportunity to store the harvested energy without requiring battery materials to be integrated on-
chip. This Project describes an array of photodiodes, modeled after a passive-pixel imager,
integrated together with storage capacitors in a commodity CMOS process. Also described is the
potential of this approach to increase the lifetime of wireless sensor nodes. The system consists
of sensors that can observe the environment, an analog-to-digital converter (ADC) that can
quantize the analog signal from the sensors, a digital signal processing (DSP) core that can
analyze and encode the quantized data and a transceiver (RF) so that the node can transmit and
receive information


.

Fig: 1.1 Low power wireless system
Light energy is converted to electrical energy through a photodiode and mechanical
vibrations are converted to electrical energy by an electromechanical transducer. A multiplexer
(mux) is used to switch between energy sources. The systems energy gathering ability will
depend on environmental conditions, which can change over time. Hence, the scavenged energy
needs to be regulated before being used by these functional blocks.Fig.1.1 shows a block diagram
of a typical wireless sensor node, which is powered by a combination of energy scavenging and
battery technology. The system consists of sensors that can observe the environment, an analog-
to-digital converter (ADC) that can quantize the analog signal from the sensors, a digital signal
processing (DSP) core that can analyze and encode the quantized data and a transceiver (RF) so
that the node can transmit and receive information. Light energy is converted to electrical energy
through a photodiode and mechanical vibrations are converted to electrical energy by an
electromechanical transducer. A multiplexer (mux) is used to switch between energy sources. The
systems energy gathering ability will depend on environmental conditions, which can change
over time. Hence, the scavenged energy needs to be regulated before being used by these
functional blocks.
In general, these types of systems work on very low duty cycles, where the sensor node
will be in a rest state for the majority of the time. Periodically, the sensor node will wake up, take



a snapshot of the environment measured by its sensors, perform its computations, and transmit
any data before returning back to the rest state.
Each of the functional blocks shown in Fig.1.1 has its own power requirement. Previous
work has shown that efficient ADCs and DSPs can achieve average power levels in the sub-
milliwatt range. However, low power ADCs usually suffer from diminished power supply
rejection. Minimizing the voltage ripple on the power supply for the ADC is important for
maintaining accuracy. The RF block typically requires significantly more peak power than the
other system blocks, and the DSP has the most relaxed supply ripple requirements due to the
robustness (large noise margin) of the digital circuitry. For Low duty cycles, the average power
for the system can be under 5microwatts.
The integration of the photovoltaic cells along with analog and digital signal processing
circuits is of interest in this work. The scaling of a photovoltaic cell from large, standalone arrays
to the integrated circuit level will impact the cells output power, efficiency, optimal load
resistance, and optical properties of the photodiode. Energy harvesting systems with high power
requirements may require a significant area allocation for integrated photodiodes. Although
integrated photodiodes can also double as power supply bypass capacitors, the additional cost
associated with the photodiodes footprint could potentially limit its usefulness to larger feature
size technologies. True integration of photodiodes and active circuitry on the same die may
require covering the active circuitry with a metal cap to block the incident light from potentially
degrading signal integrity. A substrate trench, forming a barrier, can also be employed to help
limit the lateral photocurrent traveling from the photodiodes to the active circuitry.
The construction of the storage capacitance and routing for the photodiodes must not
degrade the optical efficiency (OE), which is defined as the fraction of incident light onto the
chips surface which reaches the photodiode . In general, the optical efficiency is influenced by
three loss factors: reflection loss, absorption loss, and critical angle loss. Once photons reach the
photodiode, the quantum efficiency (QE) determines how many photons will generate electron-
hole pairs. The product of OE and QE should be maximized by the geometry of the photodiode
and storage capacitance to maximize both the energy harvesting ability and storage capacity.


An ultracapacitor is an electrochemical capacitor typically made from carbon and with a
high energy density due to a large surface area to volume ratio for the internal material. It has
been previously shown that these ultra-capacitors could reduce the high power demands on
batteries in wireless systems by storing energy harvested from environmental sources . One
advantage of ultra-capacitors is the high number of charge/discharge cycles they can undergo
before deterioration, which is approximately 100 000 cycles (roughly 100 better than
contemporary battery technologies). Ultra capacitors thus far have primarily been used for hybrid
vehicle applications with individual capacitor sizes reaching thousands of farads. In this section,
we explore and compare the effect of technology scaling on interconnect capacitance density and
ultra capacitor density.
1.2 Background of Project
Solar power is an alternative technology that will hopefully lead us away from our petroleum
dependent energy sources. The major problem with solar panel technology is that the efficiencies
for solar power systems are still poor and the costs per kilo-watt-hour (kwh) are not competitive,
in most cases, to compete with petroleum energy sources. In India, the sun is always directly
overhead and its intensity do not varies by season. This give a lot more advantage for us to use
solar power compare with the place that have season. There are two most common type systems
that always use for small building generated system:-
1. The solar thermal system
2. The photovoltaic system
The solar thermal system operate by convert the radiant energy of the sun into heat then
use that heat to provide useful electric energy. On other hand, the photovoltaic system converts
directly the sun radiant into useful electric energy, which can be used as most electrical energy in
used today. Solar power (photovoltaic) systems are a sustainable way to convert the energy of
the sun into electricity. The expected lifetime of a system is 25-30 years. This show how efficient
is this system even it is quite expensive to install this system at the beginning.


Amount of power produced by a photovoltaic panel depends upon the amount of sunlight
it is exposed to. In other word, more light means more power. In order to capture more light
produce by sun, the photovoltaic panel must constantly orient itself to the sun location. When the
photovoltaic panel does not intercept as much light as it can, it will not produce as much power
as it can. Fixed photovoltaic panel do not aim directly to the sun due to the constant motion of
earth. As the result, the power produce by the system is less then it capable producing. To
overcome this problem, the tracking system can be installed in order that the panel continually
adjusts so that the panel is always aim directly at the sun. As the result, Photovoltaic panel are
able to collect the maximum amount of sunlight and produce the most power possible.
1.3 Objective
The objective of this project is to develop tracking mechanism for photovoltaic panel to
maximize the generation of electrical energy. The objective of the project is to develop the
system that can constantly tracking the sun and storing the generated energy using CMOS logic
process.
1.4 Problem Definition
To explore integrated solar energy harvesting as a power source for low power systems, an array
of energy scavenging photodiodes based on a passive-pixel architecture for CMOS imagers has
been fabricated together with storage capacitors implemented using on-chip interconnect in a
0.35- m bulk process. Integrated vertical plate capacitors enable dense energy storage without
limiting optical efficiency. Light energy is converted to electrical energy through a photodiode
and mechanical vibrations are converted to electrical energy by an electromechanical transducer
.an analog-to-digital converter (ADC) that can quantize the analog signal from the sensors, a
CPLD/FPGA core that can analyze and encode the quantized data and a transceiver (RF) so that
the node can transmit and receive information. The systems energy gathering ability will depend
on environmental conditions, which can change over time. The scavenged energy needs to be
regulated before being used by these functional blocks Delivering power to wireless sensor
network nodes is a significant System design challenge.


Solar energy harvesting has been proposed to extend the lifetime of these networks beyond the
limitations which have been previously imposed by batteries. Prior works have successfully
demonstrated powering wireless systems through discrete photovoltaic cells together with
separate energy storage devices using board level designs.
1.5 Problem Statement
Now, We can formally state our problem to explore integrated solar energy harvesting as a
power source for low power systems, to design and implement the solar energy harvesting
system on FPGA to take sunlight as input for LEDs and convert those signals to digital and to
target the FPGA to analyze the intensity of the light and rotate the panel accordingly and store
energy into battery. The system consists of sensors that can observe the environment, an analog-
to-digital converter (ADC) that can quantize the analog signal from the sensors, Light energy is
converted to electrical energy through a photodiode and mechanical vibrations are converted to
electrical energy by an electromechanical transducer. A multiplexer (mux) is used to switch
between energy sources. The systems energy gathering ability will depend on environmental
conditions, which can change over time. Hence, the scavenged energy needs to be regulated
before being used by these functional blocks.
1.6 Existing System
Solar energy is the most readily available source of energy. It is free. It is also the most important
of the non-conventional sources of energy because it is non-polluting. We are focusing on the
Existing which uses embedded / microcontroller hardware technologies to control the system to
capture the maximum energy from sun light. In the existing system, Solar photo voltaic (SPV)
can be used to generate electricity from the sun. Silicon solar cells play an important role in
generation of electricity. While the output of solar cells depends on the intensity of sunlight and
the angle of incidence, and The solar panels must remain in front of sun. But due to rotation of
earth those panels cant maintain their position always in front of sun. This problem results in
decrease of their efficiency in storing the power. Delivering power to wireless sensor network
nodes is a significant System design challenge. Solar energy harvesting has been proposed to
extend the lifetime of these networks beyond the limitations which have been


previously imposed by batteries. Prior works have successfully demonstrated powering wireless
systems through discrete photovoltaic cells together with separate energy storage devices using
board level designs. The system consists of sensors that can observe the environment, an analog-
to-digital converter (ADC) that can quantize the analog signal from the sensors, a digital signal
processing (DSP) core that can analyze and encode the quantized data and a transceiver (RF) so
that the node can transmit and receive information.
The layout and design of an integrated energy scavenging photodiode must balance
several competing factors. The charge generated in the depletion region of the photodiode is
meant to be stored in on-chip capacitors; therefore the physical layout of the diodes should
facilitate both the solar energy harvesting and capacitive energy storage. The light that reaches
the photodiodes depletion region must first pass through the passivation layers and avoid the
metal storage capacitance, which is constructed on top of the diode to minimize area. A figure of
merit (FOM) is needed in order to quantitatively assess the performance of the photodiodes. The
FOM used here is also known as the fill factor, which is defined as the maximum output power
obtainable divided by the product of the open circuit voltage and the short circuit current , for a
given light intensity schematic for a photodiode under illumination delivering power to a load
resistance on the left, along with an curve shown on the right. The maximum output power is the
product of and which are in general functions of the incident light intensity. Graphically, the
figure of merit can be seen as the ratio of the two rectangles and a FOM equal to one would be
ideal. To explore the photodiode design tradeoffs experimentally, three different geometries were
fabricated and tested. the top view layout for the three photodiodes along with a layer key. The
first design, photodiode D1, and is similar to a passive pixel structure used for a CMOS image
the p-substrate and n-well form the diode. The second photodiode design D2 This structure has
the addition of inter digitized p-diffusion and n-diffusion fingers inside the n-well.

These fingers help to form the additional p-diffusion to n-well diodes, which can be
wired in parallel with the well-substrate diode. The final design D3. The D3 layout is similar to
the D2 layout except the n-diffusion fingers are replaced with p-diffusion fingers allowing for
more depletion region area and energy harvesting ability. The integration of the photovoltaic
cells along with analog and digital signal processing circuits is of interest in this work. The


scaling of a photovoltaic cell from large, standalone arrays to the integrated circuit level will
impact the cells output. Power, efficiency, optimal load resistance, and optical properties of the
photodiode. Energy harvesting systems with high power requirements may require a significant
area allocation for integrated photodiodes. Integrated photodiodes can also double as power
supply bypass capacitors; the additional cost associated with the photodiodes footprint could
potentially limit its usefulness to larger feature size technologies. True integration of photodiodes
and active circuitry on the same die may require covering the active circuitry with a metal cap to
block the incident light from potentially degrading signal integrity.
A substrate trench, forming a barrier, can also be employed to help limit the lateral
photocurrent traveling from the photodiodes to the active circuitry. The construction of the
storage capacitance and routing for the photodiodes must not degrade the optical efficiency (OE),
which is defined as the fraction of incident light onto the chips surface which reaches the
photodiode. In general, the optical efficiency is influenced by three loss factors: reflection loss,
absorption loss, and critical angle loss. Once photons reach the photodiode, the quantum
efficiency (QE) determines how many photons will generate electron-hole pairs.
Problems with existing methods:
Microcontroller based systems can be existing but they dont have Automatic Sun Tracking
System by getting the maximum power in the day time.

1.7 Proposed System
Thus to get a constant output, we are implementing an automated system which should be
capable to constantly rotate the solar panel. By using the VLSI / FPGAs technology to
overcome the above problem and make the system intelligently according to our requirements
with a less complexity. The unique feature of this proposed system is that instead of taking the
earth as its reference, it takes the sun as a guiding source with the use of LDRs. By using LDRs
as its reference, The use ADC to convert the analog signal into digital .it takes the sun as a
guiding source. Depends on the constantly monitor the sunlight and rotate the panel towards the
direction where the intensity of sunlight is maximum. A motor is used to rotate the panel. The
hardware complexity is simple and low power is needed for it, and reduces the cost as well. The
advantage of proposed system can be applicable in all the solar energy systems.


The relative sensitivity of a photoconductive cell is dependent on the wavelength (color)
of the incident light. Each photoconductor material type has its own unique spectral response
curve or plot of the relative response of the photocell versus wavelength of light. The sensitivity
of a photo detector is the relationship between the light falling on the device and the resulting
output signal. Two cadmium sulphide (cds) photoconductive cells with spectral responses similar
to that of the human eye. The cell resistance falls with increasing light intensity. Applications
include smoke detection, automatic lighting control, batch counting and burglar alarm systems.
Each photoconductor material type has its own unique spectral response curve or plot of
the relative response of the photocell versus wavelength of light. Light energy is converted to
electrical energy through a photodiode and mechanical vibrations are converted to electrical
energy by an electromechanical transducer. The Analog-to-Digital Converter (A/D Converter or
ADC) has both analog and digital functions; it is a mixed-signal device. Many of us consider the
ADC to be a mysterious device. It can, however, be considered very simply to be the instrument
that it is: a device that provides an output that digitally represents the input voltage or current
level. Most ADCs convert an input voltage to a digital word, but the true definition of an ADC
does include the possibility of an input current. An ADC has an analog reference voltage or
current against which the analog input is compared. This process continues through the entire
input range and the error plot is a saw tooth. The maximum error we have here is 1 LSB. This 0
to 1 LSB range is known as the quantization uncertainty because there are a range of analog
input values that could have caused any given code and we are uncertain as to exactly what the
input voltage was that caused a given code.
1.8 Project Plan
This project work is to design and implement the solar energy harvesting system on FPGA to
take sunlight as input for LEDs and convert those signals to digital and to target the FPGA to
analyze the intensity of the light and rotate the panel accordingly and store energy into battery.
The system consists of sensors that can observe the environment, an analog-to-digital converter
(ADC) that can quantize the analog signal from the sensors, Light energy is converted to
electrical energy through a photodiode and mechanical vibrations are converted to electrical


energy by an electromechanical transducer. A multiplexer (mux) is used to switch between
energy sources.
Feasibility Study
A detailed feasibility study was conducted to know the technical and financial feasibility
of the project and it was found that the project is feasible to design, develop, use, and maintain in
all respects.
Requirement Analysis and Project Planning
Before starting the design of the project, in detail the requirements of the project is analyzed
which includes system requirement specification, software and hardware requirements and after
project planning is done with the help of requirement analysis.
Coding
The coding is done according to the design strategy i.e., code is done according to the
module wise. It is done by using VHDL language which makes use of Xilinx 13.2.i.
Testing
The program is tested by giving encrypted output to decryption module as an input and it
should produce back original data.
1.9 Organization of the Report
Chapter 1: It contains Introduction and Motivation of the project.
Chapter 2: It describes the block diagram and flowchart of solar energy harvesting.
Chapter 3: It contains literature survey of the project
Chapter 4:It includes information about the language and tool used


Chapter 5: It contains the synthesis results like top module input output signals, RTL
5

schematic, technology schematic and simulation result given by ISIM..
Chapter 6: It includes the information about advantages and dis-advantages and. conclusion part
of the project
Report also contains the bibliography and appendix-A



CHAPTER 2
BLOCKDIAGRAM & FLOWCHART
2.1 Block Diagram of Project

Fig: 2.1 Block Diagram of integrated solar energy harvesting and storage
The cell resistance falls with increasing light intensity. Applications include smoke detection,
automatic lighting control, The sensitivity of a photo detector is the relationship between the
light falling on the device and the resulting output signal. The Analog-to-Digital Converter (A/D
Converter or ADC) has both analog and digital functions, it is a mixed-signal device as shown in
Fig 2.1 . Many of us consider the ADC to be a mysterious device. The digital output word tells
us what fraction of the reference voltage or current is the input voltage or current. So, basically,
the ADC is a divider. The Input/output transfer function is given by the formula indicated here.

LDR

DRIVER
CIRCUIT
FPGA
ADC
SOLAR
CELLS

DC
MOTOR

BATTER
Y


2.2 Flowchart of Project

Fig: 2.2 Flowchart Diagram of integrated solar energy harvesting and storage
The flowchart of the integrated solar energy harvesting and storage is depicted in fig 2.2 initially
the light is sensed by the LDR and converted to electrical signal. This signal is converted to
digital form by means of ADC 0804.the digital code is used by the FPGA to decide the necessary
actions to be taken .Depending upon the comparison of LDR outputs FPGA decides the direction
of robot to be either of forward motion, backward or remain in stable position. The energy
obtained by solar cells is stored in battery.


CHAPTER 3
LITERATURE SURVEY
3.1 Fundamentals of Photovoltaic System
Photovoltaic panel are made of the natural element which becomes charged electrically when
subjected to sunlight. Photovoltaic is the direct conversion of light into electricity at the atomic
level. The panel works on the principle of the photovoltaic (PV) effect. For solar cells, a thin
semiconductor wafer is specially treated to form an electric field, positive on one side and
negative on the other.
3.1.1 Photovoltaic cell
When light energy strikes the PV cell, electrons are knocked loose from the atoms in the
semiconductor material and start travel from the PV cell, through electronic circuit to the load.
Then, they return to the PV cell where the silicon recaptures the electrons and the process is
repeated. The photovoltaic itself is a p-n junction, which through the process of electron
dropping and this produces a current in proportion to the solar radiation. If electrical conductors
are attached to the positive and negative sides, forming an electrical circuit, the electrons can be
captured in the form of an electric current and produce electricity. This electricity can then be
used to power a load, such as light or a tool.

Fig 3.1 The emission of electron from metal plate


3.1.2 The Photovoltaic Effect
The photovoltaic effect is the basic physical process through which a PV cell converts sunlight into
electricity .Sunlight is composed of packets of solar energy. These sunlight radiations contain
different amounts of energy that correspond to the different wavelengths of the solar spectrum. When
photons strike a PV cell, they may be reflected or absorbed, or they may pass right through. The
absorbed photons generate electricity. The photovoltaic cells generally consist of two thin regions,
one above the other, N-type and P-type. This two region structure, called a p-n junction. The
collection of light-generated carriers by the p-n junction causes a movement of electrons to the n-type
side and holes to the p-type side of the junction. When open circuit, carriers are prevented from
leaving the solar cell, then the collection of light-generated carriers causes an increase in the number
of electrons on the n-type side of the p-n junction and a similar increase in holes in the p-type
material. This separation of charge creates an electric field at the junction which is in opposition to
that already existing at the junction. Under short circuit conditions, the minority carrier concentration
on either side of the junction is increased and the drift current, which depends on the number of
minority carriers, is increased. In equilibrium (in the dark) both the diffusion and drift current are
small

Fig 3.2 photovoltaic effect in different conditions


3.1.3 Efficiency
On a bright, sunny day, the sun's rays give off approximately 1,000 watts of energy per square
meter of the planet's surface. If we could collect all of that energy, we could easily power our
homes and offices for free. However, in practically the maximum allowed by the law of physics
is between 30% and 40%. The efficiency of photovoltaic cells can be very tricky to figure out
and many of the companies that produce them take different routes when manufacturing their
products. Different companies will use different materials and as the technology improves, the
efficiency of the solar paneling options will also improve. There are basically 3 different types of
solar panels on the market today, each of which has a different efficiency rating. The following
are the 3 types and their efficiency ratings
Monocrystalline Silicon manufactured using a single crystal of silicon which has been
cut into a prescribed shape, this type of solar panel has a 13% conversion rate, meaning
that it converts 13% of the captured sunlight into electricity .
Polycrystalline Silicon these are less expensive and have a lower conversion rate
because of the multiple crystal manufacturing process. This increases internal resistance
between the silicon crystals. The conversion rate of these panels is around 12% to 12%
.
Thin Film Amorphous Silicon probably the cheapest solar panel to produce and the
least efficient at a rate of only 6% to 8%. More suited for use in cooler and tropical
climates, this type of solar panel is not very efficient in arid, hot climates.

Other then the material that use to crate solar cell its self, there are few factor that will affect
the energy efficiency.
The output will be less at:-
In cloudy condition The module is in the shade Pointed away from the sun In space, the output is
more higher due to the solar radiation is much stronger compare at the earth. Approximately, the
power density is around 1365 watt per square meter.



3.2 Types of photovoltaic System
Basically, there are three main systems that commonly use in photovoltaic system. Its come
with several configurations for difference use.

1. Directly Connected System

a. The system work without battery storage.
b. The load connected to the system operates in synchronization with sunlight.
c. Usually an over current protection device is added for safety purpose.
d. Typical application are:-

i. Ventilation fan.
ii. Water pumping.
iii. Calculator.

2. Stand Alone System

a. The system may have battery storage or emergency backup supply to provide
power when the sun is not available.
b. Commonly use in a remote area where there is no power-lines.
c. This type of system need to have charge regulator to prevent battery overcharging or
over discharging.
d. Typical application are:-

i. Remote home.
ii. Outdoor lighting
iii. Solar car

3. Utility Interactive System

a. This system consist neither battery storage nor an emergency backup system.
b. This system connected with the utility grid.
c. When the sunlight not available it has battery storage
d. When the sunlight and battery storage out, the power will be supply by utility power
system.


3.3 Solar Position Algorithm for Solar Radiation Application
The best uncertainty achieved is greater than 0.01/ in calculating the solar zenith and azimuth
angles. For some, the algorithm is valid for a limited number of years varying from 15 years to a
hundred years. This is a step by step procedure for implementing an algorithm to calculate the
solar zenith and azimuth angles in the period from the year -2000 to 6000, with uncertainties of
0.0003/. The algorithm is described with a focus on the sun instead of the planets and stars in
general. It also introduces some changes to accommodate for solar radiation applications. The
changes include changing the direction of measuring azimuth angles to be measured from north
and eastward instead of being measured from south and eastward, and the direction of measuring
the observers geographical longitude to be measured as positive eastward from Greenwich
meridian instead of negative. This also includes the calculation of incidence angle for a surface
that is tilted to any horizontal and vertical angle, with the continuous technological
advancements in solar radiation applications, there will always be a demand for smaller
uncertainty in calculating the solar position. Many methods to calculate the solar position have
been published in the solar radiation literature, nevertheless, their uncertainties have been greater
than 0.01/ in solar zenith and azimuth angle calculations and some are only valid for a specific
number of years.
The importance of reducing the uncertainty of calculating the solar position to lower than
0.01/, is the calibration of pyranometers that measure the global solar irradiance. During the
calibration, the responsivity of the pyranometer is calculated at zenith angles from 0/ to 90/ by
dividing its output voltage by the reference global solar irradiance (G), which is a function of the
cosine of the zenith angle. From this arises the need to use a solar position algorithm with lower
uncertainty for users that are interested in measuring the global solar irradiance with smaller
uncertainties in the full zenith angle range from 0/ to 90/.
We describe a procedure for a Solar Position Algorithm (SPA) to calculate the solar
zenith and azimuth angle with uncertainties equal to 0.0003/ in the period from the year -2000
to 6000. The azimuth angle is measured westward from south, but for solar radiation
applications, it is measured eastward from north. Also, the observers geographical longitude is


considered positive west, or negative east from Greenwich, while for solar radiation applications,
it is considered negative west, or positive east from Greenwich.
3.3.1 Solar Azimuth angle
The Solar Azimuth angle is the azimuth angle of the sun. It defines in which direction the sun is,
whereas the solar zenith angle or solar elevation defines how high the sun is. (The elevation is
the complement of the zenith.) There are several conventions for the solar azimuth; however it is
traditionally defined as the angle between a line due south and the shadow cast by a vertical rod
on Earth. This convention states the angle is positive if the line is east of south and negative if it
is west of south. For example due east would be 90 and due west would be -90. Another
convention is the reverse; it also has the origin at due south, but measures angles clockwise, so
that due east is now negative and west now positive.
However, despite tradition, the most commonly accepted convention for analyzing solar
radiation, e.g. for solar energy applications, is clockwise from due north, so east is 90, south is
180 and west is 270. This is the definition used in their solar position calculators
Note: Both of these formulas assume the north-clockwise convention. The solar azimuth
angle can be calculated to a good approximation with the following formula, however angles
should be interpreted with care due to the inverse sine, i.e. x = sin
1
(y) has two solutions (unless
y is -1 or +1), only one of which will be correct.
(1)

The following formulas can also be used to approximate the solar azimuth angle, but these
formulas use cosine, so the azimuth angle will always be positive, and should be interpreted as
the angle less than 180 degrees when the hour angle, h, is negative (morning) and the angle
greater than 180 degrees when the hour angle, h, is positive (afternoon). (These two formulas
are equivalent if you assume the "solar elevation angle" approximation formula).
(2)


(3)

The formulas use the following terminology:
is the solar azimuth angle
is the solar elevation angle
is the hour angle, in the local solar time
is the current sun declination
is the local latitude

3.3.2 Solar zenith angle
The solar zenith angle,
s
is estimated using results from spherical trigonometry
where

s
is the solar zenith angle
h is the hour angle, in the local solar time.
is the current declination of the Sun
is the local latitude.
3.3.3 Solar elevation angle
The solar elevation angle is the altitude of the sun, the angle between the horizon and the centre
of the sun's disc. The approximate value can be calculated with the following formula:
where

s
is the solar elevation angle,
s
= 90
s

h is the hour angle, in the local solar time.
is the current declination of the Sun
is the local latitude.


3.4 Dc Motors
A DC motor is an electric motor that runs on direct current (DC) electricity. DC motors can
operate directly from rechargeable batteries, providing the motive power for the first electric
vehicles.
There are 2 types if DC motors.
1. Brushed DC electric motor
2. Brushless DC electric motor

Fig 3.3 DC motor
3.4.1. Brushed Dc Electric Motor
The brushed DC electric motor generates torque directly from DC power supplied to the motor
by using internal commutation, stationary magnets (permanent or electromagnets), and rotating
electrical magnets. Advantages of a brushed DC motor include low initial cost, high reliability,
and simple control of motor speed. Disadvantages are high maintenance and low life-span for
high intensity uses. Maintenance involves regularly replacing the brushes and springs which
carry the electric current, as well as cleaning or replacing the commutator.



3.4.2 .Brushless Dc Electric Motor
Brushless DC motors use a rotating permanent magnet or soft magnetic core in the rotor, and
stationary electrical magnets on the motor housing. A motor controller converts DC to AC. This
design is simpler than that of brushed motors because it eliminates the complication of
transferring power from outside the motor to the spinning rotor. Advantages of brushless motors
include long life span, little or no maintenance, and high efficiency. Disadvantages include high
initial cost, and more complicated motor speed controllers. Some such brushless motors are
sometimes referred to as "synchronous motors" although they have no external power supply to
be synchronized with, as would be the case with normal AC synchronous motors. Dept. of
Instrumentation & Control
3.5 Connection Types
3.5.1. Series Connection
A series DC motor connects the armature and field windings in series with a common D.C.
power source. This motor has poor speed regulation since its speed varies approximately
inversely to load. However, a series DC motor has very high starting torque and is commonly
used for starting high inertia loads, such as trains, elevators or hoists. With no mechanical load
on the series motor, the current is low, the magnetic field produced by the field winding is weak,
and so the armature must turn faster to produce sufficient counter-EMF to balance the supply
voltage (and internal voltage drops). For some types of motor, the speed may be higher than can
be safely sustained by the motor. In a no-load condition, the motor may increase its speed until
the motor mechanically destroys itself. This is called a runaway condition. The speed/torque
characteristic is also useful in applications such as dragline excavators, where the digging tool
moves rapidly when unloaded but slowly when carrying a heavy load.
3.5.2. Shunt Connection
A shunt DC motor connects the armature and field windings in parallel or shunt with a common
D.C. power source. This type of motor has good speed regulation even as the load varies, but


does not have as high of starting torque as a series DC motor. It is typically used for industrial,
adjustable speed applications, such as machine tools, winding/unwinding machines.

3.5.3. Compound Connection

A compound DC motor connects the armature and fields windings in a shunt and a series
combination to give it characteristics of both a shunt and a series DC motor. This motor is used
when both a high starting torque and good speed regulation is needed. The motor can be
connected in two arrangements: cumulatively or differentially. Cumulative compound motors
connect the series field to aid the shunt field, which provides higher starting torque but less speed
regulation. Differential compound DC motors have good speed regulation and are typically
operated at constant speed. They are commonly used in elevators, air compressors, conveyors
and punch presses
3.6 Dc Motor Forward Reverse Control

Fig 3.4 DC motor forward-reverse control


3.6.1 Circuit working Description
This circuit is designed to control the motor in the forward and reverse direction. It consists of
two relays named as relay1, relay2. The relay ON and OFF is controlled by the pair of switching
transistors. A Relay is nothing but electromagnetic switching device which consists of three pins.
They are Common, Normally close (NC) and normally open (NO). The common pin of two relay
is connected to positive and negative terminal of motor through snubber circuit respectively. The
relays are connected in the collector terminal of the transistors T2 and T4.When high pulse signal
is given to either base of the T1 or T3 transistors, the transistor is conducting and shorts the
collector and emitter terminal and zero signals is given to base of the T2 or T4 transistor. So the
relay is turned OFF state. When low pulse is given to either base of transistor T1 or T3 transistor,
the transistor is turned OFF. Now 12v is given to base of T2 or T4 transistor so the transistor is
conducting and relay is turn ON. The NO and NC pins of two relays are interconnected so only
one relay can be operated at a time. The series combination of resistor and capacitor is called as
snubber circuit. When the relay is turn ON and turn OFF continuously, the back emf may fault
the relays. So the back emf is grounded through the snubber circuit.
When relay 1 is in the ON state and relay 2 is in the OFF state, the motor is running in the
forward direction.
When relay 2 is in the ON state and relay 1 is in the OFF state, the motor is running
in the reverse direction.
3.7 Function of LDR
Two cadmium sulphide (cds) photoconductive cells with spectral responses similar to that of the
human eye. The cell resistance falls with increasing light intensity. Applications include smoke
detection, automatic lighting control, and batch counting and burglar alarm systems in shown in
Fig 4.2. Like the human eye, the relative sensitivity of a photoconductive cell is dependent on the
wavelength (color) of the incident light. Each photoconductor material type has its own unique
spectral response of the relative response of the photocell versus wavelength of light. The LDR
circuits as in Fig: 4.3


Fig: 3.5 Typical Application Circuits
IR_GND
L
D
R
R13
1
0
k
IR_GND
L
D
R
R12
3
3
0
k

t
o

1
m
-
(
3
3
0
k
)
R8
1
0
k
VCC-IR
IR_GND
+
-
U1D
LM339 11
10
13
3
1
2
SENSOR1
SENSOR4
L
D
R
R9
1
0
k
R2
1
M
R7
1
M
R14
1
0
k
_
N
O
T
_
P
L
A
C
E
D
R10
1
0
k
1
3
2
R15
1
0
k
1
3
2
R20
1
0
k
1
3
2
R17
1
M
SENSOR2
VCC-IR
R4
1
0
k
+
-
U1C
LM339 9
8
14
3
1
2
R5
1
0
k
1
3
2
+
-
U1A
LM339 7
6
1
3
1
2
VCC-IR
+
-
U1B
LM339 5
4
2
3
1
2
R3
1
0
k
SENSOR3
L
D
R
R18
1
0
k
R19
1
0
k
IR_GND

Fig: 3.6 LDR Circuits


3.7.1 Spectral Response
Like the human eye, the relative sensitivity of a photoconductive cell is dependent on the
Wavelength (color) of the incident light. Each photoconductor material type has its own unique
spectral response curve or plot of the relative response of the photocell versus wavelength of
light as shown in Fig: 4.4
3.7.2 Sensitivity
The sensitivity of a photo detector is the relationship between the light falling on the device and
the resulting output signal. In the case of a photocell, one is dealing with the relationship
between the incident light and the corresponding resistance of the cell. of the photocell versus
wavelength of light. Light energy is converted to electrical energy through a photodiode and
mechanical vibrations are converted to electrical energy by an electromechanical transducer

Fig: 3.7 Resistance As Function Of Illumination
3.8 Stepper motor
Dc motor is controlled by the driver circuit and the positive & negative terminals of the dc motor
are connected to snubber circuit..When dc motor positive terminal gets 12v it will make the solar
cell array to move in clockwise direction. When dc motor negative terminal gets 12v it will make


the solar cell array to move in anti clockwise direction. The systems energy gathering ability
will wireless systems through discrete photovoltaic cells together depend on environmental
conditions, which can change over time with separate energy storage devices using board level
designs

Fig 3.8 stepper motor


3.9 Analog to Digital Converter (ADC)
The Analog-to-Digital Converter (A/D Converter or ADC) has both analog and digital functions;
it is a mixed-signal device. Many of us consider the ADC to be a mysterious device. It can,
however, be considered very simply to be the instrument that it is: a device that provides an
output that digitally represents the input voltage or current level. Notice I said voltage or current.
Most ADCs convert an input voltage to a digital word, but the true definition of an ADC does
include the possibility of an input current. An ADC has an analog reference voltage or current
against which the analog input is compared. So, basically, the ADC is a divider. The Input/output
transfer function is given by the formula indicated here. If you have seen this formula before,
you probably did not see the G term (gain factor).Here is an example of a 3-bit A/D converter.
Because it has 3 bits, there are 2
3
= 8 possible output codes. The difference between each output
code is VREF / 23. Assuming that the output response has no errors, every time you increase the
voltage at the input by 1 Volt, the output code will increase by one bit.
This means, in this example, that the least significant bit (LSB) represents 1 Volt, which
is the smallest increment that this converter can resolve. For this reason, we can say that the
resolution of this converter is 1.0V because we can resolve voltages as small as a volt.
Resolution may also be stated in bits. if you reduce the reference voltage to 0.8V, the LSB would
then represent 100mV, allowing you to measure a smaller range of voltages (0 to 0.8V) with
greater accuracy. The Resolution of an A/D converter is the number of output bits it has (3 bits,
in this example).Resolution may also be defined as the size of the LSB (Least Significant Bit) or
one count (1 Volt, in this example). For a 3-bit ADC, there are 8 possible output codes. In this
example, if the input voltage is 5.5V and the reference is 8V, then the output will be 101. More
bits give better resolution and The 3-bit A/D converter as in Fig: 4.5.Because it has 3 bits, there
are 2
3
= 8 possible output codes. The difference between each output code is VREF / 23.
Assuming that the output response has no errors, every time you increase the voltage at the input
by 1 Volt, the output code will increase by one bit. This means, in this example, that the least
significant bit (LSB) represents 1 Volt, which is the smallest increment that this converter can
resolve.


Fig: 3.9 Block Diagram Of ADC
For this reason, we can say that the resolution of this converter is 1.0V because we can resolve
voltages as small as a volt. Resolution may also be stated in bits. Note that if you reduce the
reference voltage to 0.8V, the LSB would then represent 100mV, allowing you to measure a
smaller range of voltages (0 to 0.8V) with greater accuracy.
This is a common way for our customers to get better precision from a converter without
buying a more expensive, higher resolution converter. The Resolution of an A/D converter is the
number of output bits it has (3 bits, in this example). Resolution may also be defined as the size
of the LSB (Least Significant Bit) or one count (1 Volt, in this example).
Least Significant Bit (LSB) and Most Significant Bit (MSB)



The Least and Most Significant Bits (LSB and MSB) are just what their name implies:
those bits that have the least weight (LSB) and most weight (MSB) in a digital word. For an n-bit
word, the MSB has a weight of 2(n-1) = 2n / 2 where n is the total number of bits in the word.
The LSB has a weight of 1.

Since one LSB is equal to VREF / 2n, it stands to reason that better accuracy (lower
error) can be realized if we did either (or both) of two things: (1) use a higher resolution
converter and/or (2) use a smaller reference voltage. The problem with higher resolution (more
bits) is the cost. Also, the smaller LSB means it is difficult to find a really small signal as it
becomes lost in the noise, reducing SNR performance of the converter. The problem with
reducing the reference voltage is a loss of input dynamic range. Again, we also can lose a small
signal in the noise, causing a loss of SNR performance.
3.9.1 Quantization Error
Continuing with the simple example of a 3-bit ADC, an ADC input of zero produces an output
code of zero (000) as in Fig: 4.6 . As the input voltage increases towards VREF/8, the error also
increases because the input is no longer zero, but the output code remains at zero because a range
of input voltages is represented by a single output code. When the input reaches VREF/8, the
output code changes from 000 to 001, where the output exactly represents the input voltage and
the error reduces to zero. As the input voltage increases past VREF/8, the error again increases
until the input voltage reaches VREF/4, where the error again drops to zero.


Fig: 3.10 The Magnitude Of The Error Ranges From Zero To 1 LSB
This process continues through the entire input range and the error plot is a saw tooth, as
shown here. The maximum error we have here is 1 LSB. This 0 to 1 LSB range is known as the
quantization uncertainty because there are a range of analog input values that could have
caused any given code and we are uncertain as to exactly what the input voltage was that caused
a given code. The maximum quantization uncertainty is also known as the quantization error.
This error results from the finite resolution of the ADC. That is, the ADC can only resolve the
input into 2n discrete values. Each output code represents a range of input values.
This range of values is a quantum, to which we assign the symbol q. The converter
resolution, then, is 2n. So, for an 8 Volt reference (with a unity gain factor), a 3-bit converter
resolves the input into VREF/8 = 8V/8 = 1 Volt steps as shown in Fig: 4.7. Quantization error,
then, is a round off error. But an error of 0 to 1 LSB is not as desirable as is an error of 1/2
LSB, so we introduce an offset into the A/D converter to force an error range of 1/2 LSB.
Digital output. The systems energy gathering ability will depend on environmental conditions,
which can change over time. The system consists of sensors that can observe the environment, an
analog-to-digital converter (ADC) that can quantize the analog signal from the sensors, a
CPLD/FPGA core that can analyze and encode the quantized data and a transceiver (RF) so that
the node can transmit and receive information. The scavenged energy needs to be regulated
before being used by these functional blocks as shown in fig: 4.8


Fig: 3.11 Pin diagram of ADC0803

Fig: 3.12 Functional Block Diagram Of ADC0803


Because the Analog-to-Digital Converter (A/D Converter or ADC) has both analog and digital
functions, it is a mixed-signal device. Many of us consider the ADC to be a mysterious device. It
can, however, be considered very simply to be the instrument that it is: a device that provides an
output that digitally represents the input voltage or current level. Notice I said voltage or current.
Most ADCs convert an input voltage to a digital word, but the true definition of an ADC
does include the possibility of an input current. An ADC has an analog reference voltage or
current against which the analog input is compared. The digital output word tells us what fraction
of the reference voltage or current is the input voltage or current. So, basically, the ADC is a
divider. The Input/output transfer function is given by the formula indicated here. If you have
seen this formula before, you probably did not see the G term (gain factor). This is because we
generally consider this to be unity. However, National Semiconductor has introduced ADCs with
other gain factors, so it is important to understand that this factor is present.
Here is an example of a 3-bit A/D converter. Because it has 3 bits, there are 2
3
= 8
possible output codes. The difference between each output code is VREF / 23.Assuming that the
output response has no errors, every time you increase the voltage at the input by 1 Volt, the
output code will increase by one bit. This means, in this example, that the least significant bit
(LSB) represents 1 Volt, which is the smallest increment that this converter can resolve. For this
reason, we can say that the resolution of this converter is 1.0V because we can resolve voltages
as small as a volt. Resolution may also be stated in bits.
If you reduce the reference voltage to 0.8V, the LSB would then represent 100mV,
allowing you to measure a smaller range of voltages (0 to 0.8V) with greater accuracy. This is a
common way for our customers to get better precision from a converter without buying a more
expensive, higher resolution converter. The Resolution of an A/D converter is the number of
output bits it has (3 bits, in this example). Efficient energy without requiring battery materials to
be integrated t ADCs and DSPs can achieve average power levels in the on-chip. This paper
describes an array of photodiodes, modeled sub-milliwatt range. However, low power ADCs
usually suffer from diminished power supply rejection. Minimizing Manuscript received typical
characteristics of a photodiode under illumination along with a schematic.


The optimum configuration for harvesting energy is found with the load resistance that
maximizes the product of the current through the diode I and the voltage across the diode.
Capacitance can be exploited for storing the scavenged energy. In total, 11 different diodes were
fabricated in three different ports experimental integrated photodiode test sizes. Photodiodes for
energy scavenging differ from imaging results in integrated energy pixels in the way in which
they are optimized. Imagers are de-storage.
Finally provides conclusions from this signed to minimize noise, dark current, and lateral
photocurrent research (which can create pixel-to-pixel crosstalk), while photodiodes output
power. Imaging sensors are commonly designed to drive The layout and design of an integrated
energy scavenging a high impedance capacitive load presented by a sense amp, photodiode must
balance several competing factors .The while energy scavenging photodiodes are designed to
drive re-charge generated in the depletion region of the photodiode is resistive loads.
The energy storage capacitors which are bent to be stored in on-chip capacitors; therefore
the physical for storing the harvested energy from the photodiodes layout of the diodes should
facilitate both the solar energy would limit the refresh rate of an image. Harvesting and
capacitive energy storage. The light that reaches the larger photovoltaic cells were first
discovered in the mid photodiodes depletion region must first pass through the passive 1800s
and had efficiencies of less than one percent. Since then, layers and avoid the metal storage
capacitance, which is numerous advances in materials and technology have allowed constructed
on top of the diode to minimize area for substantial increases in efficiency and size. Figure of
merit (FOM) is needed in order to quantitatively available silicon photovoltaic cells boast
efficiencies near assess the performance of the photodiodes. The FOM used here 17%. which is
defined as the max-to reach efficiencies nearing 24% A commonly cited minimum output
power obtainable divided by the product of the theoretical model for the fundamental limits of
silicon solar open circuit voltage and the short circuit current ,cells that takes into account Auger
recombination and absorption-for a given light intensity.
The energy density of fully integrated storage capacitors is not competitive with system-
in-package solutions such as ultra capacitors or printable batteries, even with scaling to the end
of the ITRS roadmap.


However, for applications with very low energy storage requirements or cost constraints
which limit system-in package integration, exploiting interconnect parasitic capacitance for
storage may be a viable solution.
The combination of integrated solar energy scavenging and storage can enable a new
generation of low cost, long lifetime, small volume systems for future wireless sensor networks
or RFID applications. White LED lighting systems powered by solar cells have presented for
many years, they are not widely used in today application because of their cost and low energy
conversion efficiency. The proposed system use the dc power generated by fixed solar cells
module to energize White LED light sources that are operated by directly connected White LED
with current limitation resistors, resulting in much more power consumption. This paper presents
the use of white LED as a general lighting application powered by tracking solar cells module
and using pulse to apply the electrical power to the White LED. These systems resulted in high
efficiency power.
3.10 Light-Dependent Resistor
As its name implies, the Light Dependent Resistor (LDR) is made from a piece of exposed
semiconductor material such as cadmium sulphide that changes its electrical resistance from
several thousand Ohms in the dark to only a few hundred Ohms when light falls upon it by
creating hole-electron pairs in the material. The net effect is an improvement in its conductivity
with a decrease in resistance for an increase in illumination.
When the light level is low the resistance of the LDR is high. This prevents current from
flowing. However, when light shines onto the LDR its resistance falls and current starts flowing.
An LDR has a zigzag cadmium sulphide track. It is a bilateral device, i.e., conducts in both the
direction .We make use of two LDRs as light sensors, to achieve solar cell panel to track the
sun.LDR controls the rotation of panel depending upon the LDRs resistance, the panel moves
clockwise or anticlockwise direction.LDR1 is used to move in clockwise direction and LDR2 is
used to move in anticlockwise direction.


Fig 3.13 Light dependent resistor
If LDR1 resistance < LDR2 resistance, then panel moves clockwise direction.
If LDR1 resistance > LDR2 resistance, then panel moves anti clockwise direction.
If LDR1 resistance =LDR2 resistance, then panel does not move.
3.10.1 ADC
The LDRs analog output signal is processed in ADC0809.ADC0809 converts analog output of
LDR to equivalent digital code. For example with a LDRs zero output signal ADC produces 000,
depending upon the number of bits.
3.10.2 Driver Circuit
The driver circuit is designed to control the motor rotation in turn controls the solar cell array.
We make use of two relays, namely relay1 and relay2.When relay1 is in the on state and relay2 is
in the off state, the motor is running in the forward direction. When relay2 is in the on state and
relay1 is in the off state the motor is running in reverse direction.
3.11 Solar Cell Array
The solar energy is absorbed by the solar cell arrays and converted it to electrical energy. The
solar cell array is made to track the sunlight throughout the day. SOLAR cells or photovoltaic
cells are in fact large area semiconductor diodes that convert sunlight into electrical current to


produce usable power .They have long been used in situations where electrical power from
power station is unavailable, such as in remote area power systems. The power output of a solar
array is given in watts. In order to calculate the energy needs of the application, a measurement
in watt-hours per day is often used. The output power of the solar cell depends on multiple
factors, such as sunlight intensity and direction of the cells. In order to reach the maximum
power, the solar tracker has been added to this system to avoid time limit of the fixed systems.
3.11.1 Active Solar Trackers
Active trackers measure the light intensity from the sun to determine where the solar modules
should be pointing. Light sensors are positioned on the tracker at various locations or in specially
shaped holders. If the sun is not facing the tracker directly there will be a difference in light
intensity on one light sensor compared to another and this difference can be used to determine in
which direction the tracker has to tilt in order to be facing the sun.
3.11.2 Types Of Solar Trackers

There are many different types of solar tracker which can be grouped into single axis and double
axis models.

3.11.2.1 Single Axis Solar Trackers
Single axis solar trackers can either have a horizontal or a vertical axle. The horizontal type is
used in tropical regions where the sun gets very high at noon, but the days are short. The vertical
type is used in high latitudes (such as in UK) where the sun does not get very high, but summer
days can be very long. These have a manually adjustable tilt angle of 0 - 45 and automatic
tracking of the sun from East to West. They use the PV modules themselves as light sensor to
avoid unnecessary tracking movement and for reliability. At night the trackers take up a
horizontal position.
3.11.2.2 Double Axis Solar Trackers
Double axis solar trackers have both a horizontal and a vertical axle and so can track the Sun's
apparent motion exactly anywhere in the world. This type of system is used to control astronomical


telescopes, and so there is plenty of software available to automatically predict and track the motion
of the sun across the sky. Dual axis trackers track the sun both East to West and North to South for
added power output (approx 40% gain) and convenience

Fig 3.14 single axis solar panel

Fig 3.15 double axis tracker



3.12 Battery
Battery is used to store the power from solar cell arrays and make use for other
applications. Battery is a storage device. The systems energy gathering ability will de- wireless
systems through discrete photovoltaic cells to gathered on environmental conditions, which can
change over time. With separate energy storage devices using board level designs. the analog
signal from the sensors, a dig-system lifetime and performance, adds manufacturing cost, digital
signal processing (DSP) core that can analyze and encoder and increases system volume and
maintenance expenditures. The quantized data and a transceiver (RF) so that the node can
delivering power to wireless sensor network nodes is a significant transmit and receive
information. Light energy is converted to cant system design challenge.



CHAPTER 4
TOOLS REQUIRED
4.1 Software Tools
Xilinx ISE13.2i
ModelSim XE 6.3c
4.1.1 Xilinx ISE 13.2i
The Xilinx ISE tools allow you to use schematics, hardware description languages (HDLs),
and specially designed modules in a number of ways. Schematics are drawn by using symbols
for components and lines for wires. Xilinx Tools is a suite of software tools used for the design
of digital circuits implemented using Xilinx Field Programmable Gate Array (FPGA) or
Complex Programmable Logic Device (CPLD).

The design procedure consists of (a) design entry, (b) synthesis and implementation of
the design, (c) functional simulation and (d) testing and verification. Digital designs can be
entered in various ways using the above CAD tools: using a schematic entry tool, using a
hardware description language (HDL)Verilog or VHDL or a combination of both. In this lab we
will only use the design flow that involves the use of Verilog HDL.

The CAD tools enable you to design combinational and sequential circuits starting with
Verilog HDL design specifications.
The steps of this design procedure are listed below:
1. Create Verilog design input file(s) using template driven editor.
2. Compile and implement the Verilog design file(s).
3. Create the test-vectors and simulate the design (functional simulation) without using a
PLD (FPGA or CPLD).
4. Assign input/output pins to implement the design on a target device.
5. Download bit stream to an FPGA or CPLD device.
6. Test design on FPGA/CPLD device


The Integrated Software Environment (ISE) is the Xilinx design software suite that
allows you to take your design from design entry through Xilinx device programming. The ISE
Project Navigator manages and processes your design through the following steps in the ISE
design flow.
Design Entry
Design entry is the first step in the ISE design flow. During design entry, you create your
source files based on your design objectives. You can create your top-level design file using a
Hardware Description Language (HDL), such as VHDL, Verilog, or ABEL, or using a
schematic. You can use multiple formats for the lower-level source files in your design.
Note: If you are working with a synthesized EDIF or NGC/NGO file, you can skip design entry
and synthesis and start with the implementation process.
Synthesis
After design entry and optional simulation, you run synthesis. During this step, VHDL,
Verilog , or mixed language designs become net list files that are accepted as input to the
implementation step.
Implementation
After synthesis, you run design implementation, which converts the logical design into a
physical file format that can be downloaded to the selected target device. From Project
Navigator, you can run the implementation process in one step, or you can run each of the
implementation processes separately. Implementation processes vary depending on whether you
are targeting a Field Programmable Gate Array (FPGA) or a Complex Programmable Logic
Device (CPLD).
Verification
You can verify the functionality of your design at several points in the design flow. You
can use simulator software to verify the functionality and timing of your design or a portion of
your design. The simulator interprets VHDL or Verilog code into circuit functionality and
displays logical results of the described HDL to determine correct circuit operation. Simulation


allows you to create and verify complex functions in a relatively small amount of time. You can
also run in-circuit verification after programming your device.
Device Installation
After generating a programming file, you configure your device. During configuration,
you generate configuration files and download the programming files from a host computer to a
Xilinx device.
The programming Language Interface (PLI) is a powerful features that allows the user to
write custom C code to interact with the internal data structures of Verilog.

4.2 ModelSim 6.3 C
HDL simulation is only part of verification. You must determine the impact of the entire
environment when considering simulation performance. The Fig: 5.2 below illustrate the various
flows that may affect your simulation:

Fig: 4.1 ModelSim Simulation Environments
Any part of your environment may negatively impact simulation performance. The HDL
code may be inefficient; test bench languages and third party debug tools may slow the
simulation; Third party IP may be un-optimized. Consider that third party test bench


implementation alone can account for greater than 80 percent of the overall simulation
performance. If this is the case you should consider investigating the reason 80 percent of the
time is being spent on the test bench and its interface. ModelSim has a profiler (discussed below)
that may help you identify which part of your environment is impacting simulation performance
the most.
Turning to the simulator itself, its critical to realize simulators are run in two modes,
interactive and batch. Interactive mode is generally associated with debugging where maximum
visibility into the design is needed. Batch mode jobs are run in the background without the User
Interface (UI). Performance is generally the highest priority when running in batch mode.
Simulators in optimized performance mode remove visibility into a design. Prior to the 6.0
release ModelSim required the use of specific Verilog compiles options to enable performance.
ModelSim now has an optional flow that facilitates performance mode.

The ModelSim. Initial file is read whenever the compiler or simulator is invoked and has
a setting to enable/disable the default performance mode. This option is VoptFlow = 1. When
this is set to a zero you enable the pre-5.8C ModelSim flow, when this is set to one, you engage a
new performance out of box flow. With the 6.0 release the default is zero. Currently this optional
performance flow is very useful for pure Verilog designs where you are not interested in
debugging, or for Mixed Verilog and VHDL designs. All the Verilog in a design will be
optimized, regardless of where in the hierarchy it is located. Once again this can improve
performance up to 10x versus non-optimized mode. Another consideration with the new flow is
what part of the simulation you are measuring. ModelSim has separate compilation, optimization
(vopt) and simulation (vsim) steps. Furthermore vsim can automatically invoke vopt if it has not
already been run separately.

Simulation is a two-phase process. During phase 1 (known as elaboration), ModelSim
generates native code for your specific OS. During phase 2, ModelSim runs the native code.
Youll gain the most accurate performance statistics by measuring the elaboration phase and run
phase separately. As discussed below, you can use the switch command to measure these two
phases independently.



4.2.1 Model Sim Library
A library is a location where data to be used for simulation is stored. Libraries are ModelSims
way of managing the creation of data before it is needed for use in simulation. It also serves as a
way to streamline simulation invocation. Instead of compiling all design data each and every
time you simulate, ModelSim uses binary pre-compiled data from these libraries. So, if you
make a changes to a single Verilog module, only that module is recompiled, rather than all
modules in the design.
4.2.2 Model Sim modes of operation
Many users run ModelSim interactivelypushing buttons and/or pulling down menus in a series
of windows in the GUI (graphical user interface). But there are really three modes of ModelSim
operation, the characteristics of which are outlined in the following table 5.1.

Table 5.1 Model sim Modes Of Operation



4.2.3 Basic simulation flow
The following diagram Fig: 5.3 shows the basic steps for simulating a design in
ModelSim.

Fig 4.2 Basic simulation flow

Creating the working library
In ModelSim, all designs, be they VHDL, Verilog, or a combination of the two, are
compiled into a library. You typically start a new simulation in ModelSim by creating a working
library called "work". "Work" is the library name used by the compiler as the
default destination for compiled design units.

Compiling your design
After creating the working library, you compile your design units into it. The ModelSim
library format is compatible across all supported platforms. You can simulate your design on any
platform without having to recompile your design.

Running the simulation
With the design compiled, you invoke the simulator on a top-level module (Verilog) or a
configuration or entity/architecture pair (VHDL). Assuming the design loads successfully, the
simulation time is set to zero, and you enter a run command to begin simulation.
Create a working library
Compile design files
Run simulation
Debug results


4.3 Evolution of Programmable Logic Devices
The first type of user-programmable chip that could implement logic circuits was the
Programmable Read-Only Memory (PROM), in which address lines can be used as logic circuit
inputs and data lines as outputs. Logic functions, however, rarely require more than a few
product terms, and a PROM contains a full decoder for its address inputs. PROMS are thus an
inefficient architecture or realizing logic circuits, and so are rarely used in practice for that
purpose.
The first device developed later specifically for implementing logic circuits was the
Field-Programmable Logic Array (FPLA), or simply PLA for short. A PLA consists of two
levels of logic gates: a programmable wired AND-plane followed by a programmable wired
OR-plane. A PLA is structured So that any of its inputs (or their complements) can be ANDed
together in the AND-plane; each AND-plane output can thus correspond to any product term of
the inputs. Similarly, each OR plane output can be configured to produce the logical sum of any
of the AND-plane outputs.With this structure, PLAs are well-suited for implementing logic
functions in sum-of-products form. They are also quite versatile, since both the AND terms and
OR terms can have many inputs (this feature is often referred to as wide AND and OR
gates).This circuit is designed to control the motor in the forward and reverse direction. It
consists of two relays named as relay1, relay2. The relay ON and OFF is controlled by the pair
of switching transistors. A Relay is nothing but electromagnetic switching device which consists
of three pins. They are Common, Normally close (NC) and normally open (NO). The common
pin of two relay is connected to positive and negative terminal of motor through snubber circuit
respectively. The relays are connected in the collector terminal of the transistors T2 and T4.
When high pulse signal is given to either base of the T1 or T3 transistors, the transistor is
conducting and shorts the collector and emitter terminal and zero signals is given to base of the
T2 or T4 transistor. So the relay is turned OFF state. When low pulse is given to either base of
transistor T1 or T3 transistor, the transistor is turned OFF. Now 12v is given to base of T2 or T4
transistor so the transistor is conducting and relay is turn ON. The NO and NC pins of two relays
are interconnected so only one relay can be operated at a time. The series combination of resistor


and capacitor is called as snubber circuit. When the relay is turn ON and turn OFF continuously,
the back emf may fault the relays. So the back emf is grounded through the snubber circuit.
forward direction.
reverse direction.

4.3.1 Field Programmable Gate Array (FPGA)
This applies not only to custom devices like processors and memory, but also for logic circuits
such as state machine controllers, counters, registers, and decoders. When such circuits are
destined for high-volume systems they have been integrated into high-density gate arrays.
However, gate array NRE costs often are too expensive and gate arrays take too long to
manufacture to be viable for prototyping or other low-volume scenarios. For these reasons, most
prototypes, and also many production designs are now built using FPDs. The most compelling
advantages of FPDs are instant manufacturing turnaround, low start-up costs, low financial risk
and (since programming is done by the end user) ease of design changes.The market for FPDs
has grown dramatically over the past decade to the point where there is now a wide assortment of
devices to choose from. A designer today faces a daunting task to research the different types of
chips, understand what they can best be used for, choose a particular manufacturers product,
learn the intricacies of vendor-specific software and then design the hardware. Confusion for
designers is exacerbated by not only the sheer number of FPDs available, but also by the
complexity of the more sophisticated devices. The purpose of this paper is to provide an
overview of the architecture of the various types of FPDs.
4.3.2 Applications
Implementation of custom designs using the full power of the Virtex-E architecture Evaluate
Virtex-E FPGA families in the FF1152 package and Quickly and easily expand the complexity
of the system by stacking several boards and using partitioning software and tests of algorithms
under real time conditions and watch the signals with a logic analyzer, Experiment with different


low voltage I/O standards and differential signals ,ASIC Emulation, Error monitoring and
analysis, Digital PLL circuits, PWM controller, Adaptive digital filters, Signal multiplexers,
Stimuli generators, High speed encoder/decoder, Memory controller, Interface controller.
This board provides all the necessary basic components needed in most of FPGA-based
designs. Special care has been dedicated to routing topology and signal integrity. Most of the
I/Os are routed to ERmet 2mm Hard Metric connectors Complying to the international standard
IEC 61076-4-101. By combining two or more Virtex-E boards and using partitioning software
you can easily distribute your design over several FPGAs to cope with complex designs that
exceed the scope of a single FPGA.The Virtex-E development board gives you an ideal platform
for evaluating, implementing, testing, and extending custom designs using Virtex-E devices. You
can also easily integrate the board into a larger system. The board is equipped with On board
power supplies and can be operated from a single 5V to 24V power supply. This makes it great
for teaching, seminars, and courses.
4.3.3 General workflow when working with FPGAs:
We use a computer to describe a "logic function" that you want. You might draw a
schematic, or create a text file describing the function, doesn't matter.
You compile the "logic function" on your computer, using a software provided by the
FPGA vendor. That creates a binary file that can be downloaded into the FPGA.
We connect a cable from your computer to the FPGA, and download the binary file to the
FPGA.
That's it! Your FPGA behaves according to your "logic function".
We can download FPGAs as many time as you want - no limit - with different
functionalities every time if you want. If you make a mistake in your design, just fix your
"logic function", re-compile and re-download it. No PCB, solder or component to change.
The designs can run much faster than if you were to design a board with discrete
components, since everything runs within the FPGA, on its silicon die.


FPGAs lose their functionality when the power goes away (like RAM in a computer that
loses its content). You have to re-download them when power goes back up to restore the
functionality.
4.3.4 Internal logic
FPGAs are built from one basic "logic-cell", duplicated hundreds or thousands of time. A logic-
cell is composed of a small lookup table, some gates and a D-flipflop.
Each cell can do little, but with so many of them, complex logic functions can be created.
The interconnect wires also go to the boundary of the device where I/O cells are implemented
and connected to the pins of the FPGAs. Dedicated routing/carry chains In addition to general-
purpose interconnect resources, FPGAs have fast dedicated lines in between neighboring logic
cells. The most common type of fast dedicated lines are carry chains. Carry chains allow creating
arithmetic functions (counters/adders) very efficiently (low logic usage & high operating speed).
Older programmable technologies (PAL/CPLD) don't have carry chains and so are quickly
limited when arithmetic operations are required.
4.3.5 Internal RAM

While the first FPGAs didn't have internal memories, all new FPGAs have internal memories.
That increase lot heir scope of application. There are many parameters affecting RAM operation.
The main parameter is the number of agents that can access the RAM simultaneously.
"single-port" RAMs: only one agent can read/write the RAM.
"dual-port" or "quad-port" RAMs: 2 or 4 agents can read/write. Great to get data across
clock domains (each agent can use a different clock).
To figure out how many agents are available, count the number of separate address buses
going to the RAM. Each agent has a dedicated address bus. Each agent has also either a read, a
write, or both data buses. Having both data buses doesn't always mean an agent can read and
write simultaneously. RAM blocks are usually dedicated memory block ("block rams"). Xilinx
has a lot of flexibility in the RAM distribution, because it also allows using the logic-cells as tiny
RAMs ("distributed RAM"). Altera usually takes another approach and builds different-size
block rams around the device.


4.3.6 FPGA pins
FPGA pins fall into 2 categories: "dedicated pins" and "user pins". About 20% to 30% of the
pins of an FPGA are "dedicated pins". Power pins. Might be ground pins (GND) or power pins
(core or IO).
Configuration pins. These pins are used to "download" the FPGA.
Dedicated inputs, or clock pins. These pins are able to drive large and wide nets inside
the FPGA, suitable for clocks or signals with large fan-outs. The rest are user pins.
4.3.7 IO banks
An FPGA has many VCCIO pins (IO power pins), usually all connected to the same voltage. But
new generations of FPGAs have a concept of "user IO banks". You split IOs into groups, each
having its own VCCIO voltage. That allows using the FPGA as a voltage translator device,
useful for example if one part of your board works with 3.3V logic, and another with 2.5V.
4.3.8 FPGA power
FPGAs usually require 2 voltages to operate: a "core voltage" and an "IO voltage". Each voltage
is provided through separate power pins.
The internal core voltage (called VCCINT here for simplicity), is used to power the logic
gates and flip-flops inside the FPGA. The voltage can range from 5V for older FPGA
generations, to 3.3V, 2.5V, 1.8V, 1.5V and even lower for the latest devices! The core
voltage is fixed (set by the model of FPGA that you are using).
The IO voltage (called VCCIO here for simplicity) is used to power the I/O blocks (=
pins) of the FPGA. That voltage should match what the other devices connected to the
FPGA expect.
4.3.9 Clocks and Global lines
An FPGA design is usually "synchronous". Simply put, that means that the design is clock based
- each clock (rising edge) allows the D flip-flops to take a new state. In a synchronous design, a
single clock may drive a lot of flip-flops simultaneously. That can cause timing and electrical


problems inside the FPGA. To get that working properly, FPGA manufacturers provide special
internal wires called "global routing"or"global lines". When you feed a clock signal to your
FPGA, you shouldn't use any FPGA pin, but use a "dedicated input pin". Usually, only such
input pins have the ability to drive a global line. Check the FPGA datasheet to find which pins
are the "dedicated inputs".FPGA P&R software are aware of these dedicated inputs, and will
automatically assign clocks to them if given the choice.
4.3.10 Features in common with FPGAs
Large number of gates available CPLDs typically have the equivalent of thousands to tens of
thousands of logic gates, allowing implementation of moderately complicated data processing
devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically
range from tens of thousands to several million.



CHAPTER 5
SIMULATION RESULTS

Fig: 5.1 Launching ISE Text Editor to edit SOLAR.vhd

Fig: 5.2 Internal RTL Diagram of solar.vhd



Fig: 5.2 shows the internal RTL Schematic diagram of the entity model and When we
have to do the double click on that each block ,then it generates the internal diagrams those are
shown in below fig 5.3

Fig: 5.3 Mux Register Schematic Diagram

Above figure 5.3 shows the register schematic diagram, it has mux inputs (7:1),clock,and
reset pins and also it has output q(7:0).

Fig: 5.4 Program Generation Report

Then Modelsim XE II5.8c generates the output simulation results, those are generates using
some fixed time periods . For 001 the output as shown in Fig :5.5


Fig: 5.6 Simulation Results of solar module
Above figure 5.6 specifies the simulation results for two poles, we have observe that
wave form results at any value, these output waveforms are some time at in phase d some time
at out phase with each other.

Fig 5.7 Simulation results of LDR_sensor1


Fig 5.8 RTL block diagram of LCD_data out



CHAPTER 6
CONCLUSION AND FUTURE SCOPE

6.1 Conclusion
Summarizes and compares the results of the integrated photodiodes and storage capacitances
with a commercially available solar cell. Unless otherwise noted these measurements were
conducted with an incident white light intensity of 20 kLUX, similar to being outside on a sunny
day. Integrated photodiodes have similar overall efficiencies to commercial crystalline silicon
solar cells.. D1 needs 184 m 184 m and D2 needs 164 m 164 m to deliver 5 W. Without
illumination, the system energy must be supplied by the integrated storage capacitors. For a 25
mm total photodiode area consisting of 3 diodes in series with the metal storage capacitances for
each diode connected in parallel, D1, D2, and D3 can supply enough energy for the DSP in to
produce 687, 745, and 903 output samples respectively.The energy density of fully integrated
storage capacitors is not competitive with system-in-package solutions such as ultracapacitors or
printable batteries, even with scaling to the end of the ITRS roadmap. However, for applications
with very low energy storage requirements or cost constraints which limit system-inpackage
integration, exploiting interconnect parasitic capacitance for storage may be a viable solution

6.2 Future Scope

One goal of this work is to determine the maximum energy per area that can be gathered from
solar energy and stored in a standard CMOS logic process. Determining the maximum stored
energy requires first calculating the capacitance per area. The capacitance analysis will start with
the stored energy relationship, which can then be divided up as a sum of two components: the
energy stored in the metal capacitance and the energy stored in the junction capacitance. Our
project focuses on the use of solar energy with maximum efficiency. Apart from the obvious uses
in household applications with some enhancements; the specific uses lie in the military
applications and autonomous wireless sensor nodes. The model developed basically focuses on
the unidirectional focusing. By adding another set of motors; we can make the solar cell rotate in


the ground plane in complete 360 degrees. This would make ultra-efficient, suitable for military
applications. This development is left to the future group planning to work on our project.

6.3 Advantages:
Solar Energy is a renewable form of energy and tends to give us large amount of energy
and light. Oil, on the other hand is not renewable and also degrades the environment.
Solar cells are very silent in their working and they are quite efficient too,
Solar energy equipments do not emit any harmful gases or radiations. They are highly
eco-friendly.
Solar cells require very less maintenance and they have a long life too.
Though, the initial set up of the solar panels is expensive, later on they turn out to be highly cost
effective,

6.4 Project Limitations
Availability is a major issue related to solar power. Suppose you are in a location which receives
light sunlight, then it gets difficult to take its advantage. Though it is free and easy to harness,
nevertheless its availability is not guaranteed in every region across the globe.Weather and
climatic changes is also one drawback. If there are dark and dense clouds, they definitely will
hinder the sunrays to reach their point. Ultimately dim light will reach and the power supply of
your household will be affected. Nevertheless Solar energy has some drawbacks; yet it should be
utilized at maximum in order to lessen the burden from natural resources and to get fully
prepared for the time when we no longer will be having the rapidly finishing natural resources.

6.5 Applications
Solar power deals with the use of solar radiation for practical purposes. It has been
employed in order to decrease the carbon footprints from our environment. It is the basic motor
of all forms of energy generation methods. It is free and clean to use. This form of energy is


available in abundance in our environment. The fossil fuels are also mere frozen solar power.
Solar energy has remained a necessary ingredient for decades now. It's demand for usage still
prevails.
As the technology has advanced, we now have started making use of electric vehicles too.
Such vehicles have started becoming readily available and are operated using battery technology
as well as solar energy. Their costs are now dropping and such vehicles are becoming readily
available to the masses. Electric vehicles have a wonderful future for sure as they do not pollute
the environment. They are also cheap in their usage.

Wireless sensors can enable a variety of applications
Including interactive environments for medicine
Environmental monitoring networks
Military target tracking
Detection of chemical and biological weapons In many of these wireless systems the
power source is a bottleneck that limits system lifetime and performance adds
manufacturing cost, and increases system volume and maintenance expenditures.
Delivering power to wireless sensor network nodes is a significant system design
challenge



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Appendix A
The key features of the Spartan-3A Starter Kit board are:
Xilinx 700K-gate XC3S700A Spartan-3A FPGA in the Pb-free 484-ball
BGApackage (FGG484)
4 Mbit Xilinx Platform Flash configuration PROM
64 MByte (512 Mbit) of DDR2 SDRAM, 32Mx16 data interface4 MByte (32
Mbit) of parallel NOR Flash
FPGA configuration storage Micro Blaze code storage/shadowing
x8 or x16 data interface after configuration
16 Mbits of SPI serial Flash
Choose either the STMicroelectronics or the Atmel DataFlash serial architectures
FPGA configuration storage
Micro Blaze code shadowing
Two-line, 16-character LCD screen
PS/2 mouse or keyboard port
VGA display port
10/100 Ethernet PHY (requires Ethernet MAC in FPGA)
Two nine-pin RS-232 ports (DTE- and DCE-style)
On-board USB-based programming solution
FPGA download/debug
SPI serial Flash in-system direct programming
50 MHz clock oscillator
8-pin DIP socket for second oscillator
SMA connector for clock inputs or outputs
100-pin Hirose FX2 expansion connector with up to 43 FPGA user I/Os
Compatible with Digilent FX2 add-on cards
High-speed differential I/O connectors
Receiver: Five data channels plus clock
Transmitter: Six data channels or five data channels plus clock
Supports multiple differential I/O standards, including LVDS, RSDS, mini-LVDS
Also supports up to 24 single-ended I/O
Uses widely available 34-conductor cables
Three six-pin expansion connectors for Digilent Peripheral Modules
Four-output, SPI-based Digital-to-Analog Converter (DAC)
Two-input, SPI-based Analog-to-Digital Converter (ADC) with programmable-
gain pre-amplifier
Stereo audio jack using digital I/O pins
Chip Scope Soft Touch debugging port
Rotary-encoder with push-button shaft
Eight discrete LEDs
Four slide switches
Four push-button switches

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