DOC/LP/01/28.02.

02
LP EC2354
LESSON PLAN
LP Rev. No: 00
Date: 13/12/10
Sub Code/Name: EC2354-VLSI DESIGN
Unit : I
Branch : EC
Semester: VI Page 01 of 06

UNIT I

CMOS TECHNOLOGY

Syllabus:
A brief History-MOS transistor, Ideal I-V characteristics, C-V characteristics,
Non ideal I-V effects, DC transfer characteristics - CMOS technologies, Layout
design Rules, CMOS process enhancements, Technology related CAD issues,
Manufacturing issues.
Session
Time
Page
No.
Topics to be covered
No

Ref Teac
Met

1.

Introduction VLSI Design

50m

1-4

2.

NMOS, PMOS Enhancement transistor

50m

5-7,40

3.
4.
5.

MOS transistor-Ideal I-V characteristics

MOS transistor-C-V characteristics
Nonideal I-V characteristics- velocity saturation
and mobility degradation, channel length
modulation, subthreshold conduction
Threshold voltage, Body effect, Junction leakage,
Tunneling, temperature dependence, Geometry
dependence
CMOS inverter DC characteristics, Beta ratio
effects

50m
50m
50m

42-45
45-51
51-55

1
1
1

50m

55-60

100m

60-65

6.
7.
9.

CMOS technology : nwell, P well Twin well,

50m
83,
1,3
triple well,
15-21
10.
Layout design rules-NAND,NOR gat
50m
83-91
1
11.
CMOS Process enhancement-SOI Process,
50m
91-100
1
Interconnects, circuit elements: Resistors,
12.
Circuit element: capacitor, CAD and
50m
1071,2
manufacturing issues
109,149
Objective: To understand the MOS transistor theory, CMOS technologies and the Layout

DOC/LP/01/28.02.02
LP EC2354
LESSON PLAN
LPRev. No: 00
Date: 13/12/10
Sub Code/Name: EC2354-VLSI DESIGN
Unit : II
Branch : EC
Semester: VI Page 02 of 06
UNIT II

CIRCUIT CHARACTERIZATION AND SIMULATION

Syllabus:
Delay estimation, Logical effort and Transistor sizing, Power dissipation,
Interconnect, Design margin, Reliability, Scaling- SPICE tutorial, Device
models, Device characterization, Circuit characterization, Interconnect
simulation.
Objective:
To study the circuit characterization and performance estimation of CMOS
technology .
Session
Topics to be covered
Time
Page
No.
No
13.
Delay estimation-RC delay model, Linear
50m
111delay model
117,245
14.
Logical effort
50m
118,313
15.
Transistor sizing
50m
118
16.
Power dissipation-static and dynamic power
50m
129-135
17.
Interconnect Estimation of resistance
50m
135capacitance, delay and cross talk
145,525
18.
Design margin
50m
145-148
19.
Reliability
50m
148-159
20.
Scaling
50m
159,229
21.
SPICE tutorial, Device models
50m
181-193
22.
Device&Circuit characterization, Interconnect
50m
193
simulation
-213
23.

CAT-1

75m

Ref
1,2
1,2
1
1
1,2
1
1
1,2
1
1
-

DOC/LP/01/28.02.02

Te
M

LESSON PLAN
SubCode/Name EC2354 -VLSI DESIGN
Unit : III
Branch : EC
Semester: VI

UNIT III

LP EC2354
LP Rev. No: 00
Date: 13/12/10
Page 03 of 06

COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN 9

9
Syllabus:
Circuit families Low power logic design comparison of circuit families
Sequencing static circuits, circuit design of latches and flip flops, Static
sequencing element methodology- sequencing dynamic circuits synchronizers
Objective: To Understand the concepts of designing combinational and sequential circuit
using CMOS logic configuration
Session
No.
24.

Topics to be covered

Time

50m
50m

Page
Ref
No
2151,2
224,342
225,361, 1,2,3
353
233-240
1
241-245
1

Circuit families-static CMOS,ratioed circuit

50m
50m

28.

Cascode voltage swing logic,Dynamic

circuits
Pass transistor,Differential circuits
BiCMOS,Low power logic design
comparison of circuit families
Sequencing static circuits

50m

252-265

BB

29.

Circuit design of latches and flip flops

50m

265-274

BB

30.

Static sequencing element

50m

275-283

BB

31.

Sequencing dynamic circuits

50m

284-289

BB

32.

Synchronizers

50m

289-294

BB

25.
26.
27.

Teachi
Metho
BB
BB
BB
BB

DOC/LP/01/28.02.02
LESSON PLAN
Sub Code/Name: EC2354 -VLSI DESIGN
Unit : IV

UNIT IV

Branch : EC

LP EC2354
LP Rev. No: 00
Date: 13/12/10
Page 04 of 06

Semester: VI

CMOS TESTING

Syllabus:
Need for testing- Testers, Text fixtures and test programs- Logic verificationSilicon debug principles- Manufacturing test Design for testability
Boundary scan.
Objective: To understand the concepts of CMOS testing
Session
No.
33.
34.
35.

Topics to be covered

Time

Page No

Ref

50m
50m
50m

531-536
537-540
541-544

1
1
1

36.
38.
39.

Need for testing

Text fixtures and test programs
Logic verification- Silicon
debug principle
Manufacturing test
Design for testability-adhoc tesing
Scan design

100m 544,621,239
50m
548-550
50m
550-555

40.
41.
42.

Built in self test,IDDQ testing

Boundary scan
CAT-2

50m
50m
75m

555-558
559-570
-

1,2,4
1
1
1
1
-

DOC/LP/01/28.02.02
LESSON PLAN
LP EC2354
SubCode/Name: EC2354 VLSI
DESIGN LP Rev. No: 00
Date: 13/12/10
Unit : V
Branch : EC Semester: VI
Page 05 of 06
UNIT V SPECIFICATION USING VERILOG HDL

Syllabus:
Basic concepts- identifiers- gate primitives, gate delays, operators, timing
controls,procedural assignments conditional statements, Data flow and RTL,
structural gate level,switch level modeling, Design hierarchies, Behavioral and
RTL modeling, Test benches,Structural gate level description of decoder,
equality detector, comparator, priorityencoder, half adder, full adder, Ripple
carry adder, D latch and D flip flop.
Objective: To understand the concepts of modeling a digital system using Hardware
Description Language.
Session
Topics to be covered
No.
43.
Basic concepts- identifiers- gate
primitives,, Design hierarchies
44.
Gate delays
45
Operators
46.
Chip Timing controls
47.
48.
49.
50.
51.
52.
53.
54.

Time
50m
50m
50m
50m

Page No

Ref

478,2
48,72,106,388
121
8
138
8
171-178
8

Teac
Me
B

B
B
B

Procedural assignments ,conditional

statements
Data flow and RTL
Structural gate level
Switch level modeling
Behavioral and RTL modeling, Test
benches
Gate level verilog code-Decoder, equality
detector, comparator, priorityencoder
Half adder, full adder, Ripple carry adder,
D latch and D flip flop.

50m

166,179

50m
50m
50m
50m

131
373
383
385

8
8
8
8

B
B
B
B

50m

136

50m

452,414

2,4

CAT-3

75m

DOC/LP/01/28.02.02
LESSON PLAN

LP EC2354
LP Rev. No: 00
Date: 13/12/10
Page 06 of 06

SubCode/Name: EC2354-VLSI DESIGN

Branch : EC
Semester: VI

Course Delivery Plan:

1
2
3
4
5
6
7
8
9
10 11 12 13
14
Week
I II I II I II I II I II I II I II I II I II I II I II I II I II I I
1 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 4 5 5 5 5 5 5 5
C
C
4
A
A
C
Units
T
T
A
2
3
T
1

TEXT BOOKS:
1. Weste and Harris: CMOS VLSI DESIGN (Third edition) Pearson Education, 2005
2. Uyemura J.P: Introduction to VLSI circuits and systems, Wiley 2002.

REFERENCES:
3. D.A Pucknell & K.Eshraghian Basic VLSI Design, Third edition, PHI, 2003
4. Wayne Wolf, Modern VLSI design, Pearson Education, 2003
5. M.J.S.Smith: Application specific integrated circuits, Pearson Education, 1997
6. J.Bhasker: Verilog HDL primer, BS publication,2001
7. Ciletti Advanced Digital Design with the Verilog HDL, Prentice Hall of India, 2003
8.Samir palnitkar, Verilog HDL , Pearson Education,second edition

Name
Designation
Date

Prepared by
M.ANUSHYA
Asst- professor

Approved by
Prof.E.G .Govindan
HOD, Department of EC