PCB DESIGN FOR REAL-WORLD

EMI CONTROL
b y
Bruce R. Archambeault
IBM Corporation
Research Triangle Park, NC
KLUWER ACADEMIC PUBLISHERS
Boston / Dordrecht / London
Contents
1 Introduction to EMI/EMC Design
for Printed Circuit Boards 1
1.1 Introduction to EMI/EMC 1
1.2 EMI Emissions Sources 4
1.3 Inductance 5
1.4 "Ground" 6
1.5 Shielding 6
1.6 Summary 7
EMC Fundamentals 9
2.1 Introduction 9
2.2 Coupling Mechanisms 10
2.2.1 Electric Field Coupling 10
2.2.2 Magnetic Field Coupling 12
2.3 Signal Spectra 14
2.3.1 Clock Signals' Harmonic Frequencies 14
2.3.2 Hertz vs. Bits-per-Second 17
2.3.3 Non-Squarewave Data Signals 18
2.4 Resonance Effects 19
2.4.1 Magic and Luck 20
2.5 Potential Emissions Sources 21
2.5.1 Shielded Products 21
2.5.2 Unshielded Products 22
2.6 Intentional Signal Content 23
2.7 Summary 23
VU1
What is Inductance? 25
3.1 Introduction 25
3.2 Electromagnetic Induction 25
3.3 Mutual Inductance 27
3.4 Self-Inductance 29
3.44 Self-Inductance per Unit Length 33
3.5 Partial Inductance 36
3.6 Summary 40
The Ground Myth 43
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Where Did The Term "Ground" Originate?
What Do We Mean When We Say "Ground"?
4.2.1 Signal Reference
4.2.2 Power Reference
4.2.3 Chassis Reference
4.2.4 Unshielded Cables
4.2.5 Shielded Cables
4.2.6 Earth Safety Reference
"Ground' is Not a Current Sink
Referencing Strategies
4.4.1 Single-Point Ground-Reference
Strategy
4.4.2 Multi-Point Ground-Reference
Strategy
Grounding Heatsinks to PC boards
4.5.1 Heatsink "Grounding" Example
PCB Reference Connection to Chassis
Reference
4.6.1 I/O Area Connection
Summary
43
46
46
49
50
51
54
55
55
55
56
56
58
61
64
64
66
IX
Return Current Design 69
5.1 Introduction 69
5.2 Split Reference Planes 71
5.2.1 Stitching Capacitors 72
5.3 Trace Changing Reference Planes 76
5.4 Motherboards and Daughter Cards 80
5.4.1 Connector Pin Assignments 82
5.5 Summary 83
Controlling EMI Sources
- Intentional Signals 85
6.1 Introduction
6.2 Critical Signals
6.3 Intentional Signals
6.4 Intentional Signals - Loop-Mode
6.5 Controlling Emissions from Intentional
Signals - Loop-Mode
6.6 Intentional Signals - Common-mode
6.7 Intentional Signals - Common-mode
with Interrupted Return Path
6.7.1 Critical Signal Traces Crossing Splits
6.7.2 Critical Signals Through Vias
6.8 Summary
85
86
86
93
95
96
99
99
100
102
7 Controlling EMI Sources
- Unintentional Signals 105
7.1 Introduction 105
7.2 Unintentional Signals 106
7.3 Unintentional Signals - Common-mode 106
7.4 Controlling Emissions from Unintentional
Signals - Common-mode 108
7.5 Unintentional Signals - 'Crosstalk'
Coupling onto I/O Lines 113
7.6 Controlling Emissions from Unintentional
Signals - 'Crosstalk' Coupling to I/O Lines 115
7.7 Summary 118
8 Decoupling Power/Ground Planes 121
8.1
8.2
8.3
8.4
8.5
Introduction
Background
Calculating the Source of Decoupling Noise
8.3.1 Decoupling Noise from ASIC/ICs
power pins
Decoupling Capacitor Effectiveness
8.4.1 Test Board Description
8.4.2 Empty Test Board Configuration
8.4.3 Quantity of Distributed (Global)
Decoupling Capacitors (.Oluf Only)
8.4.4 Quantity of Distributed Decoupling
Capacitors (0.0 luf and 330 pF)
8.4.5 Selecting the Value of the Decoupling
Capacitors
8.4.6 Perfect Decoupling Capacitors
8.4.7 Source Vs Distributed Decoupling
8.4.8 Buried Capacitance Decoupling
8.4.9 Lossy Capacitors
Summary
121
122
124
124
130
131
134
136
137
140
140
141
144
146
148
EMC Filter Design 151
9.1 Introduction 151
9.2 Filter Design Concepts 151
XI
9.3 Filter Configurations 155
9.3.1 Two-Component Filter
Configurations 155
9.3.2 Reference Connection for
Two-Component Filters 157
9.3.3 Three Component Filter
Configurations 161
9.3.4 Single Component Filter
Configurations 163
9.4 Non-Ideal Components and the Impact on Filters 163
9.4.1 Non-Ideal Capacitors 164
9.4.2 Non-Ideal Ferrite Beads 166
9.4.3 Non-Ideal Zero Ohm Resistors 168
9.5 Common-Mode Filters 168
9.6 Summary 169
10 Using Signal Integrity Tools for EMC
Analysis 171
10.1
10.2
10.3
10.4
10.5
10.6
Introduction
Intentional Current Spectrum
Trace Current for Decoupling Analysis
Differential Signals Analysis
10.4.1 Internal Differential Signal Lines
10.4.2 External I/O Differential Signal
Lines
Crosstalk Analysis
Summary
171
172
177
179
181
182
185
185