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Chapter 1
INTRODUCTION
In particular, todays competitive products demand power-efficient design practices. What does
power-efficient design entail? Designers are using ever-lower voltages wherever practical in a
design, reserving higher voltages for those portions of the design that truly require the additional
power. While power-efficient designs may contain several different voltages, there are often
tens, or even hundreds, of power domainsdiscrete portions of the design that can be turned on
and off to minimize power usage. Accurate and efficient low-power and multiple-power domain
verification requires both knowledge of the overall systems power intent and careful tracking of
signals crossing these power domains. The ability to evaluate the interactions of different power
states at the transistor level, where bulk connections, floating wells, and other physical
implementation details can be verified, is critical to avoid latch-up conditions and ensure high
reliability compliance.
Typical hardware description language (HDL) design and checking tools can verify digital
designs at the module level, accurate reliability verification must happen at the transistor level.
Calibre PERC provides a new approach to reliability verification for low-power and multi-
power designs, by leveraging the information contained in the unified power format (UPF) and
applying it to transistor-level designs. The UPF provides a way to annotate a design with the
power and power control intent of that design (including such elements as supply nets, supply
sets, power states, power switches, level shifters, isolation, and retention) that is independent of
any HDL. UPFs are typically used at all levels of the design flow for P&R designs.
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Chapter 2
BACKGROUND
The increasing demand for highly reliable products covers many industries, all process
nodes, and almost all design implementations. To satisfy this demand, reliability requirements
are growing in all market segments. Ensuring these requirements are met requires design
verification that goes beyond traditional design rule checking (DRC), layout vs. schematic
(LVS) comparison, and electrical rule checking (ERC). Small and large process nodes alike are
affected by these requirements, while both system-on-chip (SoC) and full custom designs also
need comprehensive reliability coverage.
In particular, todays competitive products demand power-efficient design practices.
What does power-efficient design entail? Designers are using ever-lower voltages wherever
practical in a design, reserving higher voltages for those portions of the design that truly require
the additional power. While power-efficient designs may contain several different voltages,
there are often tens, or even hundreds, of power domainsdiscrete portions of the design that
can be turned on and off to minimize power usage. Accurate and efficient low-power and
multiple-power domain verification requires both knowledge of the overall systems power
intent and careful tracking of signals crossing these power domains. The ability to evaluate the
interactions of different power states at the transistor level, where bulk connections, floating
wells, and other physical implementation details can be verified, is critical to avoid latch-up
conditions and ensure high reliability compliance.
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Power-efficient reliability requirements apply to both low power/low voltage and high
power/high voltage designs. If theres a memory cell, high-voltage gate, or other element with
signals that are not directly compatible with the rest of the design, the designer must make sure
there is adequate isolation and protection to ensure a design is created that is reliable under all
operating conditions. Level shifters are often used between different voltages to ensure smooth
transitions (Figure 1), while retention cells are often employed to preserve a circuits input
values when its domain is switched off.
Figure 2.1: On the left, a level shifter is used to provide a safe transition between differing
voltages, while on the right, a retention cell is used to preserve input values.
Designs that incorporate multiple power domain checks are particularly susceptible to
subtle design errors that are difficult to identify using SPICE simulations or traditional physical
verification techniques. These subtle errors often dont result in immediate part failure, but
performance degradation over time. Figure 2 shows a transistor connected to different VCCs. If
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the VCCs are the same voltage, but in different domains, they may be switching on and off at
different times, leading to reliability issues. This type of error is going to be very difficult to
catch in a SPICE simulation. If VCC2 has a greater voltage than VCC1, the device is at risk for
gate oxide breakdown, a long-term reliability issue.
Place and route (P&R) tools most commonly deal with gate-level blocks. Because verification
in that environment does not go down to the transistor or well level to validate transistor biasing,
problems like the one shown in Figure 2 will not be identified during the P&R process.
Transistor-level power intent verification is a critical need, especially in designs that make
extensive use of IP. SOCs can contain any number of IPs from different providers, many of
which may use different power designs or contain their own internal global signals, and each IP
must be hooked up correctly within the design. Without an understanding of the power intent of
each IP, its very difficult to proactively prevent reliability issues (such as power domain
crossing errors) from occurring when the IP is placed into a larger design. In Figure 3, the
voltages internal to the IP block look consistent, but its been hooked up incorrectly in the larger
implementation. Also, as stated before, even if the voltages are equal, if they are in different
power domains, they may be switching on and off at different times, leading to additional
reliability issues.
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Figure 2.2: A transistor connected to two different VCCs is susceptible to long-term
performance degradation and reliability issues.
Another factor in these designs is the use of thinner oxides that allow designers to use
lower voltage, and subsequently, less power. These desirable effects are offset by the sensitivity
of these circuits to electrical overstress (EOS) issues. In addition, some power domain design
errors lead to eventual oxide breakdown, which results in device failures that occur over time. In
particular, PMOS devices can be susceptible to negative-bias temperature instability (NBTI),
which leads to the threshold voltage of the PMOS transistor increasing over time. This, in turn,
leads to reduced switching time for logic gates, and induces hot carrier injection (HCI), which
then gradually alters the threshold voltage of NMOS devices. Soft breakdown (SBD) also
contributes as a time-dependent failure mechanism, contributing to the degradation effects of
gate oxide breakdown
A transistor-level power-aware checking tool must also be able to statically propagate
voltage values from the various supplies to every node in the circuit to facilitate a variety of
reliability checks. Power-aware checking requires the ability to use the designs netlist to
recognize specific circuit topologies (such as level shifters, charge pumps, I/O drivers, and other
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structures), and then relate those to the corresponding physical implementation that makes up the
layout, to verify that these specific elements have been included and implemented correctly.
Unlike the foundry DRC decks, the definition of these checks may not all come from the
foundrysome can be tailored to the specific design styles and practices of the designers
companyso flexibility and customizability are essential features. Thin oxide gates and high-
power applications require tight controls for voltage and power domains. Many of these issues
are difficult to identify in the simulation space or with traditional physical verification
techniques.
Figure 2.3: IPs pose two levels of reliability certification challengesinternal verification, and
verification in the context of a larger implementation.
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Chapter 3
CALIBRE PERC: The Next Evolution of Circuit Reliability Verification
3.1 Introduction to Calibre perc
Reliability is a growing concern for integrated circuit (IC) designers, especially in
products such as communications, medical, and transportation, where reliability and
performance are not just market differentiators, but critical components of safe and effective
operation. Many reliability checks are difficult to check using traditional DRC, LVS and ERC
tools, and can potentially affect a wide range of IC designs. Electrostatic discharge (ESD),
electrical overstress (EOS), and latch-up are just some of these complex geometrical and
electrical errors that can result in reduced yield, defect escapes to customers, and delayed
failures in the field.
Advanced reliability verification ensures the robustness of a design both at schematic and
layout levels by checking against various electrical and physical design rules that define IC
performance standards and reduce susceptibility to premature or catastrophic electrical failures.
Calibre PERC is specifically designed to perform a wide range of complex
reliability verification tasks using both standard rules from the foundry and custom rules
created by a design team. Users can insert reliability verification into their existing design
flows with Calibre PERC as part of an integrated Calibre platform for cell, block, and full-chip
verification. Combining rules expressed in SVRF and the Tcl-based TVF language across all
applications provides users with flexibility to meet the specific and evolving needs of their
design teams, while ensuring compatibility with all foundries.
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Contrary to traditional electrical checks using a single device/pin to net relation, reliability
requirements can often only be described by a topological view that combines both circuit
description and physical devices. Calibre PERCs ability to use both netlist and layout (GDS)
information simultaneously to perform electrical checks that incorporate both layout-related
parameters and circuitry-dependent checks enables designers to address these complex
verification requirements. In addition, Calibre PERC can employ topological constraints to
verify that the correct structures are in place wherever circuit design rules require them.
Calibre PERC can automatically identify complex circuit topology on a design netlist, either
streamed from the schematic or extracted from the layout. It examines the specific constraints
defined by the design team, whether they are electrical or geometrical. Calibre PERC rule decks
may be easily augmented to provide verification beyond standard foundry rule decks to include
custom verification requirements.
3.2 Advanced Reliability Verification
At all process nodes, countless hours are diligently expended to ensure that our integrated
circuit (IC) designs will function in the way we intended, can be manufactured with satisfactory
yields, and are delivered in a timely fashion while meeting the market need. Traditional IC
verification relies on a collection of well-known and well-understood tools. Design rule checking
(DRC), layout vs. schematic comparison (LVS), electrical rule checking (ERC), parasitic
extraction (PEX), design for manufacturing (DFM) and simulation (most often SPICE and
timing closure) are all used as part of this cohesive verification flow that provides us the insight
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required to find and correct any errors or omissions in our design process. Many design errors
lead to hard failures in manufacturing, and can be readily identified and fixed, like a metal width
that is too small for a process node layer, cells that were incorrectly placed, or shorts across other
elements in the design. Finding and fixing these issues is the mainstay of IC verification.
3.2.1 The legacy of simulation
SPICE simulation, and the associated parasitic extraction that it uses, plays a vital role in
identifying less obvious errorsthose that deal primarily with reliability. Ensuring that you have
the correct simulation vectors to provide sufficient coverage while validating the waveforms or
analyzing messages from your simulation environment can be time-consuming and CPU-
intensive activities, where results often require both expert interpretation and the keen eye of
someone who understands the subtleties of each particular design.
3.2.2 Finding scalable alternatives
Whichever Greek philosopher first said that necessity is the mother of invention must
have foreseen the challenges that the IC industry would one day face. Time and again, when
faced with a new set of requirements not addressed by existing tools, engineers have leveraged
their imaginations to create innovative solutions, designs, and process flows.
The same is true for reliability verification. With larger designs, smaller process nodes,
and the increased pressure on time-to-market schedules and productivity targets, many design
teams are turning to new alternatives that provide critical advantages over existing tools:
a simple-to-use environment for the designer and verification engineer,
fast runtime (that can scale to the full chip),
a cohesive platform that is able to validate a wide range of issues.
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One tool that has found a strong role in reliability verification is Calibre