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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1
High Fill Factor Low-Voltage CMOS Image
Sensor Based on Time-to-Threshold PWM
VLSI Architecture
Kyoungrok Cho, Member, IEEE, Sang-Jin Lee, Student Member, IEEE,
Omid Kavehei, Member, IEEE, and Kamran Eshraghian
AbstractThis paper presents a CMOS image sensor
(CIS) VLSI architecture based on a single-inverter time-to-
threshold pulsewidth modulation circuitry capable of operating
as low as 330-mV supply voltage while retaining a signal-to-noise
ratio of 24 dB; an important characteristic being demanded by
very low voltage portable CIS-based equipment such as dispos-
able medical cameras and on-chip autonomous wireless security
vision systems. A 64 64 pixel array was fabricated using
standard 130-nm CMOS process consuming only 5.9 nW/pixel
with integration time of 2 ms at +0.5 V supply. The high ll
factor of 58% facilitated a better SNR at a low supply voltage
when compared with other CIS architectures. The pixel has a
dynamic range of 54 dB with 7.8 frame per second.
Index TermsCMOS image sensors (CIS), pulsewidth
modulation (PWM), time-to-threshold conversion.
I. INTRODUCTION
T
O GAIN an economic advantage in the crowded solid-
state image sensor arena, last decade has seen numerous
approaches toward formulation of new architectures for imple-
mentation of CMOS image sensor (CIS) technology [1][3].
With the advent of deep submicrometer CMOS process, it
is now possible to build high-performance single-chip cam-
eras capable of integrating both image capture and advanced
on-chip computational circuitry [4], [5]. The low output volt-
age swing brought about by technology scalinga common
characteristic of a class of visual sensory processorssuch as
the CMOS active pixel sensor (APS) designs, has resulted in
both poor signal-to-noise ratio (SNR) as well as a noticeable
degradation in the dynamic range. The minimum achievable
pixel size is primarily limited by the imaging optics as well
as the light aliasing factors. To address the inadequacies of
Manuscript received November 21, 2012; revised March 31, 2013 and
June 13, 2013; accepted July 25, 2013. This work was supported in part
by Mid-Career Researcher Program under Grant 2011-0015702 through an
NRF grant funded by the MEST. The chip was fabricated by IDEC.
K. Cho and S.-J. Lee are with the College of Electrical and Computer
Engineering, Chungbuk National University, Cheongju 561-756, South Korea
(e-mail: krcho@chungbuk.ac.kr; sjlee@hbt.cbnu.ac.kr).
O. Kavehei is with the Centre for Neural Engineering, University of
Melbourne, Parkville 3010, Australia (e-mail: omid.kavehei@unimelb.edu.au).
K. Eshraghian is with the College of Electrical and Computer
Engineering, Chungbuk National University, Cheongju 561-756, South Korea,
and also with iDataMap Corporation, Subiaco 6008, Australia (e-mail:
keshraghian@idatamap.com).
Color versions of one or more of the gures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TVLSI.2013.2275161
scaled CMOS technology, integration of additional computa-
tional circuitry within the pixel without affecting the pixel
size becomes necessary [3]. The development of digital pixel
sensor (DPS) based on on-pixel analog-to-digital converter
(ADC) addresses some of the concerns and facilitates in
achieving a higher SNR [6]. Architectures through the incor-
poration of pixel-based ADC and related memory provide
adoption of a more aggressive image processing for high-
speed digital readout as an option. Multiple image capturing
schemes and asynchronous self-reset techniques have also
been proposed offering a solution for improving the dynamic
range [7], [8]. The data processing circuitry to extend the
dynamic range in such architectures, however, increases the
complexity of periphery circuits. Time-based DPS options
have also been proposed to enhance the dynamic range [6]
whereby the output of a time-based DPS is made dependent
upon the number of pulse counts during a predetermined
integration cycle established by the time taken for the pho-
toresponse signal to exceed a threshold voltage. The drawback
for most of the DPS implementations is that under low
illumination, the output remains static within the predeter-
mined integration period. Therefore, the sensor tends to lose
image capture capability and hence the need for larger pixel
area [9].
In conventional CIS, the output from a pixel is analog.
To realize smart functions such as current mode, digital mode
or pulse processing modes have been introduced as options.
Digital and pulse mode image sensors having a good ll factor
are, however, difcult to achieve [10]. The approach pursued
in CISs based on pulsewidth modulation (PWM) architecture
incorporates a CMOS inverter as a comparator within a
pixel. The technique creates additional pixel area allowing
for the incorporation of additional processing circuitry [10].
Eklund et al. [11] adopted an inverter as a light intensity to
time convertor. A single inverter as a comparator based on
single-photon avalanche diodes was also introduced in [12].
Niclass and Rochas [13] implemented a similar architecture
based on time-of-ight for 3-D vision system. Culurciello [14]
proposed a biologically inspired readout method to imple-
ment a biomorphic digital image sensor where inverters were
adopted as comparators for generating a spike (a 1-bit pulse)
derived from the photodiode (PD) output. Guo et al. [15], [16]
formulated the concept of time-to-rst spike (TTFS) whereby
the pixel transforms the luminance into pulse events in the
1063-8210 2013 IEEE
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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 1. Time-to-threshold PWM architecture. (a) Logical architecture illustrating composition of PWM pixel array, control circuits, and time-to-threshold
converter (TTC). (b) Schematic diagram of TTC block. (c) Timing waveform showing the behavior of pixel integration including reset and enable phases, and
time-to-threshold conversion based on row-by-row operation.
time domain. These approaches have relatively low ll factor
and hence their performance is compromised in low-voltage
applications.
On-chip autonomous wireless security cameras and dispos-
able medical imaging systems and the like require adoption
of technologies that can operate under low voltage, consume
low power and are compatible with deep submicrom processes.
Therefore, instead of using the more conventional APS, PWM
imaging has become a popular approach that overcomes the
limited signal swing encountered under low-voltage operation
[17][19]. Kagawa et al. [17] achieved 3.6 pW/frame pixel
with 1.35 V supply voltage using dynamic pixel-by-pixel
readout approach. Chung et al. [18] proposed threshold
variation noise canceling scheme with high dynamic range
and 2.98 pW/frame pixel under 0.5 V supply voltage.
Hanson et al. [19] employed an in-pixel two-transistor com-
parator with column-shared current limiter that gave 23.4 dB
of SNR at 0.5 V supply voltage and consuming 8.6 pW/frame
pixel. Achievement of the ultralow power consumption,
however, requires aggressive supply voltage scaling and the
need for introduction of control techniques that consequently
limit the frame rate. This approach is susceptible to supply
voltage variation.
In this paper, we present a novel CIS VLSI architecture
that uses a single-inverter time-to-threshold PWM circuitry
incorporating an offset reduction scheme fabricated using
130-nm CMOS technology. The signicant feature of the
imager is that it operates successfully at a supply voltage as
low as 330 mV while retaining a SNR of 24 dB because of
the pixels high ll factor of 58%. The pixel dissipates only
5.9 nW while keeping a dynamic range of 54 dB at 7.8 fps
under 500-mV supply voltage.
This paper is organized as follows. Section II introduces
the new CIS architecture using a single-inverter sensor cir-
cuitry. This is followed by Section III whereby focus is
directed toward the experimental results and CIS charac-
terization, and nally, Section IV provides the concluding
remarks.
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CHO et al.: HIGH FILL FACTOR LOW-VOLTAGE CIS 3
Reset
Photo
-diode
C
PD
V
th
V
RST
Comparator
PD
V
th
V
RST
V
P
D
Reset
OUT
V
OUT
0 1
Fig. 2. Basic circuit conguration and characteristics of image acquisition
sensor architecture based on PWM. PWM produces an output signal whenever
the signal accumulation reaches a threshold value.
II. CMOS DIGITAL IMAGER LOGICAL ARCHITECTURE
A. Time-to-Threshold PWM Imager Architecture
The logical architecture for the time-to-threshold PWM
imaging system is shown in Fig. 1(a). It includes PWM pixel
array, control circuits, and TTC [Fig. 1(b)]. Timing waveforms
of pixel integration including reset and enable phases, and
time-to-threshold conversion based on row-by-row operation
are shown in Fig. 1(c). In M N CIS array, a pixel P
i, j
is in
readout mode when the row signal reset_i is low and the row
enable_i is high.
B. PWM-Based CIS
Fig. 2 shows the fundamentals of image acquisition sensor
architecture based on PWMan extension of pulse modu-
lation (PM). In this construct, the output signal is produced
whenever the signal reaches a threshold value [21]. The digital
form of output is compatible for asynchronous operation such
as various self-resetting schemes. Because the PM sensor acts
as an ADC, the architecture is highly suitable for on-chip
signal processing applications [8], [22]. A column line of the
PWM readout is driven by digital form of a comparator having
a higher drive current than a source follower of the 3T APS.
This facilitates the output signal to be more identiable [19].
C. Comparator Structure Using Single-Inverter CIS
The pixel-based CIS architecture uses a single-inverter
sensor circuitry. The basic pixel structure shown in Fig. 3(a)
includes a PD, a single CMOS inverter, two reset nMOS tran-
sistors M1 and M2, and the two nMOS transistors M3 and M4
to enable the pixel output.
The operation is initiated with the reset signal being
asserted. Node PD [Fig. 3(a)] commences to charge up toward
+V
DD
, followed by the integration phase whereby the reset is
switched to logic 0 and the enable signals is switched logic 1.
The PD enters a oating mode during this period. Upon
illumination on PD, the photocurrent created by generation of
electronhole pairs results in the voltage +(V
DD
V
TH
) at node
PD to decrease as a function of the intensity of incident light
that falls on the PD. The node voltage PD drives the inverter
for time-to-threshold modulation. By careful geometric con-
siderations, it becomes possible to minimize the deviation
of the logic threshold voltage that may be encountered as
the result of process parameter variations. Associated gain
of the inverter is large and therefore the inverter gain will
have a minor effect on the process variation. The inverter in
(a)
(b)
PD
Photo
-diode
M1 M2
M
3
M
4
enable
reset
V
DD
c
o
l
u
m
n

l
i
n
e
V
o
l
t
a
g
e

(
m
V
)
500
400
300
200
100
100 200 300
0
Reset
Vcolumn_line
VPD
PW1
PW2
Threshold
t trigger_1
t trigger_2
Fig. 3. Pixel architecture based on utilization of a single-inverter CIS whereby
nMOS transistors M3 and M4 enable the pixel when asserted. (a) Circuit
schematic diagram. (b) Pixel simulation at 500-mV supply voltage illustrating
illumination being converted to a voltage level, thus establishing the time-to-
threshold PWM for A/D conversion. High illumination results in faster voltage
drop whereas low illumination makes the discharge slower. t
trigger_1
is the
higher level of illumination whereas t
trigger_2
is the lower level of illumination.
submicrometer technology ensures that the threshold variation
is minimal assuring stability at low power supply [20].
The t
trigger
shown in Fig. 3(b) is determined by the level
of illumination, which is converted to a voltage level, thus
establishing the time-to-threshold PWM for analog-to-digital
(A/D) conversion. High illumination results in faster voltage
drop, whereas low illumination makes the discharge slower.
The output of the inverter is mapped to corresponding dig-
ital pulses with variable width according to the change of
the voltage at PD node. The time-to-threshold conversion is
incorporated at the end of column lines to realize digital data
instead of deployment of the more conventional ADC.
D. Pixel Characterization
Local variations in threshold voltage are not negligible, and
can cause differences in performance between two neighboring
pixels. The differences between the individual pixels in the
array result in variations in the analog readout, which cul-
minates in the xed pattern noise (FPN). The two important
sources of errors are: 1) variation in gain and 2) offset of the
comparator. Because the gain in the comparator is large, the
local gain variation will have a minor effect. However, the PD
gain, namely the sensitivity to illumination and the leakage
current, are difcult to control. Therefore, the comparator
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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
-12
10
-11
10
-10
Photocurrent (A)
t
(
m
s
)
t
r
i
g
g
e
r
DR w/ M2
DR w/o M2
w/ M2
w/o M2
Fig. 4. Inuence on the t
trigger
with and without the incorporation of nMOS
transistor M2 to reduce the inuence of offset voltage between input and
output of the invertor at 500-mV supply voltage.
offset is the only parameter available for optimization [14].
M2 shown in Fig. 3(a) reduces this offset to a signicant
degree. The simulation result for the pixel with M2 and
without M2 is shown in Fig. 4. During reset, input and output
nodes of the inverter are precharged at +V
DD
/2 thus reducing
the offset voltage between input and output of the inverter
by providing the same amount of charge to the intersection
of M2, M3, and the inverter input at the commencement of
enable phase. M2 effectively enhances the pixel response at
low illumination and hence a noticeable improvement in the
dynamic range (DR) is achieved.
E. DR and SNR
The transferred response between output trigger time t
trigger
and illumination intensity of PWM readout architecture is
dened by the relation between V
PD
and the threshold voltage
of inverter V
TH_inv
modeled by
V
PD
= V
PD_RST

I
ph
C
PD
t

(1)
where V
PD_RST
corresponds to +(V
DD
V
TH
), I
ph
is the pho-
tocurrent as a function of illumination, C
PD
is the PD node
capacitor, and V
TH
is the threshold voltage. If V
PD
drops below
V
TH_inv
from V
PD_RST
during the integration time T
int
, the
output triggers to high voltage level.
A time-dependent imaging architecture requires longer inte-
gration time when compared with the more conventional
analog circuits. The amplifying behavior provided by the
inverter within the pixel is degraded by 4.5%/100 mV of
supply voltage drop. Thus, the integration time needs to be
adjusted accordingly by the same ratio in relation to the
degradation of the gain.
For the sake of reducing the complexity of our model and
to gain insight into the parameters that really matter in the
model, we have assumed that the pixel is offset free (of course,
noting that the issue of offset has already been addressed in
Section II-D), which naturally implies C
PD
becomes indepen-
dent of its reverse biased voltage, and I
ph
is constant during
6
5
4
3
2
1
0
0.32 0.36 0.40 0.44 0.48
V (V)
DD
A
v
e
r
a
g
e

P
i
x
e
l

P
o
w
e
r

(
n
W
)
T =0.5ms
int
T =1.0ms
int
T =2.0ms
int
Fig. 5. Average power dissipation per pixel under dark illumination condition
as a function of V
DD
with varying integration times 0.5, 1.0, and 2.0 ms.
the integration and trigger time. If trigger time is shorter than
T
int
, the behavior can be described by
t
shortest
= (V
PD_RST
V
TH_inv
)

C
PD
I
ph,max

(2)
t
longest
= (V
PD_RST
V
TH_inv
)

C
PD
I
ph,min

. (3)
If the readout noise and dark current level are neglected,
then the DR can be expressed as follows:
DR = 20 log

t
longest
t
shortest

= 20 log

I
ph,max
I
ph,min

. (4)
Although dark current is negligible with 1/30-s integration
time using 5-m pixel pitch [23], its inuence upon the pixel
output is not negligible at dark light level when the pixel is
subjected to a low-voltage operation. Furthermore, the market
dictates the need for standard CMOS process to be used for
fabrication to ensure economic advantage. Unfortunately, the
standard CMOS process immediately introduces additional
adverse effects on the amount of dark current brought about
as the result of nonoptimal process and hence becomes the
limiting factor for minimum detectable illumination level as
described by t
longest
. In addition for a pixel, the t
longest
is
also limited by pixel temporal noise. The node voltage on the
PD is evaluated with single inverter and a time-to-threshold
conversion using a counter.
SNR can be described by
SNR = 20 log

N
T

(5)
where the total number of count, N
T
[Fig. 1(c)], is a time to the
logic threshold of the inverter. Noise on the pixel inuences
the logic threshold of the inverter, as shown in Fig. 3(a),
introduces uctuation in the number of clock count n. Here,
is the standard deviation of n in the time domain. In this
architecture, there are two dominant noise sources: 1) PD shot
noise and 2) inverter gain variation. These noises are affected
to the inverter switching and can be formalized with n in (5).
If the noise sources attributed to n become smaller than
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CHO et al.: HIGH FILL FACTOR LOW-VOLTAGE CIS 5
A
r
e
a

(


m

)
2
# of Pixels (HxV)
10
7
10
6
10
5
10 k 100 k 1 M 10 M
This work
[19]
[26]
[25]
[24]
[27]
Fig. 6. Comparison of area occupancy using 130-nm CMOS process
technology for several digital conversion schemes for a specied resolution.
logic threshold, then it can be neglected in the PWM readout
circuitry. Note that the proposed circuit has minimal FPN noise
on a column line because the signal on the column line was
already converted to digital level.
F. Power Dissipation
In the proposed pixel shown in Fig. 3(a), the node voltage
at PD and reset transistor M1 makes the transitions according
to the intensity of incident light. The gradual variation of
the slope driven by the illumination intensity brings about
ow of short circuit current of the inverter in the pixel.
Therefore, power dissipation of CIS chip depends on the
illumination intensity. Fig. 5 shows the power dissipation per
pixel under dark light condition as a function of V
DD
with
varying integration times. Under dark condition, the maximum
dissipation is 5.9 nW at 500-mV supply voltage corresponding
to 2-ms integration time. The power dissipation decreases
exponentially when the illumination intensity increases. The
pixel architecture provides a nonlinear transfer characteristics
within a single sampling cycle.
G. Time-to-Threshold Conversion Technique
For image processing, an A/D circuitry converts pixel
response to a digital value based on the incident illumination
intensity. Various schemes of column-parallel A/D conversions
such as deltasigma, successive approximation, single slope,
and cyclic ADCs [24][27] are adopted in CIS to improve the
frame rate. In our architecture, a time-to-threshold conversion
approach is implemented to obtain the digital value instead of
the more conventional ADC-based techniques. The counter in
the VLSI architecture (Fig. 1) is synchronized with a rising
edge of an enable signal. The output of the counter shown
in Fig. 1(b) is distributed for every N-bit register in the
architecture. Pixel output signal column_line is used as a clock
signal for D ip-ops, which retain the output until the next
column_line is triggered. In our approach, the TTC uses a
10-bit global counter and column-parallel registers. The area
of the TTC is estimated for over 10-megapixel-sized CIS and is
compared with the reported conventional ADC schemes. Fig. 6
shows the area utilization compared with several published
works [19], [24][27].
(a) (b)
64 x 64
Pixel Array
R
e
s
e
t

D
e
c
o
d
e
r
E
n
a
b
l
e

D
e
c
o
d
e
r
Reset/Enable Generator
Fig. 7. Fabrication of the imager using 130-nm CMOS technology.
(a) Micrograph of fabricated 64 64 CIS test chip. (b) Pixel layout based
on single inverter and four nMOS transistors per pixel.
S
N
R

(
d
B
)
40
30
20
10
0
10
1
10
2
10
3
Fig. 8. SNR measurement under different illumination levels at 7.8 fps and
500-mV supply voltage.
III. FABRICATION AND EXPERIMENTAL RESULTS
A. CIS Fabrication
Fig. 7 shows the micrograph of a 64 64 CIS prototype
having a pixel pitch of 5 m, fabricated using 130-nm
N
+
/P-sub-CMOS technology. It should be noted that the
sensitivity of N-well/P-sub PD is higher than N
+
/P-sub. The
N-well/P-sub PD, however, results in lower ll factor or larger
pixel dimensions. Therefore, in our design, we adopted the
N
+
/P-sub process to minimize the pixel size [9], resulting in
a high ll factor of 58%.
B. Experimental Results
An experimental platform was designed using a commercial
logic analyzer. The imagers pulsewidth output is acquired and
analyzed on a PC platform. The image sensor chip operates
within the range of +330 mV to +1.2 V supply and a
range of 7.831 fps. The higher ll factor inuences SNR, in
particular, when CIS is required to function at very low supply
voltage level demanded by more recent portable image sensor
equipment. The SNR shown in Fig. 8 was measured under
different illumination levels at 7.8 fps and 500-mV supply
voltage. The measured peak SNR was 42 dB at 1400 lx.
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6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
TABLE I
SUMMARY OF PROTOTYPE FEATURES
2 4 6 8
N
u
m
b
e
r

o
f

P
i
x
e
l
s
10
8
6
4
2
0
-8 -6 -4 -2 0
Fig. 9. FPN measurements. Histogram showing number of pixels that has
same deviation of the digital pixel value from mean of an averaged frame.
The general chip characteristics and performance are summa-
rized in Table I.
The FPN was evaluated as the standard deviation of pixel
values normalized with respect to the mean value of several
frame data temporally and spatially under at eld illumi-
nation. To minimize random noise, 54 frames of the same
image were acquired and averaged from the at eld images.
Histogram in Fig. 9 shows the FPN of the fabricated chip. The
standard deviation was found to be 2.5 LSB for the FPN.
Off-chip digital FPN correction could be applied to reduce the
level of FPN by a factor of at least 30 [28].
The transfer characteristic of the proposed pixel in
Fig. 3(a) has a logarithmic-like response, which is similar to
the response of human eyes to illumination. There are other
reported DPSs having nonlinear transfer behavior by capturing
multiple output signals with different integration time [9]. The
complexity of some of the approaches, however, necessitates
more signal processing circuitry resulting in complex readout
circuits and hence more dynamic power dissipation.
Fig. 10 shows dynamic illumination response of the fabri-
cated sensor with a maximum detectable illumination intensity
of >10000 lx. The nonlinearity of the pixel response between
minimum illumination and 1000 lx is 6.2% by assuming an
ideal straight line on this region. To improve the linearity,
an exponential counter or nonlinear clock generator for the
O
u
t
p
u
t

C
o
d
e
300
250
200
150
100
50
10
0
10
1
10
2
10
3
10
4
0
Fig. 10. Dynamic illumination response of the sensor with a maximum
detectable illumination intensity of >10000 lx. The nonlinearity of the pixel
response between minimum illumination and 1000 lx is 6.2%.
Frame
Rate
3.9 fps 7.8 fps 15.6 fps
Supply
Voltage
400 mV
600 mV
800 mV
Fig. 11. Captured images for a discrete resistor with a xed illumination level
and variations of supply voltage source and the frame rate. Supply voltage was
varied from 400 to 800 mV with 200-mV steps, whereas frame rate varied
from 3.9 to 15.6 fps. Features of the image are fully recognizable at the
extreme end of operating spectrum, namely 400 mV and 3.9 fps, considering
the test chip is only a 64 64 array.
pulse counter can be implemented at the output stage [29].
The measured dynamic range with 8-bit resolution has been
limited to 54 dB because of larger than expected dark current
of the PD using standard CMOS process under low supply
voltage.
Captured images without postprocessing from the test chip
are shown in Fig. 11. The images captured a discrete resistor
with a xed illumination level and variations of supply voltage
and frame rate. Supply voltage was varied from 400 to 800 mV
with 200-mV steps, whereas frame rate varied from 3.9 to
15.6 fps. The measured power consumption for the 64 64
array is 2.2 W under a dark condition with 330-mV supply
voltage at 7.8 fps.
Summary of characteristics and expected performance of the
CIS architecture, when compared with the published works,
such as [17][19] is shown in Table II. The ll factor of 25.4%
in [18] reects the higher silicon utilization, and therefore the
work in [19] is used for the purpose of comparison. Fig. 12
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CHO et al.: HIGH FILL FACTOR LOW-VOLTAGE CIS 7
TABLE II
COMPARISON BETWEEN PWM IMAGERS
S
N
R

(
d
B
)
V
DD
(V)
30
28
26
24
22
20
18
16
14
0.45 0.50 0.55
0.35
30
25
20
15
This work
[19]
0.40 0.45 0.50
0.60 0.65 0.70
Fig. 12. Comparison of SNR measurement under xed illumination while
the supply voltage was varied between the two-transistor comparator using
current limiter [19] with our approach using time-to-threshold PWM archi-
tecture. Inset provides a better insight into SNR <450 mV between the two
approaches.
shows the achieved improvement in SNR when supply voltage
is <500 mV.
Power per pixel of the fabricated test chip was 69.1 and
13.6 pW at 7.8 and 31 fps, respectively, when operated at
330-mV supply voltage being highly useful as part of the
mobile applications.
The limitation may emerge as the result of: 1) the depen-
dency of power consumption on the light variation. For exam-
ple, at dark light, the very slow change in voltage during the
integration phase at the PD node and the inverter will cause an
increase in short-circuit power consumption and 2) response
of the imager is not a linear function with variation of
illumination intensity (Fig. 10) because of the xed threshold
voltage of the inverter. Because the objective of the approach
is, however, to address low-voltage operational requirements
having reasonable SNR for the mobile applications, the listed
limitations are of no consequence in our target application.
IV. CONCLUSION
The proposed time-to-threshold PWM VLSI architecture
using standard 130-nm CMOS technology has shown promise
in terms of robustness in design, high ll factor, good SNR,
and the ability to operate down to 330-mV supply voltage.
The output of the inverter and hence the readout is mapped
onto a variable-width digital pulse according to the inci-
dent illumination intensity. This architecture provides different
pulsewidths that correspond to the level of luminance instead
of the number of reset events when compared with TTFS
approaches. The architecture does not require an ADC and
is highly compatible with parallel implementation of imaging
schemes. Data derived from a fabricated 64 64 sensor array
suggested the maximum power dissipation of 5.9 nW/pixel,
dynamic range of 54 dB with 8-bit resolution input at 7.8 fps,
and 500-mV V
DD
. Furthermore, a high ll factor of 58% is
also achieved, yielding better SNR at low supply voltage. Each
pixel occupies an area of 5 m 5 m. The sensor is capable
of operating at 450 mV with a SNR of 26 dB and as low as
330-mV supply voltage a highly desirable condition for low-
power portable imaging systems such as disposable medical
cameras and on-chip autonomous wireless security cameras
where prolonged life cycle is expected.
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Kyoungrok Cho (S89M92) received the B.S.
degree in electronic engineering from Kyoungpook
National University, Taegu, Korea, in 1977, and the
M.S. and Ph.D. degrees in electrical engineering
from the University of Tokyo, Tokyo, Japan, in 1989
and 1992, respectively.
He was with the TV Research Center of LG
Electronics in Korea from 1979 to 1986. He is cur-
rently a Full Professor with the College of Electrical
and Computer Engineering, Chungbuk National Uni-
versity, Chungcheongbuk-do, Korea. From 2008 to
2011, he was the Director of World Class University Program with Chungbuk
National University. In 1999 and 2006, he was with Oregon State University,
Corvallis, OR, USA, as a Visiting Scholar. His current research interests
include high-speed and low-power circuit design, SoC platform design
for communication systems, prospective CMOS image sensors, memristive
devices and memristive systems, and design of multilayer system-on-systems
technology.
Dr. Cho was a recipient of the Institute of Electronics Engineers of Korea
(IEEK) Award in 2004. He is a member of IEEK.
Sang-Jin Lee (S10) received the B.S. degree in
chemical engineering and M.S. degree in informa-
tion and communication engineering from Chungbuk
National University, Cheongju, Korea, in 2008 and
2010, respectively, where he is currently pursuing
the Ph.D. degree with the Graduate School.
His current research interests include design of
multilayer system-on-systems technology with par-
ticular emphasis on memristive architectures, CMOS
image sensors, and cryptographic and embedded
systems. He was a member of the World Class
University Program, Chungbuk National University.
Omid Kavehei (S05M12) received the Master of
Engineering degree from Shahid Beheshti University
(National University of Iran), Tehran, Iran, in 2005,
and the Ph.D. degree from The University of Ade-
laide, Adelaide, Australia, in 2012.
In 2011, he took up an appointment as a Research
Fellow with The University of Melbourne, Mel-
bourne, Australia. He was an Executive Member of
the SA IEEE student chapter with the University
of Adelaide. In 2008, he received an Endeavour
International Postgraduate Research Scholarship.
Dr. Kavehei was a recipient of the DR Stranks Traveling Fellowship from
UoA, Simon Rockliff Scholarship from the Defense Science and Technology
Organization for the most outstanding postgraduate mentorship, Research
Abroad Scholarship from UoA, and the World Class University program
research fellowships. He is also the recipient of the Deans Commendation
for Doctoral Excellence and a University Research Medal.
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
CHO et al.: HIGH FILL FACTOR LOW-VOLTAGE CIS 9
Kamran Eshraghian received the B.Tech.,
M.Eng.Sc., and Ph.D. degrees from the University
of Adelaide, Adelaide, Australia, in 1969, 1977,
and 1980, respectively, and the Dr.-Ing e.h. degree
from the University of Ulm, Ulm, Germany, for his
research into integration of nanoelectronics with
that of light wave technology.
He is best known in the international arena as
being one of the fathers of CMOS VLSI having
inuenced two generations of researchers in both
academia and industry. In 1979, he joined the
Department of Electrical and Electronic Engineering, University of Adelaide,
after spending some ten years with Philips Research in Australia and Europe.
In 1994, he was the Foundation Chair of computer, electronics and communi-
cations engineering in Western Australia, and became the Head of the School
of Engineering and Mathematics, and Distinguished University Professor.
He subsequently became the Director of the Electron Science Research
Institute. In 2004, he became the Founder/President of Elabs as part
of his vision for horizontal integration of nanoelectronics with those of
bio and photon-based technologies, thus creating a new design domain
for system-on-system integration. In 2007, he was an inaugural Fer-
rero Family Chair of electrical engineering and a Visiting Professor of
engineering with the University of California, Merced, CA, USA, prior
to his move in 2009 to Chungbuk National University, Cheongju-si,
Korea, as a Distinguished Professor, World Class University Program.
He has founded six high-technology companies, providing an intimate
link between university research and industry. He is currently the Presi-
dent/Chairman of iDataMap Corporation. He has co-authored six textbooks
and has lectured widely in very large scale integrated and multitechnology
systems.
Dr. Eshraghian is a fellow and life member of the Institution of Engineers,
Australia.