TEMPERATURE CYCLING RELIABILITY TEST

FOR A BALL GRID ARRAY (BGA) PACKAGE

USING FINITE ELEMENT ANALYSIS (FEA)
by
MUHAMMAD NUBLI BIN ZULKIFLI
(0630110107)
A thesis submitted
in fulfillment of the requirements for the degree of
Master of Science (Microelectronic Engineering)
School of Microelectronic Engineering
UNIVERSITI MALAYSIA PERLIS
2008

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ACKNOWLEDGEMENTS
This work would have been impossible without the help of many persons. I would like to
take this opportunity to thank those who have helped me to complete this work.
My Mother
For all the love, support, encouragement, guidance and prayers throughout the course of
my life.
Professor Dr. Zul Azhar Zahid Jamal
For being my first supervisor who taught me a lot about science of research and being a
good mentor by giving me a continuous guidance and help. Thank you for giving me such
huge opportunity by taking me as a student in UniMAP.
Associate Professor Dr. Ghulam Abdul Quadir
For being the guide by helping me a lot in the development of this work. His valuable
inputs, guidance and motivation have helped me during my study.
Lecturers and staff in Universiti Malaysia Perlis, UniMAP
Encik Mohd Khairuddin, Associate Professor. Ir. Mohabbatul Zaman, Puan Hasnizah and
others for their support and valuable criticism.
And those who have contributed directly and indirectly to this work.

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TABLE OF CONTENTS
ACKNOWLEDGEMENTS ii
TABLE OF CONTENTS iii
LIST OF TABLES vii
LIST OF FIGURES ix
LIST OF ABBREVIATIONS xi
LIST OF SYMBOLS xiii
ABSTRAK xvi
ABSTRACT xvii
CHAPTER 1 1
INTRODUCTION 1
1.1 Microelectronics Packaging Technology Trends 1
1.2 Problem Statement 3
1.3 Objectives 4
1.4 Thesis Outline 5
1.5 Publication 5
CHAPTER 2 6
LITERATURE REVIEW 6

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2.1 Reliability 6
2.1.1 Temperature Cycling 6
2.1.2 Failure Rate Function 8
2.1.3 Failure Density Function 12
2.1.4 Mean Time to Failure 13
2.2 Statistical Experimental Design 15
2.2.1 Regression Equation 18
2.2.2 Simple Linear Regression 19
2.2.3 Multiple Linear Regressions 22
2.2.4 Polynomial Regression 25
2.3 Screening Design 26
2.3.1 Full Factorial Design 26
2.3.2 Fractional Factorial Design 28
2.3.3 Central Composite Design 29
2.3.4 Box-Behnken Matrix Design 32
2.4 Solder Fatigue Model 35
2.4.1 Darveaux Energy Based Fatigue Model 37
2.5 Optimization 43
2.5.1 Probabilistic Design System 44
2.5.2 Goodness-of-Fit Measures 48
2.6 Chapter Summary 49

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CHAPTER 3 51
ANALYSIS 51
3.1 Finite Element Analysis (FEA) 51
3.1.1 Material Definition and Element Definition 52
3.1.2 Geometry Creation 56
3.1.3 Meshing 60
3.1.4 Load Definition and Solution 61
3.1.5 Postprocessing and Results 67
3.2 Ramp Rate and Dwell Time Analysis 70
3.3 Optimization Analysis 71
3.3.1 Response Surface Method Based on CCD 76
3.3.2 Response Surface Method Based on Box-Behnken Matrix Design 79
3.3.3 Monte Carlo Method 81
3.4 Chapter Summary 81
CHAPTER 4 83
RESULTS AND DISCUSSION 83
4.1 Deterministic Results 83
4.2 Effects of Varying Ramp Rate and Dwell Time 90
4.3 Optimization Results 92
4.3.1 Probabilistic Results 104

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4.4 Chapter Summary 121
CHAPTER 5 123
CONCLUSION 123
5.1 General Conclusion 123
5.2 Suggestion for Future Work 125
REFERENCES 127
APPENDICES 135
Appendix A Finite Element APDL Code 135
Appendix B Publication 163

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LIST OF TABLES
Table 2-1: Full Factorial Design Sets for 3 Design Variables 28
Table 2-2: Half Factorial Design Sets for 3 Design Variables 29
Table 2-3: CCD Design Sets 32
Table 2-4: Box-Behnken Matrix Design Sets 34
Table 2-5: Darveaux Model Constitutive Constants for SnPb Solder 41
Table 3-1: General Material Definition 53
Table 3-2: Detailed Material Definition for Each Component of BGA Package 53
Table 3-3: Modified Anands Constants Proposed by Darveaux for SnPb Solder 55
Table 3-4: Package Parameter 57
Table 3-5: JEDEC JESD22-A104 Temperature Cycle Test Conditions 63
Table 3-6: Darveauxs Crack Growth Correlation Constants 69
Table 3-7: Experiment Strategy 70
Table 3-8: Ranges of Design Variables 72
Table 3-9: Value for Each Design Variables with Respect to Their Level in CCD 77
Table 3-10: CCD Design Sets with Respect to Their Level 78
Table 3-11: Box-Behnken Matrix Design Sets with Respect to Their Level 80
Table 4-1: Design Variables Values Used for Deterministic Analysis 83
Table 4-2: Deterministic Analysis Results 88
Table 4-3: Ramp Rate and Dwell Time Analysis Results 90
Table 4-4: RSM Based on CCD Results 93
Table 4-5: RSM based on Box-Behnken Matrix Design Results 94

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Table 4-6: Comparison between Performance Parameters for RSM based on CCD and
RSM based on Box-Behnken Matrix Design Optimization Techniques 95
Table 4-7: Goodness-of-fit Measures for RSM based on CCD and RSM
based on Box-Behnken Matrix Design 109
Table 4-8: Probability Parameters Results for RSM based on CCD and
RSM based on Box-Behnken Matrix Design 121

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LIST OF FIGURES
Figure 1-1: Microelectronics Packaging Technology Trend 1
Figure 2-1: Temperature Cycle Profile 7
Figure 2-2: Bathtub Curve 10
Figure 2-3; Interaction of Factors, Process, and Responses 16
Figure 2-4: Stages in Statistical Experiment Design 17
Figure 2-5: Fitted Regression Line 22
Figure 2-6: Design Space for Full Factorial Design with 3 Design Variables 27
Figure 2-7: Design Space for Half-Factorial Design with 3 Design Variables 29
Figure 2-8: Design Space for Central Composite Design with 3 Design Variables 31
Figure 2-9: Design Space for Box-Behnken Matrix Design with 3 Design Variables 34
Figure 2-10: General Fatigue Modeling Steps 35
Figure 2-11: Darveauxs Methodology Procedure 37
Figure 2-12: Typical Constant Load Creep Behavior of Metal 38
Figure 3-1: ANSYS Finite Element Analysis Steps 51
Figure 3-2: VISCO107 and SOLID45 Element Geometry and Direction of
Degree of Freedom 56
Figure 3-3: Types of Symmetry 58
Figure 3-4: BGA Package Outline 59
Figure 3-5: Side View of Quarter Symmetry BGA Package Model 59
Figure 3-6: Darveauxs Model Meshing Consideration 60
Figure 3-7: Package Model Boundary Constraints 62
Figure 3-8: Thermal Cycles Loading 65

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Figure 3-9: Probabilistic Design Data Flow Chart Used in ANSYS 72
Figure 3-10: Statistical Distribution Graphs 74
Figure 3-11: Optimization Process Flow Chart using RSM based on CCD in
ANSYS 76
Figure 3-12: General Analysis Process Flow Chart 82
Figure 4-1: Critical Solder Joint Location 84
Figure 4-2: Stress Intensity Plot for Solder Joints 85
Figure 4-3: Stress Intensity Plot for BGA Package Model 86
Figure 4-4: Vector Sum Displacement Plot of BGA Package Model 87
Figure 4-5: Plastic Work History for Case 1 91
Figure 4-6: Solder Joint Contact Angle 97
Figure 4-7: Stress Intensity Distributions in BGA Package with Respect to the
Changes of Mold Compound Thickness 99
Figure 4-8: Location of Critical Solder Joint with Respect to the Changes of Mold
Compound Thickness 102
Figure 4-9: Response Surface Plots from Central Composite Design Sets 111
Figure 4-10: Response Surface Plots from Box-Behnken Matrix Design Sets 113
Figure 4-11: Sensitivity Plot for Design Variables 116
Figure 4-12: Distribution Function Histogram of SFAIL 119
Figure 4-13: Cumulative Distribution Function of SFAIL 120

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LIST OF ABBREVIATIONS
APDL ANSYS Parametric Design Language and Macros
BGA Ball Grid Array
CCD Central Composite Design
CTE Coefficient of Thermal Expansion
DFR Design for Reliability
DIE Die Thickness
DOE Design of Experiment
FEA Finite Element Analysis
GUI Graphical User Interface
HAST Highly Accelerated Temperature and Humidity Stress Test
JEDEC Joint Electron Device Engineering Council
MLD Mould Compound Thickness
MTTF Mean Time to Failure
PCB Printed Circuited Board
PDS Probabilistic Design System
RSM Response Surface Method
SFAIL Solder Joint Fatigue Life
SSE Sum of Squares of the Errors
SSR Regression Sum of Squares
SST Total Sum of Squares
STD Solder Joint Standoff Height

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TK PCB Core Thickness
YOU PCB Core-in-Plane Youngs Modulus

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LIST OF SYMBOLS
Failure Rate Function
The Mean of Exponential Distribution
Shape Factor
The Log Mean
The Scale Parameter
(x) The Gamma Function

The Total Shear Strain

e

The Elastic Shear Strain Component

p

The Plastic Strain Component

c

The Creep Strain Component

f
N The Mean Cycles to Failure
C The Fatigue Ductility Coefficient
pl
eq
d The Stabilized Incremental Equivalent Plastic Strain
pl
eq
The Summation of the Stabilized Incremental Equivalent Plastic Strain
m
T Melting Temperature
S
d
dt

The Steady State Strain Rate

k Boltzmanns Constant
T The Absolute Temperature

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The Applied Stress
a
Q The Apparent Activation Energy
n The Stress Exponent
The Stress Level at Which the Power Law Dependence Breaks Down
C
The Creep Strain
T
Transient Creep Strain
B The Transient Creep Coefficient
C
d
dt

Instantaneous Creep Rate

p
Time-Independent Plastic Strain
G Shear Modulus
in
Total Inelastic Strain Energy
p
Time Independent Plastic Strain
c
Time Dependent Creep Strain
ave
W The Average Viscoplastic Strain Energy Density Accumulated per Cycle
V The Volume of Each Element
0
N The Number of Cycles to Crack Initiation
da
dN
The Crack Growth Rate per Thermal Cycle
The Characteristic Solder Joint Fatigue Life
a The Total Distance the Crack Travels
0
S Initial Value of Deformation Resistance
Q/R Activation Energy / Boltzmanns Constant

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A Pre-Exponential Factor
Multiplier of Stress
m Strain Rate Sensitivity of Stress
0
h Hardening Constant
s^ Coefficient of Deformation Resistance Saturation Value
n Deformation Resistance Value
a Strain Rate Sensitivity of Hardening

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ABSTRAK
UJIAN KEBOLEHARAPAN SUHU BERKITAR BAGI PAKEJ BEBOLA
TATASUSUNAN GRID (BGA) MENGGUNAKAN ANALISA UNSUR
TERHINGGA (FEA)
Ujian suhu berkitar adalah salah satu daripada ujian kebolehharapan yang selalunya digunakan
untuk menilai kebolehharapan sambungan pateri di dalam pembungkusan mikroelektronik. Tujuan ujian suhu
berkitar adalah untuk mencirikan mekanisme kegagalan mekanik haba ke atas pembungkusan
mikroelektronik. Penyelidikan ini menggunakan keupayaan komputer untuk melakukan ujian suhu berkitar
melalui analisa unsur terhingga. Analisa unsur terhingga untuk ujian suhu berkitar dijalankan dengan
menggunakan perisian unsur terhingga ANSYS. Satu per empat model pakej bebola tatasusunan grid
(BGA) dibina secara berparameter menggunakan APDL (bahasa dan makro rekabentuk berparameter
ANSYS). Dua jenis analisa digunakan untuk menilai keupayaan keboleharapan sambungan pateri ke atas
pakej BGA, iaitu analisa secara fizik dan analisa secara statistik. Model lesu berdasarkan tenaga Darveaux
digunakan sebagai persamaan juzuk untuk pateri. Keadaan suhu berkitar G berdasarkan piawaian JEDEC
JESD22-A104 digunakan di dalam analisa unsur terhingga. Kesan perubahan suhu berkitar dikaji dengan
menggunakan beberapa nilai berbeza bagi masa inap dan masa tanjakan. Dua kaedah rekabentuk ujikaji
statistik iaitu rekabentuk komposit berpusat (CCD) dan rekabentuk matriks Box-Behnken digunakan untuk
memperolehi faktor terpenting daripada beberapa pembolehubah rekabentuk seperti ketinggian sambungan
pateri, ketebalan papan litar tercetak (PCB), modulus Young teras di dalam satah PCB, pekali pengembangan
haba (CTE) teras di dalam satah PCB, ketebalan die, dan ketebalan mold. Proses pengoptimuman
menggunakan kaedah permukaan sambutan (RSM) digunakan untuk mengesan pembolehubah atau faktor
yang mempunyai kesan langsung ke atas kegagalan pembungkusan mikroelektronik dan juga interaksi antara
faktor. Simulasi Monte Carlo digunakan untuk melakukan penilaian kewarakan ke atas keputusan yang
diperolehi melalui pengoptimuman berdasarkan rekabentuk komposit berpusat (CCD) dan rekabentuk
matriks Box-Behnken. Daripada pemerhatian didapati bahawa perubahan pada masa tanjakan menghasilkan
kesan langsung ke atas hayat lesu pateri berbanding daripada perubahan pada masa inap.
Walaubagaimanpun, masa inap pada suhu tinggi memberikan kesan yang boleh diabaikan ke atas hayat lesu
sambungan pateri. Ketebalan mold didapati mempunyai kesan langsung paling tinggi terhadap perubahan
keupayaan keboleharapan pateri (lebih daripada 50%) daripada faktor-faktor yang lain. Selain daripada kesan
individu bagi setiap faktor, interaksi antara faktor juga dapat mengubah keupayaan keboleharapan pateri.
RSM berdasarkan kepada rekabentuk matriks Box-Behnken menghasilkan hayat lesu ciri sambungan pateri
paling tinggi iaitu bersamaan dengan 2861 kitaran atau 44.1% peningkatan daripada nilai awal set
rekabentuk. RSM berdasarkan kepada rekabentuk CCD menghasilkan pengiraan kebagusan padanan yang
terbaik. Oleh itu RSM berdasarkan kepada CCD mempunyai ketepatan yang terbaik dalam mewakili titik
sampel terhadap permukaan sambutan.

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ABSTRACT
Thermal cycling test is one of the reliability test that has been used to evaluate the reliability of the
solder joint interconnect in ball grid array (BGA) package. The purpose of thermal cycling test is to
characterize thermomechanical failure mechanism on microelectronics package. This research utilizes the
computer capability to run the thermal cycling test by using finite element analysis (FEA). FEA of thermal
cycling test is done by using ANSYS finite element software. Quarter symmetry BGA package model is
built parametrically by using APDL (ANSYS Parametric Design Language and Macros). Two types of
analyses are used to evaluate the reliability performance of solder joints in BGA package, namely the physics
based analysis and the statistical based analysis. Darveauxs energy based fatigue model is used as the
constitutive equation for solder. One of the temperature cycling conditions namely, G based on JEDEC
JESD22-A104 standard is used throughout the finite element analysis. The effect of different temperature
cycling condition is studied by applying different value of dwell times and ramp rates. Two screening design
methods namely, Central Composite Design (CCD) and Box-Behnken Matrix Design method are used to
isolate the most important factors amongst six design variables such as solder joint standoff height, printed
circuited board (PCB) core thickness, PCB core-in-plane Youngs Modulus, PCB core-in-plane coefficient of
thermal expansion (CTE), die thickness and mold compound thickness. The optimization process is carried
out using response surface methodology (RSM) to predict appropriate variables or factors that have a
significant influence on BGA package failure and their interactions. Monte Carlo simulations are used to
validate the randomness of the results obtained through CCD and Box-Behnken matrix design based
optimization methods. It is observed that changes in ramp rate produce significant effect in solder joint
fatigue life rather than changes in dwell time, but the dwell time at high temperature (high dwell) has a
negligible contribution to solder joint fatigue life. It is also found that the thickness of the mold has a
significant effect on the performance of the solder joint reliability (more than 50 %) as compared to that
from other factors. Besides the effect of individual factor, the interaction among factors also changes the
solder joint reliability. RSM based on Box-Behnken Matrix design offers the highest characteristic solder
joint fatigue life with a value of 2861 cycles or 41.1% enhancement from the initial design set. RSM based on
CCD offers the best goodness-of-fit measures over RSM based on Box-Behnken Matrix design. These results
show that RSM based on CCD has better accuracy in representing the sample points on response surface.

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CHAPTER 1
INTRODUCTION
1.1 Microelectronics Packaging Technology Trends
Microelectronics packaging is one of the major fields in microelectronics
engineering. The functions of a microelectronics package are to protect, power, and cool
the microelectronic chips or components and provide electrical and mechanical connection
between microelectronics parts and outside world (Tummala, 2001). The technology and
business trend of microelectronics such as further miniaturization, high performance
electronic product, increasing level of technology and function integration, cost reduction
and also short time to market lead to increase chances of failures and design complexity of
microelectronics packaging (figure 1-1).
Figure 1-1: Microelectronics Packaging Technology Trend (Bolanos, 2006)

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Performing reliability tests is important before any microelectronics product goes
to the market. The tests are becoming more challenging as more complex processes and
products must be developed in shorter time scale. Furthermore, the next generation of
microelectronics packages is expected to perform with ten time higher reliability than
todays packages (Tummala, 2001). The packages should perform under various stress
environments, with temperature ranging from -60 C to 175 C for the automotive and
aerospace industries, and -50 C to 150 C for the telecommunication, consumer and
computer industries. Nowadays, product qualification requires many reliability tests such
as thermal shock, temperature cycling, highly accelerated temperature and humidity stress
test (HAST), to name a few. All of these tests require expensive equipment and long
testing time and this in turn will add to the total cost of the packages.
To reduce cost and process or product development time and to improve reliability
performance, integrated design for reliability (DFR) at the earlier stage of development has
become a vital practice. DFR process can be done by utilizing the capability of commercial
finite element software. By utilizing the computational capability of computer, DFR can
produce reliability test results faster than the actual reliability test. This will help in
reducing the time to market the product and also to make sure that reliable product is
produced before entering the market.
Thermal cycling test is one of the reliability tests that has been used to evaluate the
reliability of the solder joint interconnect in microelectronics package. Solder joint fatigue
crack failure caused by thermomechanical mechanism is one of the major failures in
microelectronics package. The purpose of thermal cycling test is to characterize
thermomechanical failure mechanism on microelectronics package. Finite element

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software is used to run the thermal cycling test virtually to evaluate the reliability of the
solder joint. Solder joint reliability using finite element analysis is evaluated on the basis of
physical analysis and statistical analysis. Physical analysis is used to analyze the effect of
several factors such as component geometry, material properties and loading conditions on
the performance of solder joint reliability. The statistical analysis is used to find the critical
factors and to see the interaction among the factors affecting the performance of solder
joint reliability.
1.2 Problem Statement
Solder joint fatigue crack failure is one of the major reliability issues in
microelectronics package. The evaluation of solder joint reliability by using thermal
cycling test requires a lot of time and very costly. To reduce cost and time consumption of
reliability test, finite element analysis (FEA) is usually used to run an actual reliability test
virtually. In this present analysis, commercial finite element software ANSYS is used to
run thermal cycling test on a BGA package to evaluate the reliability of solder joint. Solder
joint reliability using finite element analysis is evaluated on the basis of physical analysis
and statistical analysis which provide a more comprehensive and in-depth results compared
to the results obtained through an actual thermal cycling test.

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1.3 Objectives
The objectives of this research are:
To extend the work of Hossain et al. (2007) by adding two additional design
variables (mold compound thickness and die thickness) and using a different type
of screening design (Box-Behnken Matrix design).
To build a BGA package model for the finite element analysis using
ANSYS.
To understand the effects of several factors on solder joint reliability of
BGA package through physical analysis and statistical analysis.
To find the value of inelastic strain energy and characteristic solder joint
fatigue life.
To find the critical factors that affects the reliability performance of solder
joint.
To find the optimum value of solder joint fatigue life.
To develop a solder joint reliability predictive equation based on response
surface methodology.
To analyze the effect of different temperature cycling loading condition (ramp rate
and dwell time) on the characteristic solder joint fatigue life.

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1.4 Thesis Outline
Chapter 2 outlines a literature review about basics of reliability, statistical
experimental design, screening design, solder fatigue models, and optimization technique
approaches. Chapter 3 explains the analysis to develop BGA package model in ANSYS
finite element software and the procedure needed to run an optimization process in
ANSYS built-in feature known as Probabilistic Design System (PDS). Chapter 4
describes and discusses the results obtained from the analysis. Chapter 5 provides the
conclusions and suggestions for future work. Appendix A provides the APDL code used
for finite element analysis in ANSYS and Appendix B includes the publication that has
been published based on this present analysis.
1.5 Publication
Some of the results and discussions of this research presented in chapters 3 and 4 in
this thesis have been published in the following scientific literature (Appendix B):
Zulkifli, M. N., Jamal, Z., Quadir, G.A., and Hashim, U. (2008). Thermal Cycling
Analysis of SnAgCu and SnPb Solder Joints Reliability. Proceeding of Malaysian
Technical Universities Conference on Engineering and Technology (MUCET)
2008, 26-31.

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CHAPTER 2
LITERATURE REVIEW
2.1 Reliability
The reliability of a packaged microelectronics system is defined as the probability
that this system will be operational within acceptable limits for a given period of time
(Tummala, 2001). Usually, the effect of microelectronics package reliability issues are
often realized at the system level, but the actual failure mechanism occurs at the lowest
hardware level. Therefore, in order to run reliability analysis on microelectronics packages,
it will require a thorough understanding about failure modes and failure mechanisms
relevant to microelectronics packaging.
The reliability of semiconductor packaging is always related on interconnection
issues such as the reliability of solder joints. This is because most of the failure modes such
as fatigue, creep, crack and voids often occur at the solder joints area (Li et al., 2007). In
electronic assemblies, fatigue of solder joints is believed to play a major role in about 90 %
of all structural and electrical failures (Tummala, 2001).
2.1.1 Temperature Cycling
To asses the reliability of microelectronic package, several reliability tests or
accelerated tests are usually used in the industry. One of the reliability tests that has been
used is thermal cycling test. Thermal cycling test is used to characterize thermomechanical

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reliability issues in microelectronics package in order to determine the ability of
components and solder interconnects to withstand mechanical stresses induced by
alternating high and low extremes (JEDEC, 2000). The repeated temperature cycling
produces stress that eventually causes solder joint fatigue crack failure because of the
thermomechanically-induced strains and stresses generated at the solder joints. Figure 2-1
shows temperature cycle profile that is usually used in a thermal cycling test (JEDEC,
2000).
Figure 2-1: Temperature Cycle Profile
There are two types of thermal cycling tests that have been used in industry;
thermal cycling and thermal shock tests. The major difference between these two tests is
the physical chamber used for testing. Thermal shock test is conducted in two separate
liquid thermal baths or two separate air chambers in which the tested components are

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