SWINBURNE UNIVERSITY OF TECHNOLOGY

(Sarawak Campus)

School of Engineering

HET 202

DIGITAL ELECTRONIC DESIGN

FINAL EXAMINATION

December 2006

Time allowed: 3 hours

Reading time: 10 minutes

60% of Total Subject mark

STUDENT ID NO:________________________________________________________

Question
Possible Mark
Actual Mark
1 5

2 8

3 9

4 4

5 5

6 9

7 4

8 7

9 10

10 8

11 8

12 11

13 5

14 7

Total
100


2








INSTRUCTIONS TO CANDIDATES

1. This exam is worth 60% of the total assessment for the subject.
2. This Paper contains 21 pages including formula sheet and VHDL syntax.
3. This paper contains 14 questions worth a total of 100 marks.
4. Formula sheets and VHDL syntax are given at the back of the question paper.
5. Answer all questions in the located blank space. Students are encouraged to answer separate
pages if it is necessary.
6. Show relevant steps to your answers for maximum marks.
7. Your Exam Question Paper must be handed in to the invigilators.

Exam Duration Three (3) hours

Reading Time Ten (10) minutes

Aids Allowed: Any Programmable Calculator is not allowed.






















3
Answer all in the following questions

[5+8+9+4+5+9+4+7+10+8+8+11+5+7=100]

1. Simplify the following expression using Boolean algebra.
(A+C+F+G)(A+C+F+G)(A+B+C+D+G)(A+C+E+G)(A+B+G)(B+C+F+G)




























[5]
4
2. (a) By the use of a K-map, explain why F(a,b,c) =ab+ac has a static1 hazard and identify an
input transition for which the hazard may occur.
(b) Draw a timing diagram that illustrates this hazard. Assume suitable propagation delays to exhibit the
problem.










































[4+4=8]
5
Q
R
S
P
3. Design a debouncing circuit and show its switching timing diagram using the following S-R Latch.















































[4+5=9]
6
4. Draw the timing diagram for the following gated latch.






















5. Show how four 2-to-1 and one 4-to-1 multiplexers could be connected to form an 8-to-1 MUX with
three control inputs.





















D
G
Q
Q
S
R Q
Q
D
G
S
R Q
Q
D
G
[4]
[5]
7
6. Draw the equivalent circuit for the following VHDL code.













































[4+5=9]
a) k <= '0' when a = '1' and b = '1' else
1 when b=0 else
'0' when a = '0' else
not c;
b) Process (Clk)
begin
if Clkevent and Clk =1 then
Q1 <= Q3;
Q2 <= Q1;
Q3 <= Q2;
End if;
End process;
a)
b)
8
A
Aen
B
Ben
T
7. Complete the timing diagram for the following concurrent VHDL statements:

signal A,B,T,Aen,Ben : std_logic;
---------------------------------
T <= A when Aen = '1' else 'Z';
T <= B when Ben = '1' else 'Z';




















8. Write a VHDL module that implements an 8-input priority encoder.



















[4]
[7]
9























9. Design a circuit for 3-bit sequence generator using T flip-flops which counts in the following sequence:
001, 011, 010, 110, 111, 101, 100, (repeat) 001,





















[10]
10













































11
10. Design a state machine graph for a synchronous 3 bit counter which has a control mode M. When
M =0, the counter counts up in the binary sequence. When M =1, the counter advances through the
Gray code sequence.

Binary: 000, 001, 010, 011, 100, 101, 110, 111
Gray: 000, 001, 011, 010, 110, 111, 101, 100








































[8]
12
11. Convert the following state graph to the State Machine (SM) chart.













































[8]
S0 S1 S2
0/0
0/1 0/0
S3
0/0
1/1 1/0
1/1
1/1
13
12. (a) Design a state diagram for sequence detector to detect occurrences 010 & 100.
(b) Write a VHDL module for the sequence detector of Q12 (a).












































[5+6=11]
14
























13. Write a Testbench VHDL module to verify the sequence detector of question 12 (b).





















[5]
15























14. Reduce the following state table to a minimum number of states.

Present State Next State Present Output
X=0 X=1 X=0 X=1
A E G 1 0
B B H 0 0
C H E 1 1
D G H 0 0
E E B 1 0
F H A 1 1
G D H 0 0
H G F 1 0












16













































17
Boolean Theorems and Laws

Operations with 0 and 1
X +0 =X X 1 =X
X +1 =1 X 0 =0

Idempotent law
X +X =X X X =X

Involution law
(X) =X

Complementation law
X +X =1 X X =0

Commutative Laws
X +Y =Y +X X Y =Y X

Associative Laws
(X +Y) +Z =X +(Y +Z) =X +Y +Z
(X Y) Z =X (Y Z) =X Y Z

Distributive Laws
X (Y +Z) =XY +XZ
X +(Y Z) =(X +Y) (X +Z)

Simplification Theorems
XY +XY=X (X+Y)(X+Y) =X
X +XY =X X(X+Y) =X
(X+Y)Y =XY XY +Y =X +Y

DeMorgans Theorem
(X +Y) =X Y (XY) =X +Y
(X +Y) =(X Y) (XY) =(X +Y)

Useful derived-relations
(X+Y)(X+Z) =XZ +XY

Consensus Theorem
XY +XZ +YZ =XY +XZ
(X+Y)(X+Z)(Y+Z) =(X+Y)(X+Z)





18
VHDL Syntax
Entities
entity EXAMPLE is
generic (list-of-generics-and-their-type);
port ( A, B, : in std_ulogic ; CARRY: out bit ) ;
end example;
Architecture DECAM of EXAMPLE is
signal FRMERR, PERM : bit_vector (9 downto 0);
signal xaas : Bit :=0 ;
component decoder
generic (PT_HL, PT_LH, : time) ;
port ( x, y, z : in BIT, Z : out bit_vector (0 to 7) ;
end component ;

begin
v0: decoder port map ( a,b,c,d) ;
v1: decoder generic map (5 ns, 10 ns ) port map ( a,x,w,y) ;

SUM <= A and B after 10 ns ;

process ( a,b,c,d,e,...,m)
variable x34_add
begin
Sequential Statements
end process;
end DECAM;
Packages
package PACKS is
type SUMMER is (J UN , J ULY, AUG , SEP ) ;
component D_FLIPFLOP
port (D, CK:in BIT ; Q , QBAR : out BIT) ;
end component ;
constant PIN2PIN : time :=125 ns ;
function INT2BIT_VEC(INT_VALUE : INTEGER)
return BIT_VECTOR ;
end PACKS;

package body ANOTHERV_PACKAGE is
package-body-item-declarations -->these are
--subprogram bodies
--complete constant declarations
--subprogram declarations
--type and subtype declarations
--file and alias declarations
--use clauses
end package body ANOTHERV_PACKAGE;

Sequential Statements

wait on sensitivity-list;
wait until boolean-expression ;
wait for time-expression ;
wait on sensitivity-list until boolean-expression for tine-expression;
IF Statement
if boolean-expression then
19
sequential-statements
end if ;

if CONDITION then
sequential statements
elsif condition then
sequential statements
elsif condition then
sequenial statements
else
sequential statements
end if ;


if CONDITION then
sequential statements
else
sequential statements
end if ;

Case Statement

case EXPRESSION is
when value _1 =>
-- sequential statements
when value_2 | value_4 =>
-- sequential statements
when value_m to value_n =>
-- sequential statements
end case;

LOOP STATEMENT

for I in range loop
--sequential statements
end loop

while boolean_expression loop
--sequential statements
end loop;

null ;
exit [ loop_label] when condition];

next[loop_label] [ when condition]

ASSERTION STATEMENT
assert boolean-expression
report string-expression
severity expression


Concurrent Statements
Block Statement

block_label : block ( guard-expression) is
20
block -header
block-declaration
begin
concurrent-statements
-- Z <=guarded not A;
end block block_label ;

GENERATE STATEMENT

generate-label: for generate-identifier in discrete-range generate

--concurrent statements
end generate generate-label;

COMPONENT DECLARATION

component decoder
generic (PT_HL, PT_LH, : time) ;
port ( x, y, z : in BIT, Z : out bit_vector (0 to 7) ;
v1: decoder generic map (5 ns, 10 ns ) port map ( a,x,w,y) ;

CONDITIONAL SIGNAL ASSIGNMENT STATEMENT

target-signal <= waveform1 when condition1 else
waveform2 when condition2 else
...
waveform when conditionz ;


with expression select
target-signal <= waveform when choices ,
waveform when choices ,
...
waveform when choices ;


Configuration

Configuration Specification

for list-of comp-labels : component -name binding-indication;
use entity entity-name(architecture-name)
generic map (generic-association-list)
port map (port-association-list) ;


Configuration declaration

configuration configuration-name of entity-name is
block-configuration
end configuration configuration-name;

Examples:
library CMOS;
configuration FA_CON of FULL_ADDER is
for FA_STR
21
use work.all
for A1, A2, A3 : AND2
use entity CMOS.BIGAND2(AND2STR);
end for ;
for others : OR2
end for ;
for all : XOR2
use configuration WORK.XOR2CON;
end for;
end for;
end FA_CON ;

SUBPROGRAMS
Functions:

function TO_CHARCT(ARG: STD_ULOGIC) return CHARCT is

begin
-- sequential statements

end TO_CHARCT ;

procedure ARITH_UNIT( parameter -list)


Library Clauses
library CMOS;
use CMOS.Synth_pack.all




Signals and Related Attributes:

SEVENT: returns true if an event occurred on signal S in the current delta
SACTIVE : returns true if signal S is active in current delta.
SLAST_EVENT : returns the time lapsed since the last event on signal S.
SLAST_ACTIVE: return the time lapsed since the last time the signal was active.
SDELAYED(T) is a new signal that is the same type as S but delayed from S by time T.
SSTABLE(T) is a Boolean signal that is true when signal S has not had any event for time T.
SQUIET(T) creates a signal of type BIT that toggles its values every time signal S becomes active.

Logical And Shift Operators
AND, NAAD, OR, NOR, XOR,XNOR
SLL,SRL,ALA,ROL,ROR