1

Low Power System Design

Low Power System Design
Module 2 (3 hours):
Source of Power Consumption
Jan. 2007
Naehyuck Chang
EECS/CSE
Seoul National University
2
Source of Power
Consumption (1)
Source of Power
Consumption (1)
Naehyuck Chang
EECS/CSE
Seoul National University
naehyuck@snu.ac.kr
3
Contents
Contents
Overview
Dynamic power
Transition probability
Signal probability
Decreasing the switching activities
4
Power and Energy
Power and Energy
Power consumption of digital circuits is defined by the
supply voltage times the current flow from VDD to GND
Generally, VDD is constant and IDD is variable
Instantaneous power:
Energy:
Average power:
5
Source of Power Consumption
Source of Power Consumption
Dynamic power
Current flow from VDD to GND when logic transition occurs
Static power
Current flow from VDD to GND regardless of logic
transition
6
Source of Power Consumption
Source of Power Consumption
Dynamic power
Switching power
Short-circuit power
Glitch power
Static power
DC current
Leakage current
Weak inversion current
Drain-induced barrier lowering
Gate-induced drain leakage
Channel punch-through
Oxide leakage tunneling
Hot carrier injection
7
Source of Power Consumption
Source of Power Consumption
Traditional CMOS circuits
Slow operation
Negligible dynamic power consumption
Electric watches, calculators, etc.
High VDD and Vt
Negligible leakage power consumption
Small short-circuit current
Modern high-speed CMOS
Fast operation
Low VDD and Vt
Power is the most important design constraints
8
Pull-up and pull-down network
Pull-up and pull-down network
NMOS pull-up transistor
PMOS pull-down
transistor
9
Dynamic Power
Dynamic Power
Switching power
A step voltage is applied at t=0
Energy transferred from the power supply
10
Dynamic Power
Dynamic Power
When
is dissipated by heat
is stored in the capacitor
The remaining is dissipated by heat again
when high-to-low transition occurs
High-to-low transition does not
draw additional current from the
power supply
11
Dynamic Power
Dynamic Power
Switching power:
12
Dynamic Power
Dynamic Power
Gate capacitance
: sum of the gate-to-bulk capacitances
Overlap capacitance
Due to Miller effect:

Diffusion capacitance
Interconnect capacitance
13
Dynamic Power
Dynamic Power
Activity Factor:
System clock frequency = f
Let f
sw
= f, where = activity factor
If the signal is a clock, = 1
If the signal switches once per cycle, =
Dynamic gates: switch either 0 or 2 times per cycle, =
Static gates: depending on design, but typically = 0.1
Switching power:
14
Dynamic Power
Dynamic Power
Reduced swing
Rail-to-rail swing: VDD to GND
When VOH < VDD, swing is VOH to GND
Reduced bit-line in memory
15
Dynamic Power
Dynamic Power
Short-circuit power
Transient current from VDD to GND when logic transition
occurs
16
Dynamic Power
Dynamic Power
Short-circuit power
17
Dynamic Power
Dynamic Power
Glitch power
Power dissipated in
intermediate transitions
during the evaluation of
the logic function
Unbalanced delay paths
are principle cause
Usually 8% -25% of
dynamic power
18
Transition Probability
Transition Probability
Dynamic power is data dependent
Activity factor is dependent on the run-time data
Switching activity, P
0 1
, has two components
A static component: function of the logic topology
A dynamic component: function of the timing behavior
(glitch)
Static transition probability
P
0 1
= P
out=0
P
out=1
= P
0
(1-P
0
)
With input signal probabilities
P
A=1
=1/2 and P
B=1
=1/2
NOR static transition probability
= 3/4 * 1/4 = 3/16
2-input NOR Gate
19
Transition Probability
Transition Probability
Switching activity is a strong function of the input signal
statistics
Generalized switching activity of a 2 input NOR gate
P
0 1
= P
0
P
1
= (1-(1-P
A
)(1-P
B
)) (1-P
A
)(1-P
B
)
Transition probability for basic gates
Transition probability for 2 input NOR gates
20
Transition Probability
Transition Probability
Transition probability propagation
C: P
0 1
= P
0
P
1
= (1-P
A
) P
A
=1/2 *1/2 = 1/4
D: P
0 1
= P
0
P
1
= (1-P
C
P
B
) P
C
P
B
= (1 (1/2 * 1/2)) x (1/2 * 1/2) = 3/16
21
Signal Probability (Advanced)
Signal Probability (Advanced)
Switching activity in combinational logic
Boolean difference:
Switching activity in sequential logic
Estimation of glitching power
22
Decreasing the Switching Activities
Decreasing the Switching Activities
No or little performance and/or functional degradation
Different coding techniques
Fewer bit transitions between two states
Boolean expressions simplification
Gate minimization
Avoid glitches
Get rid off unnecessary transitions
Power down modes
Turn off parts of that are not in use
23
Decreasing the Switching Activities
Decreasing the Switching Activities
Gray coding
Hamming distance of one
Used when a sequence is
predictable
FSMs
Address busses
Makes full use of the bit-
width
000 100
101
111
110
001
011
010
24
Source of Power
Consumption (2)
Source of Power
Consumption (2)
Naehyuck Chang
EECS/CSE
Seoul National University
naehyuck@snu.ac.kr
25
Contents
Contents
Static power
Leakage power introduction
Short-channel effect
Leakage power components
(VDD-V
t
) design space
Total power management
26
Static Power
Static Power
DC current
Pseudo NMOS logic
27
Static Power
Static Power
DC current
Steady current flow from VDD to GND
Either logic value is 0 or 1 depending on the logic structure
Mostly when the output is 0
28
Static Power
Static Power
Leakage current
A transistor switch is a resistive-capacitive network
between the power supply and GND
Non-ideal off-state characteristics (a finite resistance)
makes current draw even when the transistor is in the cut-
off state
29
Leakage Power Introduction
Leakage Power Introduction
Long channel (L>1um): negligible leakage
Short channel (L>180nm, Tox>30): subthreshold leakage
Very short channel (L>90nm, Tox>20): subthreshold+gate leakage
Nano scaled (L<90nm, Tox<20): subthreshold+gate+BTBT leakage
(DIBL)
(Gate leakage)
(BTBT)
30
Leakage Power Introduction
Leakage Power Introduction
Scaling makes the leakage power worse
Transistor scaling road map
Year 1999 2002 2005 2008 2011 2014
Feature size (nm) 180 130 100 70 50 35
Logic trans/Chip (M) 15 60 235 925 3,650 14,400
Power supply V
dd
(V) 1.8 1.5 1.2 0.9 0.7 0.6
Threshold V
T
(V) 0.5 0.4 0.4 0.35 0.3 0.25
31
Leakage Power Introduction
Leakage Power Introduction
Drain leakage increases as V
t
decreases to meet
frequency demands leading to excessive leakage power
8KW
1.7KW
400W
88W
12W
0%
10%
20%
30%
40%
50%
2000 2002 2004 2006 2008
D
r
a
i
n

L
e
a
k
a
g
e

P
o
w
e
r
10
100
1,000
10,000
100,000
30 40 50 60 70 80 90 100
Temp (C)
I
o
f
f
(
n
A
/
n
m
)
180nm
130nm
100nm
70nm
50nm
Source: Intel
32
Short-Channel Effect
Short-Channel Effect
Long-channel MOSFET
Source and drain-to-body PN junction region is relatively smaller
than the entire channel region
The extensions of the source and drain depletion regions into the
channel area have a negligible effect on V
t
Short-channel MOSFET
Depletion regions around the source and drain terminals become
closer
Depth of the source and drain depletion regions becomes
comparable to the effective channel length
More charge is contributed to the depletion region beneath the
gate area by source-to-substrate and drain-to-substrate
depletion layers
33
Short-Channel Effect
Short-Channel Effect
V
t
roll-off
V
t
is reduced with
decreasing L
Increasing dependence of V
t
on L threaten the future
technology scaling due to
variations
WID
D2D
34
Short-Channel Effect
Short-Channel Effect
Novel device techniques
Overcome the drawback of
the short-channel MOSFET
Super-halo doping
Multiple gate device
Planar devices Lmin = 10nm
Silicon-on-insulator (SOI)
device
35
Leakage Power Components
Leakage Power Components
Reverse bias PN junction leakage
Minority carrier diffusion/drift near the edge of the
depletion region
Election-hole pair generation in the depletion region of the
reverse bias junction
36
Leakage Power Components
Leakage Power Components
Subthreshold leakage current
Weak inversion current
The most significant leakage in DSM technologies
A MOSFET operates in the weak inversion (subthreshold)
region when V
GS
< V
t
Source to drain current conduction is primarily due to
diffusion of the carriers
Ioff is when V
GS
= 0, is affected by the V
t
, W, L, depletion
width beneath the channel area, channel/surface doping
profiles, drain/source junction depths, gate oxide thickness,
VDD, and junction temperature
37
Leakage Power Components
Leakage Power Components
Subthreshold leakage current
Thermal voltage:
Boltzmann constant:
Unit charge:
Subthreshold swing coefficient:
Permittivity
Permittivity
Thickness of the gate oxide
Thickness of the depletion layer
38
Leakage Power Components
Leakage Power Components
Subtherehod leakage current
Assuming the body effect is approximately linear for low
source-to-body voltages
Subthreshold leakage is exponentially dependent on the
junction temperature, V
GS
, V
DS
, and V
t
Simplified BSIM (Berkeley short-channel insulated gate FET model)
Body effect coefficient DIBL coefficient
39
Leakage Power Components
Leakage Power Components
Subthreshold leakage current
Frequently used equations
40
Leakage Power Components
Leakage Power Components
Subthreshold leakage current
Subthreshold leakage decreases exponentially as S decreases
Lowering the gate oxide thickness and/or doping concentration of the
substrate due to increasing thickness of the depletion layer of the substrate
Lowing the junction temperature
A subthreshold slope of 60 mV/decade is a lower theoretical limit
at room temperature for bulk silicon MOSFET with fully depleted
SOI devices
Typical values are ranging from 80 mV/decade to 100
mV/decade
41
Leakage Power Components
Leakage Power Components
Drain-induced barrier lowering (DIBL)
The depth of the junction depletion layer increases as the
reverse bias voltage across the drain-to-body PN junction
increases
Increased drain-to-body reverse bias voltage enhances the
short-channel effects and lowers V
t
A significant portion of the subthreshold leakage current of
a DSM MOSFET can be due to DIBL at high reverse bias
voltage across the drain-to-body PN junction
42
Leakage Power Components
Leakage Power Components
Oxide leakage tunneling
When the gate of an NMOS (PMOS) device is positively (negatively) biased,
the electrons (holes) in the inverted channel can tunnel to the poly gate
43
Leakage Power Components
Leakage Power Components
Two gate tunneling mechanisms
Fowler-Nordheimtunneling
Through the oxide layer conduction band
Observed at unusually high oxide voltage due to the electrons
tunneling into the conduction band of the gate insulator
Are not typically encountered during the normal operation of a CMOS
circuit
44
Leakage Power Components
Leakage Power Components
Two gate tunneling mechanisms
Direct tunneling
Through the forbidden energy gap of the gate insulator
Under normal bias conditions
With very thin oxide layer
The electrons or holes in the inverted silicon surface tunnel directly
through the forbidden energy gap of the ultra-thin gate insulator
Typically observed for t
ox
less than about 4nm
45
Leakage Power Components
Leakage Power Components
Two gate tunneling mechanisms
Direct tunneling
Dependent on the voltage across the gate dielectric, the thickness of
the dielectric, the tunneling barrier height, the effective mass of the
carriers, and the number of free carriers available for tunneling on
the MOS electrodes
Primary sources of the gate dielectric direct tunneling
Electron tunneling from the conduction band (ECB)
Electron tunneling from the valence band (EVB)
Hole tunneling from the valence band (HVB)
46
Leakage Power Components
Leakage Power Components
Direct tunneling of an NMOS transistor
47
Leakage Power Components
Leakage Power Components
Components of gate dielectric
tunneling
I
gs0
and I
gd0
are the leakage
current through the gate-
to-source and gate-to-drain
overlap region
Igc is the gate-to-channel
tunneling current during
operation in the inversion
region
48
Leakage Power Components
Leakage Power Components
Components of gate dielectric
tunneling
Gate to source/drain
overlap region (I
gs0
, I
gd0
)
Controlled by V
GD
and V
GS
Gate to channel (I
gc
)=to
source (I
gcs
) + to drain
(I
gcd
)
Controlled by V
ox
V
GS
-V
FB
(flat-
band voltage) -
s
V
poly
(voltage across the polysilicon
depletion region)
Gate to body (I
gb
)
Controlled by V
GB
49
Leakage Power Components
Leakage Power Components
Components of gate dielectric tunneling
Transistor off (Vg=0)
I
gd0
and I
gs0
dominates
Transistor on (Vg=1)
I
gc
(I
gcs
& I
gcd
) dominates
I
gb
small compared to others
50
Leakage Power Components
Leakage Power Components
Maximum gate oxide leakage
A transistor operates in the active region with the maximum
voltage difference across the gate-to-source and the gate-to-
drain terminals
Maximum subthreshod leakage: cut-off transistor
51
Leakage Power Components
Leakage Power Components
Semi-empirical gate oxide tunneling model
Assuming
Direct current density (A/cm
2
)
52
Leakage Power Components
Leakage Power Components
Semi-empirical gate oxide tunneling model

3.1 eV for electrons tunneling from the conduction band

4.2 eV for electrons tunneling from the valence band
4.5 eV for holes tunneling from the balance band
53
Leakage Power Components
Leakage Power Components
Hot carrier injection
Short-channel transistors are more susceptible to the
injection of hot carriers (holes and electrons) into the oxide
Theses charges are a reliability risk and are measurable as
gate and substrate currents
Can occur in the off-state, but more typically occurs during
the transistor bias states in transition
54
Leakage Power Components
Leakage Power Components
J unction band-to-band tunneling (BTBT)
V
D
=VDD
Equilibrium
55
Leakage Power Components
Leakage Power Components
J unction band-to-band tunneling (BTBT)
Tunneling probability should involve the barrier height (E
G
)
and the barrier width (depletion layer)
High BTBT
Strong Halo, small depletion region and large electric field
56
Leakage Power Components
Leakage Power Components
BT increases exponentially with the increase in
drain/source-to-substrate bias
57
Leakage Power Components
Leakage Power Components
Gate-induced drain leakage (GIDL)
In the high electric field under the gate/drain overlap
region
Carriers are generated from
Direct band-to-band tunneling
Trap-assisted tunneling
Thermal emission and tunneling
Thinner Tox and higher VDD cause a higher potential
between the gate and drain that enhances the electric field
dependent GIDL
58
Leakage Power Components
Leakage Power Components
Channel punch-through
When the drain and source depletion regions approach
each other and electrically touch deep in the channel
A space-charge condition that allows the channel current to
exist deep in the sub-gate region
Causing the gate to lose control of the sub-gate channel
region
59
Leakage Power Components
Leakage Power Components
Summary of leakage power components
(DIBL)
On-state leakage
Off-state leakage
60
(VDD-V
t
) Design Space
(VDD-V
t
) Design Space
Two key transistor scaling schemes
CE (Constant electric field) scaling
All the horizontal and vertical dimensions are scaled with the power
supply to maintain constant electric fields throughout the device
Standard scaling methodology in industry in a 30% reduction
(1/S=0.7) of all dimensions per generation
Supply and threshold voltages are scaled down by the factor of 1/S
Current, gate capacitances, and delay also scaled by 1/S
Results in 50% improvement in frequency
Improvement gradually degrades due to interconnect dominant delay
CV (Constant voltage) scaling
Maintains a constant power supply
Gradually scales the gate oxide thickness to slow down the growth of
fields in the oxide
61
(VDD-V
t
) Design Space
(VDD-V
t
) Design Space
CE scaling
Switching energy scaled down by 1/S
3
Dynamic power scaled down by 1/S
2
Operating frequency scaled up by S
Dynamic power for a constant die size is the same
Number of switching elements scaled up by S
2
Leakage power increases exponentially
Total effective width of a device scaled up by S
Example
Leakage power is 0.1% in 25um technology
Leakage power is 25% in 0.1um technology
62
(VDD-V
t
) Design Space
(VDD-V
t
) Design Space
(VDD-V
t
) Design Space
Delay of a gate
Subthreshold leakage current increases exponentially as V
t
decreases
For a given process and VDD/Vt ratio, the energy efficient V
t
point is significantly below the typical threshold levels of todays
technology
Excessive headroom for (VDD-V
t
) scaling
But lowering V
t
results in bad noise margin, short-channel effect, and V
t
variation
Short-channel effect
63
Total Power Management
Total Power Management
Power minimization in both active and standby modes
Dynamic power in active mode
Subthreshold leakage power in standby mode