3.fiscal Access System Using Rfid Document

FISCAL ACCESS SYSTEM USING RFID
1
INDEX
CONTENTS
1. Abbreviations
2. Fi!res "o#ations
$. Intro%!#tion
&. '"o#( Diara)
*. '"o#( Diara) Des#ri+tion
,. S#-e)ati#
.. S#-e)ati# Des#ri+tion
/. 0ar%1are Co)+onents
2o1er s!++"3
Mi#ro#ontro""er
RFID Rea%er
LCD
4e3+a%
EE2ROM
'!55er
6. Cir#!it Des#ri+tion
17.So8t1are #o)+onents
a. Abo!t 4ie"
b. E)be%%e% 9C:
11. 4EIL +ro#e%!re %es#ri+tion
12.Con#"!sion ;or< S3no+sis
1$. F!t!re As+e#ts
1&. 'ib"iora+-3
2
Abbreviations
S3)bo" Na)e
ACC A##!)!"ator
' ' reister
2S= 2rora) stat!s 1or%
S2 Sta#( +ointer
D2TR Data +ointer 2 b3tes
D2L Lo1 b3te
D20 0i- b3te
27 2ort7
21 2ort1
22 2ort2
2$ 2ort$
I2 Interr!+t +riorit3 #ontro"
IE Interr!+t enab"e #ontro"
TMOD Ti)er>#o!nter )o%e #ontro"
TCON Ti)er>#o!nter #ontro"
T2CON Ti)er>#o!nter 2 #ontro"
T2MOD Ti)er>#o!nter )o%e2 #ontro"
T07 Ti)er>#o!nter 7-i- b3te
TL7 Ti)er>#o!nter 7 "o1 b3te
T01 Ti)er>#o!nter 1 -i- b3te
T02 Ti)er>#o!nter 2 -i- b3te
SCON Seria" #ontro"
S'UF Seria" %ata b!88er
MAX MAXIM ;IC )an!8a#t!rer <
TTL Transistor to Transistor Loi#
ATM A!to)ati# Te""er Ma#-ine
RS 2$2 Re#o))en%e% Stan%ar%
AC A"ternatin C!rrent
DC Dire#t C!rrent
LCD Li?!i% Cr3sta" Dis+"a3
2C 2ersona" Co)+!ter
R2S Re!"ate% 2o1er S!++"3
RMS Root Mean S?!are
EE2ROM E"e#tri#a""3 Erasab"e 2rora))ab"e ROM
ROM Rea% On"3 Me)or3
RAM Ran%o) A##ess Me)or3
'IOS 'asi# In+!t O!t+!t S3ste)
3
SRAM Stati# RAM
E2ROM Erasab"e 2rora))ab"e ROM
DRAM D3na)i# Ran%o) A##ess Me)or3
ISR Interr!+t Servi#e Ro!tine
ICC Interate% Cir#!it C-i+
CAD Car% A##e+tan#e Devi#e
IFD Inter8a#e Devi#e
IDE Interate% Deve"o+)ent Environ)ent
Fi!re Lo#ations
S.No. Fi!re 2ae No.
1
Components of Typical Linear Power
Supply
2 An Electrical Transformer
3 Bridge Rectifier
4 Bridge Rectifier Positie Cycle
5 Bridge Rectifier !egatie Cycle
6 T"ree terminal oltage Regulator
7 #unctional $iagram of %icrocontroller
8 Pin $iagram of %icrocontroller
9 &scillator connections
10 E'ternal cloc( drie connections
11 A register
12 B register
13 RA%
14 RA% Allocation
15 Register Ban(s
16 PS)
17 $PTR
18 SP
19 P&RT *
20 TL* and T+*
,
21 $B-
22 Connecting %icrocontroller to PC
23
24
25
26 LC$
27
28
29
30
31
32
33 Linear .eypad
34 Pro/ect
35 !ew Pro/ect
36 Select Target deice
37 Select deice for Target
38 Copy 0*11 startup code
39 Source group 1
40 !ew file
41 &pened new file
42 #ile Sae
43 Add files to t"e source group
44 Adding files to t"e source group
45 Compilation
46 After Compilation
47 Build
48 Selecting t"e Ports to 2e isuali3ed
49 Start $e2ugging
1
INTRODUCTION
EM'EDDED SYSTEM@
An e)be%%e% s3ste) is a special4purpose system in w"ic" t"e computer is completely
encapsulated 2y or dedicated to t"e deice or system it controls5 6nli(e a general4purpose
computer7 suc" as a personal computer7 an em2edded system performs one or a few predefined
tas(s7 usually wit" ery specific re8uirements5 Since t"e system is dedicated to specific tas(s7
design engineers can optimi3e it7 reducing t"e si3e and cost of t"e product5 Em2edded systems
are often mass4produced7 2enefiting from economies of scale5
Personal digital assistants 9P$As: or "and"eld computers are generally considered
em2edded deices 2ecause of t"e nature of t"eir "ardware design7 een t"oug" t"ey are more
e'panda2le in software terms5 T"is line of definition continues to 2lur as deices e'pand5 )it"
t"e introduction of t"e &;& %odel 2 wit" t"e )indows <P operating system and ports suc" as a
=
6SB port > 2ot" features usually 2elong to ?general purpose computers?7 > t"e line of
nomenclature 2lurs een more5
P"ysically7 em2edded systems ranges from porta2le deices suc" as digital watc"es and
%P3 players7 to large stationary installations li(e traffic lig"ts7 factory controllers7 or t"e systems
controlling nuclear power plants5
@n terms of comple'ity em2edded systems can range from ery simple wit" a single
microcontroller c"ip7 to ery comple' wit" multiple units7 perip"erals and networ(s mounted
inside a large c"assis or enclosure5
EAa)+"es o8 E)be%%e% S3ste)s@
Aionics7 suc" as inertial guidance systems7 flig"t control "ardwareAsoftware and ot"er
integrated systems in aircraft and missiles
Cellular telep"ones and telep"one switc"es
Engine controllers and antiloc( 2ra(e controllers for automo2iles
+ome automation products7 suc" as t"ermostats7 air conditioners7 sprin(lers7 and security
monitoring systems
+and"eld calculators
+and"eld computers
+ouse"old appliances7 including microwae oens7 was"ing mac"ines7 teleision sets7
$B$ players and recorders
%edical e8uipment
C
Personal digital assistant
Bideogame consoles
Computer perip"erals suc" as routers and printers5
@ndustrial controllers for remote mac"ine operation5
'LOC4 DIAGRAM@
R# @$
REA$ER
%icro
controller
Power
supply
LC$
EEPR&%
.EDPA$
B6EEER
0
Bloc( $iagram description
T"is Pro/ect mainly consists of Power Supply section7 %icrocontroller section7 .eypad
section7 R#@$ Reader section7 LC$ display section7 EEPR&% section and RTC 9Real Time
Cloc(: section5
2o1er S!++"3 Se#tion@
T"is section is meant for supplying Power to all t"e sections mentioned a2oe5 @t
2asically consists of a Transformer to step down t"e 23*B ac to -B ac followed 2y diodes5 +ere
diodes are used to rectify t"e ac to dc5 After rectification t"e o2tained rippled dc is filtered using
a capacitor #ilter5 A positie oltage regulator is used to regulate t"e o2tained dc oltage5
Mi#ro#ontro""er Se#tion@
-
T"is section forms t"e control unit of t"e w"ole pro/ect5 T"is section 2asically consists of
a %icrocontroller wit" its associated circuitry li(e Crystal wit" capacitors7 Reset circuitry7 Pull
up resistors 9if needed: and so on5 T"e %icrocontroller forms t"e "eart of t"e pro/ect 2ecause it
controls t"e deices 2eing interfaced and communicates wit" t"e deices according to t"e
program 2eing written5
LCD Dis+"a3 Se#tion@
T"is section is 2asically meant to s"ow up t"e status of t"e pro/ect5 T"is pro/ect ma(es
use of Li8uid Crystal $isplay to display A prompt for necessary information5
4e3+a% Se#tion@
T"is section consists of a Linear .eypad5 T"is (eypad is used to enter t"e details of
e'piry date and purc"age date of t"e p"arma5 T"e (eypad is interfaced to microcontroller w"ic"
continuously scans t"e (eypad5
RFID Rea%er ;Ra%io Fre?!en#3 I%enti8i#ation<@
Radio #re8uency @dentification 9R#@$: is a generic term for non4contacting tec"nologies
t"at use radio waes to automatically identify people or o2/ects5 T"e com2ined antenna and
microc"ip are called an ?R#@$ transponder? or ?R#@$ tag? and wor( in com2ination wit" an
?R#@$ reader?5
Radio #re8uency @dentification 9R#@$: is t"e latest tec"nology t"at is 2eing adopted to
trac( and trace materials7 including 2oo(s5 R#@$ 2ased Li2rary %anagement System "as 2een
implemented in most of t"e reputed li2raries across t"e glo2e5 R#@$ interfaced li2rary
management system7 along wit" smart card issued to t"e users are 2eing implemented to
automate t"e li2rary functions and ma(e t"e inentory management process efficient and
effectie5 T"e system improes t"e trac(ing of 2oo(s and documents so t"at t"e 2oo(s can 2e
more 8uic(ly located7 t"e document wor(flow more easily trac(ed and transaction records are
seamlessly captured5
1*
EE2ROM Se#tion@
T"is section 2asically consists of an EEPR&%5 @n t"is pro/ect t"is section 2asically used
as a 2ac(end data2ase5 T"e details of t"e e'piry date and purc"ase date of medicines are stored in
t"e memory called EEPR&%5
S#-e)ati#
11
12
0ARD=ARE Co)+onents
T"e +ardware components used in t"is pro/ect are
Regulated Power Supply
%icrocontroller
R#@$ reader
13
LC$
.eypad
EEPR&%
2u33er
REGULATED 2O=ER SU22LY
T"e power supplies are designed to conert "ig" oltage AC mains electricity to a
suita2le low oltage supply for electronics circuits and ot"er deices5 A R2S 9Re!"ate% 2o1er
S!++"3: is t"e Power Supply wit" Rectification7 #iltering and Regulation 2eing done on t"e AC
mains to get a Regulated power supply for %icrocontroller and for t"e ot"er deices 2eing
interfaced to it5
1,
A power supply can 2y 2ro(en down into a series of 2loc(s7 eac" of w"ic" performs a
particular function5 A d5c power supply w"ic" maintains t"e output oltage constant irrespectie
of a5c mains fluctuations or load ariations is (nown as FRegulated $5C Power SupplyG
#or e'ample a 1B regulated power supply system as s"own 2elowH
#ig 1 Components of linear power supply
Trans8or)er@
A transformer is an electrical deice w"ic" is used to conert electrical power from
one Electrical circuit to anot"er wit"out c"ange in fre8uency5
Transformers conert AC electricity from one oltage to anot"er wit" little loss of
power5 Transformers wor( only wit" AC and t"is is one of t"e reasons w"y mains electricity is
AC5 Step4up transformers increase in output oltage7 step4down transformers decrease in output
oltage5 %ost power supplies use a step4down transformer to reduce t"e dangerously "ig" mains
oltage to a safer low oltage5 T"e input coil is called t"e primary and t"e output coil is called
t"e secondary5 T"ere is no electrical connection 2etween t"e two coilsI instead t"ey are lin(ed 2y
an alternating magnetic field created in t"e soft4iron core of t"e transformer5 T"e two lines in t"e
middle of t"e circuit sym2ol represent t"e core5 Transformers waste ery little power so t"e
power out is 9almost: e8ual to t"e power in5 !ote t"at as oltage is stepped down current is
stepped up5 T"e ratio of t"e num2er of turns on eac" coil7 called t"e turnJs ratio7 determines t"e
11
ratio of t"e oltages5 A step4down transformer "as a large num2er of turns on its primary 9input:
coil w"ic" is connected to t"e "ig" oltage mains supply7 and a small num2er of turns on its
secondary 9output: coil to gie a low output oltage5

#ig 2 H An E"e#tri#a" Trans8or)er
Turns ratio K BpA BS K !pA!S
Power &utK Power @n
BS < @SKBP < @P
Bp K primary 9input: oltage
!p K num2er of turns on primary coil
@p K primary 9input: current
RECTIFIER@
A circuit w"ic" is used to conert a5c to dc is (nown as RECT@#@ER5 T"e process of
conersion a5c to d5c is called FrectificationG
TY2ES OF RECTIFIERS@
+alf wae Rectifier
#ull wae rectifier
15 Centre tap full wae rectifier5
25 Bridge type full 2ridge rectifier5
Co)+arison o8 re#ti8ier #ir#!its@
2ara)eter
T3+e o8 Re#ti8ier
0a"8 1ave F!"" 1ave 'ri%e
!um2er of diodes
1

2

,
P@B of diodes
Bm

2Bm

Bm

1=
$5C output oltage BmA 2BmA 2BmA
Bdc7at
no4load

*5310Bm

*5=3=Bm *5=3=Bm
Ripple factor

1521

*5,02

*5,02
Ripple
fre8uency

f

2f

2f
Rectification
efficiency

*5,*=

*5012

*5012
Transformer
6tili3ation
#actor9T6#:

*520C *5=-3 *5012
R%S oltage Brms BmA2 BmAL2 BmAL2
F!""B1ave Re#ti8ier@
#rom t"e a2oe comparison we came to (now t"at full wae 2ridge rectifier as more
adantages t"an t"e ot"er two rectifiers5 So7 in our pro/ect we are using full wae 2ridge rectifier
circuit5
'ri%e Re#ti8ier@
A 2ridge rectifier ma(es use of four diodes in a 2ridge arrangement to ac"iee full4wae
rectification5 T"is is a widely used configuration7 2ot" wit" indiidual diodes wired as
s"own and wit" single component 2ridges w"ere t"e diode 2ridge is wired internally5
A 2ridge rectifier ma(es use of four diodes in a 2ridge arrangement as s"own in fig 93: to
ac"iee full4wae rectification5 T"is is a widely used configuration7 2ot" wit" indiidual diodes
wired as s"own and wit" single component 2ridges w"ere t"e diode 2ridge is wired internally5
1C
#ig 3 H Bridge rectifier
O+eration@
$uring positie "alf cycle of secondary7 t"e diodes $2 and $3 are in forward 2iased w"ile $1
and $, are in reerse 2iased as s"own in t"e fig9,:5 T"e current flow direction is s"own in t"e fig
9,: wit" dotted arrows5
#ig 9,:H Bridge Rectifier Positie Cycle
$uring negatie "alf cycle of secondary oltage7 t"e diodes $1 and $, are in forward 2iased
w"ile $2 and $3 are in reerse 2iased as s"own in t"e fig91:5 T"e current flow direction is
s"own in t"e fig 91: wit" dotted arrows5
10

#ig91: H Bridge Rectifier !egatie Cycle
Fi"ter@
A #ilter is a deice w"ic" remoes t"e a5c component of rectifier output 2ut
allows t"e d5c component to reac" t"e load
Ca+a#itor Fi"ter@
)e "ae seen t"at t"e ripple content in t"e rectified output of "alf wae rectifier is 121C or
t"at of full4wae or 2ridge rectifier or 2ridge rectifier is &/C suc" "ig" percentages of ripples is
not accepta2le for most of t"e applications5 Ripples can 2e remoed 2y one of t"e following
met"ods of filtering5
;a< A capacitor7 in parallel to t"e load7 proides an easier 2y Mpass for t"e ripples oltage t"oug"
it due to low impedance5 At ripple fre8uency and leae t"e $5C5 to appear at t"e load5
;b< An inductor7 in series wit" t"e load7 preents t"e passage of t"e ripple current 9due to "ig"
impedance at ripple fre8uency: w"ile allowing t"e d5c 9due to low resistance to d5c:
;#< Barious com2inations of capacitor and inductor7 suc" as L4section filter section filter7
multiple section filter etc5 )"ic" ma(e use of 2ot" t"e properties mentioned in 9a: and 92: a2oe5
Two cases of capacitor filter7 one applied on "alf wae rectifier and anot"er wit" full wae
rectifier5
#iltering is performed 2y a large alue electrolytic capacitor connected across t"e $C
supply to act as a reseroir7 supplying current to t"e output w"en t"e arying $C oltage from
t"e rectifier is falling5 T"e capacitor c"arges 8uic(ly near t"e pea( of t"e arying $C7 and t"en
1-
disc"arges as it supplies current to t"e output5 #iltering significantly increases t"e aerage $C
oltage to almost t"e pea( alue 915, N R%S alue:5
To calculate t"e alue of capacitor9C:7
C K OPL3PfPrPRl
)"ere7
f K supply fre8uency7
r K ripple factor7
Rl K load resistance
NoteH @n our circuit we are using 1***Q# "ence large alue of capacitor is placed to
reduce ripples and to improe t"e $C component5
Re!"ator@
Boltage regulator @cs is aaila2le wit" fi'ed 9typically 17 12 and 11B: or aria2le output
oltages5 T"e ma'imum current t"ey can pass also rates t"em5 !egatie oltage regulators are
aaila2le7 mainly for use in dual supplies5 %ost regulators include some automatic protection
from e'cessie current 9Roerload protectionJ: and oer"eating 9Rt"ermal protectionJ:5 %any of
t"e fi'ed oltage regulators @cs "ae 3 leads and loo( li(e power transistors7 suc" as t"e C0*1
S1B 1A regulator s"own on t"e rig"t5 T"e L%C0*1 is simple to use5 Dou simply connect t"e
positie lead of your unregulated $C power supply 9anyt"ing from -B$C to 2,B$C: to t"e
@nput pin7 connect t"e negatie lead to t"e Common pin and t"en w"en you turn on t"e power7
you get a 1 olt supply from t"e output pin5
#ig =H A T"ree Terminal Boltage Regulator
./XX@
2*
T"e Bay Linear L%C0<< is integrated linear positie regulator wit" t"ree terminals5 T"e
L%C0<< offer seeral fi'ed output oltages ma(ing t"em useful in wide range of applications5
)"en used as a 3ener diodeAresistor com2ination replacement7 t"e L%C0<< usually results in an
effectie output impedance improement of two orders of magnitude7 lower 8uiescent current5
T"e L%C0<< is aaila2le in t"e T&42127 T&422* T T&42=3pac(ages7
Feat!res@
U &utput Current of 151A
U &utput Boltage Tolerance of 1V
U @nternal t"ermal oerload protection
U @nternal S"ort4Circuit Limited
U &utput Boltage 15*B7 =B7 0B7 -B7 1*B7 12B7 11B7 10B7 2,B5
MICRO CONTROLLER /6C*1
Intro%!#tion
A %icro controller consists of a powerful CP6 tig"tly coupled wit" memory7 arious @A&
interfaces suc" as serial port7 parallel port timer or counter7 interrupt controller7 data ac8uisition
interfaces4Analog to $igital conerter7 $igital to Analog conerter7 integrated on to a single
silicon c"ip5
@f a system is deeloped wit" a microprocessor7 t"e designer "as to go for e'ternal
memory suc" as RA%7 R&%7 EPR&% and perip"erals5 But controller is proided all t"ese
facilities on a single c"ip5 $eelopment of a %icro controller reduces PCB si3e and cost of
design5
21
&ne of t"e ma/or differences 2etween a %icroprocessor and a %icro controller is t"at a controller
often deals wit" 2its not 2ytes as in t"e real world application5
@ntel "as introduced a family of %icro controllers called t"e %CS4115
T-e MaDor Feat!res@
Compati2le wit" %CS411 products
,( Bytes of in4system Reprogramma2le flas" memory
#ully static operationH *+E to 2,%+E
T"ree leel programma2le cloc(
120 P 0 M2it timerAcounters
Si' interrupt sources
Programma2le serial c"annel
Low power idle power4down modes
=-3 AT /6C*1
T"e system re8uirements and control specifications clearly rule out t"e use of 1=7 32 or
=, 2it micro controllers or microprocessors5 Systems using t"ese may 2e earlier to implement
due to large num2er of internal features5 T"ey are also faster and more relia2le 2ut7 042it micro
controller satisfactorily seres t"e a2oe application5 6sing an ine'pensie 042it %icrocontroller
will doom t"e 3242it product failure in any competitie mar(et place5
Coming to t"e 8uestion of w"y to use AT0-C11 of all t"e 042it microcontroller aaila2le
in t"e mar(et t"e main answer would 2e 2ecause it "as , .2 on c"ip flas" memory w"ic" is /ust
sufficient for our application5 T"e on4c"ip #las" R&% allows t"e program memory to 2e
reprogrammed in system or 2y conentional non4olatile memory Programmer5 %oreoer
AT%EL is t"e leader in flas" tec"nology in todayJs mar(et place and "ence using AT 0-C11 is
t"e optimal solution5
AT/6C*1 MICROCONTROLLER ARC0ITECTURE
T"e 0-C11 arc"itecture consists of t"ese specific featuresH
Eig"t M2it CP6 wit" registers A 9t"e accumulator: and B
22
Si'teen42it program counter 9PC: and data pointer 9$PTR:
Eig"t4 2it stac( pointer 9PS):
Eig"t42it stac( pointer 9Sp:
@nternal R&% or EPR&% 90C11: of *90*31: to ,. 90-C11:
@nternal RA% of 120 2ytesH
15 #our register 2an(s7 eac" containing eig"t registers
25 Si'teen 2ytes7 w"ic" may2e addressed at t"e 2it leel
35 Eig"ty 2ytes of general4 purpose data memory
T"irty Mtwo inputAoutput pins arranged as four 042it portsHp*4p3
Two 1=42it timerAcountersH T* and T1
#ull duple' serial data receierAtransmitterH SB6#
Control registersH TC&!7 T%&$7 SC&!7 PC&!7 @P7 and @E
Two e'ternal and t"ree internal interrupts sources5
&scillator and cloc( circuits5

23
#ig C H #unctional 2loc( diagram of micro controller

T-e /6C*1 os#i""ator an% #"o#(@
T"e "eart of t"e 0-C11 circuitry t"at generates t"e cloc( pulses 2y w"ic" all t"e internal
all internal operations are sync"roni3ed5 Pins <TAL1 And <TAL2 is proided for connecting a
resonant networ( to form an oscillator5 Typically a 8uart3 crystal and capacitors are employed5
T"e crystal fre8uency is t"e 2asic internal cloc( fre8uency of t"e microcontroller5 T"e
manufacturers ma(e 0-C11 designs t"at run at specific minimum and ma'imum fre8uencies
typically 1 to 1= %+35
4 &scillator and timing circuit
T3+es o8 )e)or3@
T"e 0-C11 "ae t"ree general types of memory5 T"ey are on4c"ip memory7 e'ternal Code
memory and e'ternal Ram5 &n4C"ip memory refers to p"ysically e'isting memory on t"e micro
2,
controller itself5 E'ternal code memory is t"e code memory t"at resides off c"ip5 T"is is often in
t"e form of an e'ternal EPR&%5 E'ternal RA% is t"e Ram t"at resides off c"ip5 T"is often is in
t"e form of standard static RA% or flas" RA%5
a< Co%e )e)or3
Code memory is t"e memory t"at "olds t"e actual 0-C11 programs t"at is to 2e run5 T"is
memory is limited to =,.5 Code memory may 2e found on4c"ip or off4c"ip5 @t is possi2le to "ae
,. of code memory on4c"ip and =*. off c"ip memory simultaneously5 @f only off4c"ip memory
is aaila2le t"en t"ere can 2e =,. of off c"ip R&%5 T"is is controlled 2y pin proided as EA
b< Interna" RAM
T"e 0-C11 "ae a 2an( of 120 of internal RA%5 T"e internal RA% is found on4c"ip5 So
it is t"e fastest Ram aaila2le5 And also it is most fle'i2le in terms of reading and writing5
@nternal Ram is olatile7 so w"en 0-C11 is reset7 t"is memory is cleared5 120 2ytes of internal
memory are su2diided5 T"e first 32 2ytes are diided into , register 2an(s5 Eac" 2an( contains
0 registers5 @nternal RA% also contains 120 2its7 w"ic" are addressed from 2*" to 2#"5 T"ese
2its are 2it addressed i5e5 eac" indiidual 2it of a 2yte can 2e addressed 2y t"e user5 T"ey are
num2ered **" to C#"5 T"e user may ma(e use of t"ese aria2les wit" commands suc" as SETB
and CLR5
FLAS0 MEMORY@
#las" memory 9sometimes called Fflas" RA%G: is a type of constantly4powered non
olatile t"at can 2e erased and reprogrammed in units of memory called blocks5 @t is a ariation
of electrically erasa2le programma2le read4only memory 9EEPR&%: w"ic"7 unli(e flas"
memory7 is erased and rewritten at t"e 2yte leel7 w"ic" is slower t"an flas" memory updating5
#las" memory is often used to "old control code suc" as t"e 2asic inputAoutput system 9B@&S: in
a personal computer5 )"en B@&S needs to 2e c"anged 9rewritten:7 t"e flas" memory can 2e
written to in 2loc( 9rat"er t"an 2yte: si3es7 ma(ing it easy to update5 &n t"e ot"er "and7 flas"
memory is not useful as random access memory 9RA%: 2ecause RA% needs to 2e addressa2le
at t"e 2yte 9not t"e 2loc(: leel5
#las" memory gets its name 2ecause t"e microc"ip is organi3ed so t"at a section of
memory cells are erased in a single action or Fflas"5G T"e erasure is caused 2y #owler4!ord"eim
tunneling in w"ic" electrons pierce t"roug" a t"in dielectric material to remoe an electronic
c"arge from a floating gate associated wit" eac" memory cell5 @ntel offers a form of flas"
21
memory t"at "olds two 2its 9rat"er t"an one: in eac" memory cell7 t"us dou2ling t"e capacity of
memory wit"out a corresponding increase in price5
#las" memory is used in digital cellular p"ones7 digital cameras7 LA! switc"es7 PC
Cards for note2oo( computers7 digital set4up 2o'es7 em2edded controllers7 and ot"er deices5
Me)or3 T3+e Feat!res
FLAS0 Low4cost7 "ig"4density7 "ig"4speed
arc"itectureI low powerI "ig" relia2ility
ROM
Read4&nly %emory
%ature7 "ig"4density7 relia2le7 low costI
time4consuming mas( re8uired7 suita2le
for "ig" production wit" sta2le code
SRAM
Static Random4Access %emory
+ig"est speed7 "ig"4power7 low4density
memoryI limited density dries up cost
E2ROM
Electrically Programma2le Read4&nly
%emory
+ig"4density memoryI must 2e e'posed
to ultraiolet lig"t for erasure
EE2ROMorE
2
2ROM
Electrically Erasa2le Programma2le
Read4&nly %emory
Electrically 2yte4erasa2leI lower
relia2ility7 "ig"er cost7 lowest density
DRAM
$ynamic Random Access %emory
+ig"4density7 low4cost7 "ig"4speed7
"ig"4power
Te#-ni#a" Overvie1 o8 F"as- Me)or3
#las" memory is a nonolatile memory using !&R tec"nology7 w"ic" allows t"e user to
electrically program and erase information5 @ntelW #las" memory uses memory cells similar to
an EPR&%7 2ut wit" a muc" t"inner7 precisely grown o'ide 2etween t"e floating gate and t"e
source 5 #las" programming occurs w"en electrons are placed on t"e floating gate5 T"e c"arge is
stored on t"e floating gate7 wit" t"e o'ide layer allowing t"e cell to 2e electrically erased t"roug"
t"e source5 @ntel #las" memory is an e'tremely relia2le nonolatile memory arc"itecture5
2=
#ig 0H Pin diagram of AT0-C11
2in Des#ri+tion@
ECC@ Supply oltage5
GND@ Xround5
2ort 7@
Port * is an 042it open4drain 2i4directional @A& port5 As an output port7 eac" pin can sin(
eig"t TTL inputs5 )"en oneJs are written to port * pins7 t"e pins can 2e used as "ig" impedance
inputs5 Port * may also 2e configured to 2e t"e multiple'ed low order addressAdata 2us during
accesses to e'ternal program and data memory5 @n t"is mode P* "as internal pull4ups5 Port * also
receies t"e code 2ytes during #las" programming7 and outputs t"e code 2ytes during program
erification5 E'ternal pull4ups are re8uired during program erification5
2ort 1@
Port 1 is an 042it 2i4directional @A& port wit" internal pull4ups5 T"e Port 1 output 2uffers
can sin(Asource four TTL inputs5 )"en 1s are written to Port 1 pins t"ey are pulled "ig" 2y t"e
2C
internal pull4ups and can 2e used as inputs5 As inputs7 Port 1 pins t"at are e'ternally 2eing pulled
low will source current 9@@L: 2ecause of t"e internal pull4ups5 Port 1 also receies t"e low4order
address 2ytes during #las" programming and erification5
2ort 2@
low will source current 9@@L: 2ecause of t"e internal pull4ups5 Port 2 emits t"e "ig"4order address
2yte during fetc"es from e'ternal program memory and during accesses to e'ternal data
memories t"at use 1=42it addresses 9%&B< Y$PTR:5 @n t"is application7 it uses strong internal
pull4ups w"en emitting 1s5 $uring accesses to e'ternal data memories t"at use 042it addresses
9%&B< Y R@:7 Port 2 emits t"e contents of t"e P2 Special #unction Register5 Port 2 also
receies t"e "ig"4order address 2its and some control signals during #las" programming and
erification5
2ort $@
low will source current 9@@L: 2ecause of t"e pull4ups5
Port 3 also seres t"e functions of arious special features of t"e AT0-C11 as listed 2elowH
Port 3 also receies some control signals for #las" programming and erification
20
Ta2 =5251 Port pins and t"eir alternate functions
RST@
Reset input5 A "ig" on t"is pin for two mac"ine cycles w"ile t"e oscillator is running
resets t"e deice5
ALE>2ROG@
Address Latc" Ena2le output pulse for latc"ing t"e low 2yte of t"e address during
accesses to e'ternal memory5 T"is pin is also t"e program pulse input 9PR&X: during #las"
programming5 @n normal operation ALE is emitted at a constant rate of 1A=t"e oscillator
fre8uency7 and may 2e used for e'ternal timing or cloc(ing purposes5 !ote7 "oweer7 t"at one
ALE pulse is s(ipped during eac" access to e'ternal $ata %emory5
@f desired7 ALE operation can 2e disa2led 2y setting 2it * of S#R location 0E+5 )it" t"e 2it set7
ALE is actie only during a %&B< or %&BC instruction5 &t"erwise7 t"e pin is pulled "ig"5
Setting t"e ALE4disa2le 2it "as no effect if t"e microcontroller is in e'ternal e'ecution mode5
2SEN@
Program Store Ena2le is t"e read stro2e to e'ternal program memory5 )"en t"e AT0-C11
is e'ecuting code from e'ternal program memory7 PSE! is actiated twice eac" mac"ine cycle7
e'cept t"at two PSE! actiations are s(ipped during eac" access to e'ternal data memory5
EA>E22@
2-
E'ternal Access Ena2le EA must 2e strapped to X!$ in order to ena2le t"e deice to
fetc" code from e'ternal program memory locations starting at ****+ up to ####+5
!ote7 "oweer7 t"at if loc( 2it 1 is programmed7 EA will 2e internally latc"ed on reset5
EA s"ould 2e strapped to BCC for internal program e'ecutions5 T"is pin also receies t"e 124
olt programming ena2le oltage 9BPP: during #las" programming7 for parts t"at re8uire 124olt
BPP5
XTAL1@
@nput to t"e inerting oscillator amplifier and input to t"e internal cloc( operating circuit5
XTAL2@
@t is t"e &utput from t"e inerting oscillator amplifier5
Os#i""ator C-ara#teristi#s@
<TAL1 and <TAL2 are t"e input and output7 respectiely7 of an inerting amplifier
w"ic" can 2e configured for use as an on4c"ip oscillator7 as s"own in #igs -5 Eit"er a 8uart3
crystal or ceramic resonator may 2e used5 To drie t"e deice from an e'ternal cloc( source7
<TAL2 s"ould 2e left unconnected w"ile <TAL1 is drien as s"own in #igure 1*5T"ere are no
re8uirements on t"e duty cycle of t"e e'ternal cloc( signal7 since t"e input to t"e internal
cloc(ing circuitry is t"roug" a diide42y4two flip4flop7 2ut minimum and ma'imum oltage "ig"
and low time specifications must 2e o2sered5
#ig - &scillator Connections
3*
#ig 1* E'ternal Cloc( $rie Configuration

NotesH
2 6nder steady state 9non4transient: conditions7 @&L must 2e e'ternally
limited as followsH
%a'imum @&L per port pin H 1* mA
%a'imum @&L per 042it port H Port * H 2= mA
Ports 17 27 3H 11 mA
%a'imum total @&L for all output pinsH C1 mA
@f @&L e'ceeds t"e test condition7 B&L may e'ceed t"e related specification5 Pins are
not guaranteed to sin( current greater t"an t"e listed test conditions5
2. %inimum BCC for Power4down is 2B5
REGISTERS@
@n t"e CP67 registers are used to store information temporarily5 T"at information could
2e a 2yte of data to 2e processed7 or an address pointing to t"e data to 2e fetc"ed5 T"e ast
ma/ority of 0*11 registers are 0M2it registers5 @n t"e 0*11 t"ere is only one data typeH 02its5 T"e
02its of a register are s"own in t"e diagram from t"e %SB 9most significant 2it: $C to t"e LSB
9least significant 2it: $*5 )it" an 042it data type7 any data larger t"an 02its must 2e 2ro(en into
042it c"un(s 2efore it is processed5 Since t"ere are a large num2er of registers in t"e 0*117 we
31
will concentrate on some of t"e widely used general4purpose registers and coer special registers
in future c"apters5
$C $= $1 $, $3 $2 $1 $*
T"e most widely used registers of t"e 0*11 are A 9accumulator:7 B7 R*7 R17 R27 R37 R,7
R17 R=7 RC7 $PTR 9data pointer:7 and PC 9program counter:5 All of t"e a2oe registers are 04
2its7 e'cept $PTR and t"e program counter5 T"e accumulator7 register A7 is used for all
arit"metic and logic instructions5
SFRs ;S+e#ia" F!n#tion Reisters<
Among t"e registers R*4RC is part of t"e 120 2ytes of RA% memory5 )"at a2out
registers A7 B7 PS)7 and $PTRZ $o t"ey also "ae addressesZ T"e answer is yes5 @n t"e 0*117
registers A7 B7 PS) and $PTR are part of t"e group of registers commonly referred to as S#R
9special function registers:5 T"ere are many special function registers and t"ey are widely used5
T"e S#R can 2e accessed 2y t"e names 9w"ic" is muc" easier: or 2y t"eir addresses5 #or
e'ample7 register A "as address E*"7 and register B "as 2een ignited t"e address #*+7 as s"own
in ta2le5
T"e following two points s"ould noted a2out t"e S#R addresses5
15 T"e Special function registers "ae addresses 2etween 0*+ and ##+5 T"ese
addresses are a2oe 0*+7 since t"e addresses ** to C#+ are addresses of RA%
memory inside t"e 0*115
25 !ot all t"e address space of 0*+ to ##+ is used 2y t"e S#R5 T"e unused locations
0*+ to ##+ are resered and must not 2e used 2y t"e 0*11 programmer5
Regarding direct addressing mode7 notice t"e following two pointsH 9a: t"e address alue
is limited to one 2yte7 **4##+7 w"ic" means t"is addressing mode is limited to accessing RA%
locations and registers located inside t"e 0*115 92: @f you e'amine t"e l
st
file for an assem2ly
language program7 you will see t"at t"e S#R registers names are replaced wit" t"eir addresses as
listed in ta2le5
S3)bo" Na)e A%%ress
32
ACC Accumulator *E*+
B B register *#*+
PS) Program status word *$*+
SP Stac( pointer 01+
$PTR $ata pointer 2 2ytes
$PL Low 2yte 02+
$P+ +ig" 2yte 03+
P* Port* 0*+
P1 Port1 -*+
P2 Port2 *A*+
P3 Port3 *B*+
@P @nterrupt priority control *B0+
@E @nterrupt ena2le control *A0+
T%&$ TimerAcounter mode control 0-+
TC&! TimerAcounter control 00+
T2C&! TimerAcounter 2 control *C0+
T2%&$ TimerAcounter mode2 control *C-+
T+* TimerAcounter *"ig" 2yte 0C+
TL* TimerAcounter * low 2yte 0A+
T+1 TimerAcounter 1 "ig" 2yte 0$+
TL1 TimerAcounter 1 low 2yte 0B+
T+2 TimerAcounter 2 "ig" 2yte *C$+
TL2 TimerAcounter 2 low 2yte *CC+
RCAP2+ TAC 2 capture register "ig" 2yte *CB+
RCAP2L TAC 2 capture register low 2yte *CA+
SC&! Serial control -0+
SB6# Serial data 2uffer --+
PC&! Power control 0C+
Tab"e@ /7*1 S+e#ia" 8!n#tion reister A%%ress
A Reister ;A##!)!"ator<

#ig 11H Accumulator register
T"is is a general4purpose register w"ic" seres for storing intermediate results during operating5
A num2er 9an operand: s"ould 2e added to t"e accumulator prior to e'ecute an instruction upon
33
it5 &nce an arit"metical operation is preformed 2y t"e AL67 t"e result is placed into t"e
accumulator5 @f a data s"ould 2e transferred from one register to anot"er7 it must go t"roug"
accumulator5 #or suc" uniersal purpose7 t"is is t"e most commonly used register t"at none
microcontroller can 2e imagined wit"out 9more t"an a "alf 0*11 microcontrollerJs instructions
used use t"e accumulator in some way:5
' Reister
B register is used during multiply and diide operations w"ic" can 2e performed only upon
num2ers stored in t"e A and B registers5 All ot"er instructions in t"e program can use t"is register
as a spare accumulator 9A:5
#ig 12H B register
$uring programming7 eac" of registers is called 2y name so t"at t"eir e'act address is not
so important for t"e user5 $uring compiling into mac"ine code 9series of "e'adecimal num2ers
recogni3ed as instructions 2y t"e microcontroller:7 PC will automatically7 instead of registersJ
name7 write necessary addresses into t"e microcontroller5
R Reisters ;R7BR.<
3,
#ig 13HRA%
T"is is a common name for t"e total 0 general purpose registers 9R*7 R17 and R2 555RC:5
Een t"ey are not true S#Rs7 t"ey desere to 2e discussed "ere 2ecause of t"eir purpose5 T"e
2an( is actie w"en t"e R registers it includes are in use5 Similar to t"e accumulator7 t"ey are
used for temporary storing aria2les and intermediate results5 )"ic" of t"e 2an(s will 2e actie
depends on two 2its included in t"e PS) Register5 T"ese registers are stored in four 2an(s in t"e
scope of RA%5
T"e following e'ample 2est illustrates t"e useful purpose of t"ese registers5 Suppose t"at
mat"ematical operations on num2ers preiously stored in t"e R registers s"ould 2e performedH
9R1SR2: M 9R3SR,:5 &2iously7 a register for temporary storing results of addition is needed5
Eeryt"ing is 8uite simple and t"e program is as followsH
MOE AF R$G %eansH moe num2er from R3 into accumulator
ADD AF R&G %eansH add num2er from R, to accumulator 9result remains in accumulator:
MOE R*F AG %eansH temporarily moes t"e result from accumulator into R1
MOE AF R1G %eansH moe num2er from R1 into accumulator
ADD AF R2G %eansH add num2er from R2 to accumulator
SU'' AF R*G %eansH su2tract num2er from R1 9t"ere are R3SR,:
31
/7*1 Reister 'an(s an% Sta#(
RAM )e)or3 s+a#e a""o#ation in t-e /7*1
T"ere are 120 2ytes of RA% in t"e 0*115 T"e 120 2ytes of RA% inside t"e 0*11 are
assigned addresses ** toC#+5 T"ese 120 2ytes are diided into t"ree different groups as followsH
15 A total of 32 2ytes from locations ** to 1#+ "e' are set aside for register 2an(s and
t"e stac(5
25 A total of 1= 2ytes from locations 2* to 2#+ "e' are set aside for 2it4addressa2le
readAwrite memory5
35 A total of 0* 2ytes from locations 3*+ to C#+ are used for read and write storage7 or
w"at is normally called Scratc" pad5 T"ese 0* locations of RA% are widely used for
t"e purpose of storing data and parameters nu 0*11 programmers5
Reister ban(s in t-e /7*1
A total of 322ytes of RA% are set aside for t"e register 2an(s and stac(5 T"ese 32
2ytes are diided into , 2an(s of registers in w"ic" eac" 2an( "as registers7 R*4RC5 RA%
locations * to C are set aside for 2an( * of R*4RC w"ere R* is RA% location *7 R1 is RA%
location 17 and R2 is location 27 and so on7 until memory locationC7 w"ic" 2elongs to RC of
2an(*5 T"e second 2an( of registers R*4RC starts at RA% location *0 and goes to location *#+5
T"e t"ird 2an( of R*4RC starts at memory location 1*+ and goes to location 1C+5 #inally7 RA%
locations 10+ to 1#+ are set aside for t"e fourt" 2an( of R*4RC5 #ig s"ows "ow t"e 32 2ytes are
allocated into , 2an(s5
As we can see from fig 17 t"e 2an( 1 uses t"e same RA% space as t"e stac(5 T"is is a
ma/or pro2lem in programming t"e 0*115 )e must eit"er not use register 2an(17 or allocate
anot"er area of RA% for t"e stac(5
De8a!"t reister ban(
@f RA% locations **41# are set aside for t"e four register 2an(s7 w"ic" register 2an( of
R*4RC do we "ae access to w"en t"e 0*11 is powered upZ T"e answer is register 2an( *I t"at
is 7 RA% locations *7 172737,717=7 and C are accessed wit" t"e names R*7 R17 R27 R37 R,7 R17 R=7
and RC w"en programming t"e 0*115 @t is muc" easier to refer to t"ese RA% locations wit"
3=
names suc" as R*7 R1 and so on7 t"an 2y t"eir memory locations as s"own in fig 25T"e register
2an(s are switc"ed 2y using t"e $3 T $, 2its of register PS)5

#@X1, H RA% Allocation in t"e 0*11
3C
#ig 11H 0*11 Register Ban(s and t"eir RA% Addresses
2S= Reister ;2rora) Stat!s =or%<
#ig 1=H PS) register
T"is is one of t"e most important S#Rs5 T"e Program Status )ord 9PS): contains
seeral status 2its t"at reflect t"e current state of t"e CP65 T"is register containsH Carry 2it7
Au'iliary Carry7 two register 2an( select 2its7 &erflow flag7 parity 2it7 and user4defina2le status
flag5 T"e AL6 automatically c"anges some of registerJs 2its7 w"ic" is usually used in regulation
of t"e program performing5
2 H 2arit3 bit @f a num2er in accumulator is een t"en t"is 2it will 2e automatically set 91:7
ot"erwise it will 2e cleared 9*:5 @t is mainly used during data transmission and receiing ia
serial communication5
B 'it 1. T"is 2it is intended for t"e future ersions of t"e microcontrollers7 so it is not supposed to
2e "ere5
OE Over8"o1 occurs w"en t"e result of arit"metical operation is greater t"an 211 9decimal:7 so
t"at it can not 2e stored in one register5 @n t"at case7 t"is 2it will 2e set 91:5 @f t"ere is no oerflow7
t"is 2it will 2e cleared 9*:5
RS7F RS1 H Reister ban( se"e#ts bits. T"ese two 2its are used to select one of t"e four register
2an(s in RA%5 By writing 3eroes and ones to t"ese 2its7 a group of registers R*4RC is stored in
one of four 2an(s in RA%5
RS1 RS2 S+a#e in RAM
* * Ban(* **"4*C"
30
* 1 Ban(1 *0"4*#"
1 * Ban(2 1*"41C"
1 1 Ban(3 10"41#"
F7 H F"a 7. T"is is a general4purpose 2it aaila2le to t"e user5
AC H A!Ai"iar3 Carr3 F"a is used for BC$ operations only5
CY H Carr3 F"a is t"e 9nint": au'iliary 2it used for all arit"metical operations and s"ift
instructions5
D2TR Reister ;Data 2ointer<
T"ese registers are not true ones 2ecause t"ey do not p"ysically e'ist5 T"ey consist of
two separate registersH $P+ 9$ata Pointer +ig": and 9$ata Pointer Low:5 T"eir 1= 2its are used
for e'ternal memory addressing5 T"ey may 2e "andled as a 1=42it register or as two independent
042it registers5 Besides7 t"e $PTR Register is usually used for storing data and intermediate
results w"ic" "ae not"ing to do wit" memory locations5
#ig 1CH $PTR register
S2 Reister ;Sta#( 2ointer<
3-

#ig 10H SP register
T"e stac( is a section of RA% used 2y t"e CP6 to store information temporarily5 T"is
information could 2e data or an address5 T"e CP6 needs t"is storage area since t"ere are only a
limited num2er of registers5
0o1 sta#(s are a##esse% in t-e /7*1
@f t"e stac( is a section of RA%7 t"ere must 2e registers inside t"e CP6 to point to it5
T"e register used to access t"e stac( is called t"e SP 9Stac( point: Register5 T"e stac( pointer in
t"e 0*11 is only 0 2its wideI w"ic" means t"at it can ta(e alues of ** to ##+5 )"en t"e 0*11 is
powered up7 t"e SP register contains alue *C5 T"is means t"at RA% location *0 is t"e first
location used for t"e stac( 2y t"e 0*115 T"e storing of a CP6 register in t"e stac( is called a
P6S+7 and pulling t"e contents off t"e stac( 2ac( into a CP6 register is called a P&P5 @n ot"er
words7 a register is pus"ed onto t"e stac( to sae it and popped off t"e stac( to retriee it5 T"e
/o2 of t"e SP is ery critical w"en pus" and pop actions are performed5
2!s-in onto t-e sta#(
@n t"e 0*11 t"e stac( pointer 9SP: points to t"e last used location of t"e stac(5 As we
pus" data onto t"e stac(7 t"e stac( pointer is incremented 2y one5 !otice t"at t"is different from
many microprocessors7 nota2ly '0= processors in w"ic" t"e SP is decremented w"en data is
pus"ed onto t"e stac(5 As eac" P6S+ is e'ecuted7 t"e contents of t"e register are saed on t"e
stac( and SP is incremented 2y 15 !otice t"at for eery 2yte of data saed on t"e stac( and t"en
SP is incremented only once5 !otice also t"at to pus" t"e registers onto t"e stac( we must use
t"eir RA% addresses5 #or e'ample7 t"e instruction FP6S+G pus"es register R1 onto t"e stac(5
2o++in 8ro) t-e sta#(
,*
Popping t"e contents of t"e stac( 2ac( into a gien register is t"e opposite process of
pus"ing5 )it" eery pop7 t"e top 2yte of t"e stac( is copied to t"e register specified 2y t"e
instruction and t"e stac( pointer is decremented once5
T-e !++er "i)it o8 t-e sta#(
As7 mentioned earlier7 locations *0 to 1#+ in t"e 0*11 RA% can 2e used for t"e stac(5
T"is is 2ecause locations 2*42#+ of RA% are resered for 2it4addressa2le memory and must not
2e used 2y t"e stac(5 @f in a program we need more t"an 2, 2ytes 9*0 to 1#+K2,2ytes: of stac(7
we can c"ange t"e SP to point to RA% locations 3*4C#+5 T"is is done wit" t"e instruction
F%&B SP7 [<<G5
27F 21F 22F 2$ H In+!t>O!t+!t Reisters

#ig 1-H P&RT* @A& register
@n case t"at e'ternal memory and serial communication system are not in use t"en7 ,
ports wit" in total of 32 input4output lines are aaila2le to t"e user for connection to perip"eral
enironment5 Eac" 2it inside t"ese ports corresponds to t"e appropriate pin on t"e
microcontroller5 T"is means t"at logic state written to t"ese ports appears as a oltage on t"e pin
9* or 1 B:5 !aturally7 w"ile reading7 t"e opposite occurs M oltage on some input pins is reflected
in t"e appropriate port 2it5
T"e state of a port 2it7 2esides 2eing reflected in t"e pin7 determines at t"e same time
w"et"er it will 2e configured as input or output5 @f a 2it is cleared 9*:7 t"e pin will 2e configured
as output5 @n t"e same manner7 if a 2it is set to 1 t"e pin will 2e configured as input5 After reset7
as well as w"en turning t"e microcontroller &!7 all 2its on t"ese ports are set to one ;1<5 T"is
means t"at t"e appropriate pins will 2e configured as in+!ts5
2rora) #o!nterH
,1
T"e important register in t"e 0*11 is t"e PC 9Program counter:5 T"e program counter
points to t"e address of t"e ne't instruction to 2e e'ecuted5 As t"e CP6 fetc"es t"e &PC&$E
from t"e program R&%7 t"e program counter is incremented to point to t"e ne't instruction5 T"e
program counter in t"e 0*11 is 1=2its wide5 T"is means t"at t"e 0*11 can access program
addresses **** to ####+7 a total of =,( 2ytes of code5 +oweer7 not all mem2ers of t"e 0*11
"ae t"e entire =,. 2ytes of on4c"ip R&% installed7 as we will see soon5
T3+es o8 instr!#tions
$epending on operation t"ey perform7 all instructions are diided in seeral groupsH
Arit"metic @nstructions
Branc" @nstructions
$ata Transfer @nstructions
Logical @nstructions
Logical @nstructions wit" 2its
T"e first part of eac" instruction7 called %!E%&!@C refers to t"e operation an instruction
performs 9copying7 addition7 logical operation etc5:5 %nemonics commonly are s"ortened form
of name of operation 2eing e'ecuted5 #or e'ampleH
INC R1I @ncrement R1 9increment register R1:
LJMP LAB5 ILong \ump LAB1 9long /ump to address specified as LAB1:
JNZ LOOP I\ump if !ot Eero L&&P 9if t"e num2er in t"e accumulator is not *7 /ump to address
specified as L&&P:
Anot"er part of instruction7 called &PERA!$ is separated from mnemonic at least 2y
one empty space and defines data 2eing processed 2y instructions5 Some instructions "ae no
operandI some "ae one7 two or t"ree5 @f t"ere is more t"an one operand in instruction7 t"ey are
separated 2y comma5 #or e'ampleH
RET M 9return from su24routine:
,2
JZ TEMP M 9if t"e num2er in t"e accumulator is not *7 /ump to address specified as TE%P:
ADD A,R3 M 9add R3 and accumulator:
CJNE A,#20,LOOP M 9compare accumulator wit" 2*5 @f t"ey are not e8ual7 /ump to address
specified as L&&P:
Arit-)eti# instr!#tions
T"ese instructions perform seeral 2asic operations 9addition7 su2traction7 diision7
multiplication etc5: After e'ecution7 t"e result is stored in t"e first operand5 #or e'ampleH
ADD A, R1 M T"e result of addition 9ASR1: will 2e stored in t"e accumulator5
Arit-)eti#a" Instr!#tions
Mne)oni# Des#ri+tion
'3te
N!)ber
Os#i""ator
2erio%
A$$ A7Rn Add R Register to accumulator 1 1
A$$ A7R'
Add directly addressed R' Register to
accumulator
2 2
A$$ A7YRi
Add indirectly addressed Register to
accumulator
1 1
A$$ A7[< Add num2er < to accumulator 2 2
A$$C A7Rn Add R Register wit" Carry 2it to accumulator 1 1
'ran#- Instr!#tions
T"ere are two (inds of t"ese instructionsH
Un#on%itiona" D!)+ instr!#tions@
After t"eir e'ecution a /ump to a new location from w"ere t"e program continues
e'ecution is e'ecuted5
,3
Con%itiona" D!)+ instr!#tions@
@f some condition is met M a /ump is e'ecuted5 &t"erwise7 t"e program normally
proceeds wit" t"e ne't instruction5
'ran#- Instr!#tion
'3te
N!)ber
Os#i""ator
2erio%
ACALL
adr11
Call su2routine located at address wit"in 2 . 2yte
Program %emory space
2 3
LCALL adr1=
Call su2routine located at any address wit"in =, .
2yte Program %emory space
3 ,
RET Return from su2routine 1 ,
RET@ Return from interrupt routine 1 ,
A\%P adr11
\ump to address located wit"in 2 . 2yte Program
%emory space
2 3
L\%P adr1=
\ump to any address located wit"in =, . 2yte
Program %emory space
3 ,
Data Trans8er Instr!#tions
T"ese instructions moe t"e content of one register to anot"er one5 T"e register w"ic"
content is moed remains unc"anged5 @f t"ey "ae t"e suffi' F<G 9%&B<:7 t"e data is
e'c"anged wit" e'ternal memory5
Data Trans8er Instr!#tion
'3te
N!)ber
C3#"e
N!)ber
%&B A7Rn %oe R register to accumulator 1 1
%&B A7R'
%oe directly addressed R' register to
accumulator
2 2
%&B A7YRi %oe indirectly addressed register to 1 1
,,
accumulator
%&B A7[< %oe num2er < to accumulator 2 2
Loi#a" Instr!#tions
T"ese instructions perform logical operations 2etween corresponding 2its of two
registers5 After e'ecution7 t"e result is stored in t"e first operand5
Loi#a" Instr!#tions
'3te
N!)ber
C3#"e
N!)ber
A!L A7Rn Logical A!$ 2etween accumulator and R register 1 1
A!L A7R'
Logical A!$ 2etween accumulator and directly
addressed register R'
2 2
A!L A7YRi
Logical A!$ 2etween accumulator and indirectly
addressed register
1 1
A!L A7[< Logical A!$ 2etween accumulator and num2er < 2 2
Loi#a" O+erations on 'its
Similar to logical instructions7 t"ese instructions perform logical operations5 T"e
difference is t"at t"ese operations are performed on single 2its5
Loi#a" o+erations on bits
'3te
N!)ber
C3#"e
N!)ber
CLR C Clear Carry 2it 1 1
CLR 2it Clear directly addressed 2it 2 2
SETB C Set Carry 2it 1 1
SETB 2it Set directly addressed 2it 2 2
CPL C Complement Carry 2it 1 1
CPL 2it Complement directly addressed 2it 2 2
,1
TIMERS
&n4c"ip timingAcounting facility "as proed t"e capa2ilities of t"e microcontroller for
implementing t"e real time application5 T"ese includes pulse counting7 fre8uency measurement7
pulse widt" measurement7 2aud rate generation7 etc75 +aing sufficient num2er of timerAcounters
may 2e a need in a certain design application5 T"e 0*11 "as two timersAcounters5 T"ey can 2e
used eit"er as timers to generate a time delay or as counters to count eents "appening outside
t"e microcontroller5 Let discuss "ow t"ese timers are used to generate time delays and we will
also discuss "ow t"ey are 2een used as eent counters5
2ROGRAMMING /7*1 TIMERS
T"e 0*11 "as timersH Timer * and Timer15t"ey can 2e used eit"er as timers or as eent
counters5 Let us first discuss a2out t"e timersJ registers and "ow to program t"e timers to
generate time delays5
'ASIC RIGISTERS OF T0E TIMER
Bot" Timer * and Timer 1 are 1= 2its wide5 Since t"e 0*11 "as an 042it arc"itecture7 eac"
1=42it timer is accessed as two separate registers of low 2yte and "ig" 2yte5
TIMER 7 REGISTERS
T"e 1=42it register of Timer * is accessed as low 2yte and "ig" 2yte5 T"e low 2yte
register is called TL*9Timer * low 2yte:and t"e "ig" 2yte register is referred to as T+*9Timer *
"ig" 2yte:5T"ese register can 2e accessed li(e any ot"er register7 suc" as A7B7R*7R17R27etc5for
e'ample7 t"e instruction G%&B TL*7 [,#Gmoes t"e alue ,#+ into TL*7t"e low 2yte of Timer
*5T"ese registers can also 2e read li(e any ot"er register5
#ig 2*HTimer *9T+* and TL* : registers
,=
TIMER 1 REGISTERS
Timer 1 is also 1=42it register is split into two 2ytes7 referred to as TL1 9Timer 1 low
2yte: and T+1 9Timer 1 "ig" 2yte:5t"ese registers are accessi2le n t"e same way as t"e register of
Timer *5
TMOD ;ti)er )o%e< REGISTER
Bot" timers T@%ER * and T@%ER 1 use t"e same register7 called T%&$7 to set t"e
arious timer operation modes5 T%&$ is an 042it register in w"ic" t"e lower , 2its are set aside
for Timer * and t"e upper , 2its for Timer 15in eac" caseI t"e lower 2 2its are used to set t"e
timer mode and t"e upper 2 2its to specify t"e operation5
MODES@
M1F M7@
%* and %1 are used to select t"e timer mode5 T"ere are t"ree modesH *7 17 25%ode * is
a 1342it timer7 mode 1 is a 1=42it timer7 and mode 2 is an 042it timer5 )e will concentrate on
modes 1 and 2 since t"ey are t"e ones used most widely5 )e will soon descri2e t"e
c"aracteristics of t"ese modes7 after descri2ing t"e reset of t"e T%&$ register5
GATE@ Xate control w"en set5 T"e timerAcounter is ena2led only
)"ile t"e @!T' pin is "ig" and t"e TR' control pin is5
Set5 )"en cleared7 t"e timer is ena2led5
C>T Timer or counter selected cleared for timer operation
9@nput from internal system cloc(:5set for counter
&peration 9input T< input pin:5
M 1 %ode 2it 1
M7 %ode 2it *
M1 M7 MODE O+eratin Mo%e
,C
* 7 7 1342it timer mode
042it timerAcounter T+' wit"
TL' as 1 M Bit pre4scaler5
7 1 1 1=42it timer mode
1=42it timerAcounters T+'
wit" TL' are CascadedI t"ere
is no prescaler
1 * 2 042it auto reload
042it auto reload
timerAcounterIT+' +olds a
alue t"at is to 2e reloaded
into TL' eac" time it
oerflows5
1 1 $ Split timer mode5

C>T ;#"o#(>ti)er<
T"is 2it in t"e T%&$ register is used to decide w"et"er t"e timer is used as a delay
generator or an eent counter5 @f CATK*7 it is used as a timer for time delay generation5 T"e cloc(
source for t"e time delay is t"e crystal fre8uency of t"e 0*115t"is section is concerned wit" t"is
c"oice5 T"e timerJs use as an eent counter is discussed in t"e ne't section5
Seria" Co))!ni#ation@
Computers can transfer data in two waysH parallel and serial5 @n parallel data transfers7
often 0 or more lines 9wire conductors: are used to transfer data to a deice t"at is only a few feet
away5 E'amples of parallel data transfer are printers and "ard dis(sI eac" uses ca2les wit" many
wire strips5 Alt"oug" in suc" cases a lot of data can 2e transferred in a s"ort amount of time 2y
using many wires in parallel7 t"e distance cannot 2e great5 To transfer to a deice located many
meters away7 t"e serial met"od is used5 @n serial communication7 t"e data is sent one 2it at a
time7 in contrast to parallel communication7 in w"ic" t"e data is sent a 2yte or more at a time5
Serial communication of t"e 0*11 is t"e topic of t"is c"apter5 T"e 0*11 "as serial
,0
communication capa2ility 2uilt into it7 t"ere 2y ma(ing possi2le fast data transfer using only a
few wires5
@f data is to 2e transferred on t"e telep"one line7 it must 2e conerted from *s and 1s to
audio tones7 w"ic" are sinusoidal4s"aped signals5 A perip"eral deice called a modem7 w"ic"
stands for FmodulatorAdemodulatorG7 performs t"is conersion5
Serial data communication uses two met"ods7 async"ronous and sync"ronous5 T"e
sync"ronous met"od transfers a 2loc( of data at a time7 w"ile t"e async"ronous met"od transfers
a single 2yte at a time5
@n data transmission if t"e data can 2e transmitted and receied7 it is a duple'
transmission5 T"is is in contrast to simple' transmissions suc" as wit" printers7 in w"ic" t"e
computer only sends data5 $uple' transmissions can 2e "alf or full duple'7 depending on
w"et"er or not t"e data transfer can 2e simultaneous5 @f data is transmitted one way at a time7 it
is referred to as "alf duple'5 @f t"e data can go 2ot" ways at t"e same time7 it is full duple'5 &f
course7 full duple' re8uires two wire conductors for t"e data lines7 one for transmission and one
for reception7 in order to transfer and receie data simultaneously5
As3n#-rono!s seria" #o))!ni#ation an% %ata 8ra)in
T"e data coming in at t"e receiing end of t"e data line in a serial data transfer is all *s
and 1sI it is difficult to ma(e sense of t"e data unless t"e sender and receier agree on a set of
rules7 a protocol7 on "ow t"e data is pac(ed7 "ow many 2its constitute a c"aracter7 and w"en t"e
data 2egins and ends5
Start an% sto+ bits
Async"ronous serial data communication is widely used for c"aracter4oriented
transmissions7 w"ile 2loc(4oriented data transfers use t"e sync"ronous met"od5 @n t"e
async"ronous met"od7 eac" c"aracter is placed 2etween start and stop 2its5 T"is is called
framing5 @n t"e data framing for async"ronous communications7 t"e data7 suc" as ASC@@
c"aracters7 are pac(ed 2etween a start 2it and a stop 2it5 T"e start 2it is always one 2it7 2ut t"e
stop 2it can 2e one or two 2its5 T"e start 2it is always a * 9low: and t"e stop 2it 9s: is 1 9"ig":5
Data trans8er rate
T"e rate of data transfer in serial data communication is stated in 2ps 92its per second:5
Anot"er widely used terminology for 2ps is 2aud rate5 +oweer7 t"e 2aud and 2ps rates are not
necessarily e8ual5 T"is is due to t"e fact t"at 2aud rate is t"e modem terminology and is defined
,-
as t"e num2er of signal c"anges per second5 @n modems a single c"ange of signal7 sometimes
transfers seeral 2its of data5 As far as t"e conductor wire is concerned7 t"e 2aud rate and 2ps are
t"e same7 and for t"is reason we use t"e 2ps and 2aud interc"angea2ly5
T"e data transfer rate of gien computer system depends on communication ports
incorporated into t"at system5 #or e'ample7 t"e early @B%PCA<T could transfer data at t"e rate
of 1** to -=** 2ps5 @n recent years7 "oweer7 Pentium 2ased PCS transfer data at rates as "ig" as
1=. 2ps5 @t must 2e noted t"at in async"ronous serial data communication7 t"e 2aud rate is
generally limited to 1**7***2ps5
RS2$2 Stan%ar%s
To allow compati2ility among data communication e8uipment made 2y arious
manufacturers7 an interfacing standard called RS232 was set 2y t"e Electronics @ndustries
Association 9E@A: in 1-=*5 @n 1-=3 it was modified and called RS232A5 RS232B A!$ RS232C
were issued in 1-=1 and 1-=-7 respectiely5 Today7 RS232 is t"e most widely used serial @A&
interfacing standard5 T"is standard is used in PCs and numerous types of e8uipment5 +oweer7
since t"e standard was set long 2efore t"e adert of t"e TTL logic family7 its input and output
oltage leels are not TTL compati2le5 @n RS2327 a 1 is represented 2y 43 to 421B7 w"ile a * 2it
is S3 to S21B7 ma(ing 43 to S3 undefined5 #or t"is reason7 to connect any RS232 to a
microcontroller system we must use oltage conerters suc" as %A<232 to conert t"e TTL
logic leels to t"e RS232 oltage leels7 and ice ersa5 %A<232 @C c"ips are commonly
referred to as line driers5
RS2$2 +ins
RS232 ca2le is commonly referred to as t"e $B421 connector5 @n la2eling7 $B421P refers
to t"e plug connector 9male: and $B421S is for t"e soc(et connector 9female:5 Since not all t"e
pins are used in PC ca2les7 @B% introduced t"e $B4- Bersion of t"e serial @A& standard7 w"ic"
uses - pins only7 as s"own in ta2le5
1 2 3 , 1
= C 0 -

9&ut of computer and e'posed end of ca2le:
1*
#ig 21H $B4- pin connector
Pin #unctionsH
Pin $escription
1 $ata carrier detect 9$C$:
2 Receied data 9R<$:
3 Transmitted data 9T<$:
, $ata terminal ready9$TR:
1 Signal ground 9X!$:
= $ata set ready 9$SR:
C Re8uest to send 9RTS:
0 Clear to send 9CTS:
- Ring indicator 9R@:
!oteH DCDF DSRF RTS and CTS are actie low pins5
T"e met"od used 2y RS4232 for communication allows for a simple connection of t"ree linesH
T'7 R'7 and Xround5 T"e t"ree essential signals for 24way RS4232
Communications are t"eseH
TXDH carries data from $TE to t"e $CE5
RXDH carries data from $CE to t"e $TE
SGH signal ground
/7*1 #onne#tion to RS2$2
T"e RS232 standard is not TTL compati2leI t"erefore7 it re8uires a line drier suc" as
t"e %A<232 c"ip to conert RS232 oltage leels to TTL leels7 and ice ersa5 T"e
interfacing of 0*11 wit" RS232 connectors ia t"e %A<232 c"ip is t"e main topic5
T"e 0*11 "as two pins t"at are used specifically for transferring and receiing data
serially5 T"ese two pins are called T<$ and R<$ and a part of t"e port 3 group 9P35* and P351:5
Pin 11 of t"e 0*11 is assigned to T<$ and pin 1* is designated as R<$5 T"ese pins are TTL
compati2leI t"erefore7 t"ey re8uire a line drier to ma(e t"em RS232 compati2le5 &ne suc" line
drier is t"e %A<232 c"ip5
%A<232 conerts from RS232 oltage leels to TTL oltage leels7 and ice ersa5
&ne adantage of t"e %A<232 c"ip is t"at it uses a S1B power source w"ic"7 is t"e same as t"e
source oltage for t"e 0*115 @n t"e ot"er words7 wit" a single S1B power supply we can power
11
2ot" t"e 0*11 and %A<2327 wit" no need for t"e power supplies t"at are common in many older
systems5 T"e %A<232 "as two sets of line driers for transferring and receiing data5 T"e line
driers used for T<$ are called T1 and T27 w"ile t"e line driers for R<$ are designated as R1
and R25 @n many applications only one of eac" is used5

#@X 22 HC&!!ECT@!X ]C to PC using %A< 232
INTERRU2TS
A single microcontroller can sere seeral deices5 T"ere are two ways to do t"atH
@!TERR6PTS or P&LL@!X5
2OLLING@
@n polling t"e microcontroller continuously monitors t"e status of a gien deiceI w"en
t"e status condition is met7 it performs t"e serice 5After t"at7 it moes on to monitor t"e ne't
deice until eac" one is sericed5 Alt"oug" polling can monitor t"e status of seeral deices and
sere eac" of t"em as certain condition are met5
INTERRU2TS@
@n t"e interrupts met"od7 w"eneer any deice needs its serice7 t"e deice notifies t"e
microcontroller 2y sending it an interrupts signal5 6pon receiing an interrupt signal7 t"e
microcontroller interrupts w"ateer it is doing and seres t"e deice5 T"e program associated
wit" t"e interrupts is called t"e interrupt serice routine 9@SR:5or interrupt "andler5
12
INTERRU2TS Es 2OLLING@
T"e adantage of interrupts is t"at t"e microcontroller can sere many deices
9not all t"e same time7 of course:I eac" deice can get t"e attention of t"e microcontroller 2ased
n t"e priority assigned to it5 T"e polling met"od cannot assign priority since it c"ec(s all deices
in round4ro2in fas"ion5 %ore importantly7 in t"e interrupt met"od t"e microcontroller can also
ignore 9mas(: a deice re8uest for serice5 T"is is again not possi2le wit" t"e polling met"od5
T"e most important reason t"at t"e interrupt met"od is prefera2le is t"at t"e polling met"od
wastes muc" of t"e microcontrollerJs time 2y polling deices t"at do not need serice5 So7 in
order to aoid tying down t"e microcontroller7 interrupts are used5
INTERRU2T SEREICE ROUTINE
#or eery interrupt7 t"ere must 2e an interrupt serice routine 9@SR:7 or interrupt
"andler5 )"en an interrupt is ino(ed7 t"e microcontroller runs t"e interrupts serice routine5 #or
eery interrupt7 t"ere is a fi'ed location in memory t"at "olds t"e address of its @SR5 T"e group
of memory location set aside to "old t"e addresses of @SR and is called t"e @nterrupt Bector
Ta2le5 S"own 2elowH
Interr!+t Ee#tor Tab"e 8or t-e /7*1@
S.No. INTERRU2T ROM LOCATION ;0EX< 2IN FLAG
CLEARING
15 Reset **** - Auto
25 E'ternal "ardware
@nterrupt *
***3 P352 912: Auto
35 Timers * interrupt
9T#*:
***B Auto
,5 E'ternal "ardware **13 P353 913: Auto
13
@nterrupt 19@!T1:
15 Timers 1 interrupt
9T#1:
**1B Auto
=5 Serial C&% 9R@
and T@:
**23 Programmer
clears it
SiA Interr!+ts in t-e /7*1@
@n reality7 only fie interrupts are aaila2le to t"e user in t"e 0*117 2ut many
manufacturersJ data s"eets state t"at t"ere are si' interrupts since t"ey include reset 5t"e si'
interrupts in t"e 0*11 are allocated as a2oe5
15 Reset5 )"en t"e reset pin is actiated7 t"e 0*11 /umps to address location ****5t"is is t"e
power4up reset5
25 Two interrupts are set aside for t"e timersH one for Timer * and one for Timer 15%emory
location ***B+ and **1B+ in t"e interrupt ector ta2le 2elong to Timer * and Timer 17
respectiely5
35 Two interrupts are set aside for "ardware e'ternal "arder interrupts5 Pin num2er 129P352:
and 139P353: in port 3 are for t"e e'ternal "ardware interrupts @!T* and
@!T17respectiely5T"ese e'ternal interrupts are also referred to as E<1 and E<25%emory
location ***3+ and **13+ in t"e interrupt ector ta2le are assigned to @!T* and @!T17
respectiely5
,5 Serial communication "as a single interrupt t"at 2elongs to 2ot" receie and transmit5 T"e
interrupt ector ta2le location **23+ 2elongs to t"is interrupt5
!otice t"at a limited num2er of 2ytes are set aside for eac" interrupt5 #or e'ample7 a
total of 0 2ytes from location ***3 to ***A is set aside for @!T*7 e'ternal "ardware interrupt
*5similarly7a total of 0 2ytes from location **B+ to **12+ is resered for T#*7 Timer * interrupt5
@f t"e serice routine for a gien interrupt is s"ort enoug" to fit in t"e memory space allocated to
it7 it is placed in t"e ector ta2leI ot"erwise7 and an L\%P instruction is placed in t"e ector ta2le
to point to t"e address of t"e @SR5 @n t"at rest of t"e 2ytes allocated to t"at interrupt are unused5
#rom t"e a2oe ta2le also notice t"at only t"ree 2ytes of R&% space are assigned to t"e
reset pin5 T"ey are R&% address location *71 and25address location 3 2elongs to e'ternal
1,
"ardware interrupt *5for t"is reason7 in our program we put t"e L\%P as t"e first instruction and
redirect t"e processor away from t"e interrupt ector ta2le7 as s"own 2elow
Ste+s in eAe#!tin an interr!+t
6pon actiation of an interrupt7 t"e microcontroller goes t"roug" t"e following steps5
15 @t finis"es t"e instruction it is e'ecuting and saes t"e address of t"e ne't instruction 9PC:
on t"e stac(5
25 @t also saes t"e current status of all t"e interrupts internally 9i5e57 not on t"e stac(:5
35 @t /umps to a fi'ed location in memory called t"e interrupt ector ta2le t"at "olds t"e
address of t"e interrupts serice routine5
,5 T"e microcontroller gets t"e address of t"e @SR from t"e interrupt ector ta2le and /umps
to it5 @t starts to e'ecute t"e interrupt serice su2routine until it reac"es t"e last instruction
of t"e su2routine7 w"ic" is RET@ 9return from interrupt:5
15 6pon e'ecuting t"e RET@ instruction7 t"e microcontroller returns to t"e place w"ere it
was interrupted5 #irst7 it gets t"e program counter 9PC: address from t"e stac( 2y popping
t"e top two 2ytes of t"e stac( into t"e PC5 T"en it starts to e'ecute from t"at address5
!otice from step 1 t"e critical role of t"e stac(5 #or t"is reason7 we must 2e careful in
manipulating t"e stac( contents in t"e @SR5 Specifically7 in t"e @SR7 /ust as in any CALL
su2routine7 t"e num2er of pus"es and pops must 2e e8ual5
Enab"in an% %isab"in an interr!+t@
6pon reset7 all interrupt are disa2led 9mas(ed:7 meaning t"at none will 2e responded to
2y t"e microcontroller if t"ey are actiated5 T"e interrupt must 2e ena2led 2y software in order
for t"e microcontroller to respond to t"em5 T"ere is a register called @E 9interrupt ena2le: t"at is
responsi2le for ena2ling 9unmas(ing: and disa2ling 9mas(ing: t"e interrupts5
!otice t"at @E is a 2it4addressa2le register5
Ste+s in enab"in an interr!+t@
To ena2le an interrupt7 we ta(e t"e following stepsH
15 Bit $C of t"e @E register 9EA: must 2e set to "ig" to allow t"e reset to ta(e effect5
@f EAK17 interrupts are ena2led and will 2e responded to if t"eir corresponding 2it in @E are "ig"5
@f EAK*7 no interrupt will 2e responded to7 een if t"e associated 2it in t"e @E register is "ig"5
Interr!+t Enab"e Reister
11
$C $= $1 $, $3 $2 $1 $*

EA @E5C disa2les all interrupts5 @f EAK*7 no interrupts is ac(nowledged5
@f EAK17 eac" interrupt source is indiidually ena2led disa2led
By setting or clearing its ena2le 2it5
44 @E5= !ot implemented7 resered for future use5P
ET2 @E51 Ena2les or disa2les Timer 2 oerflow or capture interrupt 90*12 &nly:
ES @E5, Ena2les or disa2les t"e serial port interrupts5
ET1 @E53 Ena2les or disa2les Timers 1 oerflow interrupt
E<1 @E52 Ena2les or disa2les e'ternal interrupt 15
ET* @E51 Ena2les or disa2les Timer * oerflow interrupt5
E<* @E5* Ena2les or disa2les e'ternal interrupt5
RFID READER
Actie R#@$ and Passie R#@$ tec"nologies7 w"ile often considered and ealuated
toget"er7 are fundamentally distinct tec"nologies wit" su2stantially different capa2ilities5 @n most
cases7 neit"er tec"nology proides a complete solution for supply c"ain asset management
applications5 Rat"er 7t"e most effectie and complete supply c"ain solutions leerage t"e
adantages of eac" tec"nology and com2ine t"eir use in complementary ways5 T"is need for 2ot"
tec"nologies must 2e considered 2y R#@$ standards initiaties to effectiely meet t"e
re8uirements of t"e user community5
RFID Rea%er Mo%!"e7 are also called as interrogators5 T"ey conert radio waes
Returned from t"e R#@$ tag into a form t"at can 2e passed on to Controllers7 w"ic" can
%a(e use of it5 R#@$ tags and readers "ae to 2e tuned to t"e same fre8uency in order to
Communicate5 R#@$ systems use many different fre8uencies7 2ut t"e most common and
)idely used T supported 2y our Reader is 121 .+35
1=
EA 44 ET2 ES ET1 E<1 ET* E<*

Functions
15 Supports reading of =, Bit %anc"ester Encoded cards
25 Pins for E'ternal Antenna connection
35 Serial @nterface 9TTL:
,5 )iegand @nterface also aaila2le
15 Customer application on re8uest
Te#-ni#a" Data@
#re8uencyH 121 (+3
Read RangeH up to 0 cm
Power supplyH 1B $C 9 ^ 1 V:
Current consumption ma'5 H =* mA
&perating temperatureH 42* 555 S=1_ C
Storing temperatureH 4,* 555 SC1_ C
@nterfaceH RS232 9TTL:7 )iegand and ot"ers 9on $emand:
$imensions 9l ' w ' ": H 3= ' 10 ' 1* mm
Serial @nterface #ormatH -=**Baud7 !o Parity7 0 $ata 2its7 1 Stop 2it
NoteH T"e TTL RS4232 @nterface can not 2e connected directly to a PC C&% port5
T"erefore t"e signal must 2e conerted to RS 232 leel for PC connection5
T"is #irmware "as t"e following #unctionsH
Read Tag4@$
1C
Send Tag4@$ in ASC@@ #ormat t"roug" t"e SerialA )iegand @nterface5
Se8uence starts wit" Tag @$ follows from Carriage4ReturnALine4#eed 9*$" *A":7
E'ampleH `*,12*1-30CaCRbaL#bJ
A++"i#ations@
&ur readers can 2e used for Access control7 Time T Attendance7 Bending mac"ines7
@ndustrial and ot"er applications w"ere Reading t"e data from t"e Card only is re8uired5
RFID 125 Reader Module Pin Diagram & Description
2IN NO.
SIGNAL
DESCRI2TION
Pin !o H = T'$ Transmit data 9TTL leel: output from module to serial
10
interface
Pin !o H , )iegand $ATA +@X+
9 aaila2le in )iegand :
@t will gie $ATA +@X+ signal5
Pin !o H 0 R'$ Receie data 9TTL leel: input to t"e module from
serial interface
Pin !o H 12 Bu33er 9actie low: Bu33er will 2u33 for 20* ms w"en tag is detected
Pin !o H 13 LE$ 9 actie low: LE$ will glow for 20* ms w"en tag is detected
Pin !o H 1, )iegand $ATA L&)
9 aaila2le in )iegand :
@t will gie $ATA L&) signal5
Pin
!oH2C720
Antenna @nput Loop Antenna s"ould 2e connected5
Li?!i% Cr3sta" Dis+"a3
Li8uid crystal displays 9LC$s: "ae materials w"ic" com2ine t"e properties of 2ot"
li8uids and crystals5 Rat"er t"an "aing a melting point7 t"ey "ae a temperature range wit"in
w"ic" t"e molecules are almost as mo2ile as t"ey would 2e in a li8uid7 2ut are grouped toget"er
in an ordered form similar to a crystal5An LC$ consists of two glass panels7 wit" t"e li8uid
crystal material sand witc"ed in 2etween t"em5 T"e inner surface of t"e glass plates are coated
wit" transparent electrodes w"ic" define t"e c"aracter7 sym2ols or patterns to 2e displayed
polymeric layers are present in 2etween t"e electrodes and t"e li8uid crystal7 w"ic" ma(es t"e
li8uid crystal molecules to maintain a defined orientation angle5
&ne eac" polarisers are pasted outside t"e two glass panels5 T"ese polarisers would rotate
t"e lig"t rays passing t"roug" t"em to a definite angle7 in a particular direction
)"en t"e LC$ is in t"e off state7 lig"t rays are rotated 2y t"e two polarisers and t"e
li8uid crystal7 suc" t"at t"e lig"t rays come out of t"e LC$ wit"out any orientation7 and "ence
t"e LC$ appears transparent5
)"en sufficient oltage is applied to t"e electrodes7 t"e li8uid crystal molecules would 2e
aligned in a specific direction5 T"e lig"t rays passing t"roug" t"e LC$ would 2e rotated 2y t"e
polarisers7 w"ic" would result in actiating A "ig"lig"ting t"e desired c"aracters5
1-
T"e LC$Js are lig"tweig"t wit" only a few millimeters t"ic(ness5 Since t"e LC$Js
consume less power7 t"ey are compati2le wit" low power electronic circuits7 and can 2e powered
for long durations5
T"e LC$ s doesnJt generate lig"t and so lig"t is needed to read t"e display5 By using
2ac(lig"ting7 reading is possi2le in t"e dar(5 T"e LC$Js "ae long life and a wide operating
temperature range5 C"anging t"e display si3e or t"e layout si3e is relatiely simple w"ic"
ma(es t"e LC$Js more customer friendly5
T"e LC$s used e'clusiely in watc"es7 calculators and measuring instruments are t"e
simple seen4segment displays7 "aing a limited amount of numeric data5 T"e recent adances in
tec"nology "ae resulted in 2etter legi2ility7 more information displaying capa2ility and a wider
temperature range5 T"ese "ae resulted in t"e LC$s 2eing e'tensiely used in
telecommunications and entertainment electronics5 T"e LC$s "ae een started replacing t"e
cat"ode ray tu2es 9CRTs: used for t"e display of te't and grap"ics7 and also in small TB
applications5
T"is section descri2es t"e operation modes of LC$Js t"en descri2e "ow to program and
interface an LC$ to 0*11 using Assem2ly and C5
LCD o+eration@
@n recent years t"e LC$ is finding widespread use replacing LE$ s 9seen4segment LE$
s or ot"er multi4segment LE$ s:5T"is is due to t"e following reasonsH
15 T"e declining prices of LC$s5
25 T"e a2ility to display num2ers7 c"aracters and grap"ics5 T"is is in contrast to LE$ w"ic"
is limited to num2ers and a few c"aracters5
35 @ncorporation of a refres"ing controller into t"e LC$7 t"ere 2y relieing t"e CP6 of t"e
tas( of refres"ing t"e LC$5 @n t"e case of LE$ s7 t"ey must 2e refres"ed 2y t"e CP6 to
(eep on displaying t"e data5
,5 Ease of programming for c"aracters and grap"ics5
LCD +in %es#ri+tion@
T"e LC$ discussed in t"is section "as 1, pins5 T"e function of eac"
pin is gien in ta2le5
=*
#ig 2- H LC$
TA'LE 1@ 2in %es#ri+tion 8or LCD

2in s3)bo" I>O Des#ri+tion
1 Bss 44 Xround
2 Bcc 44 S1B power supply
3 BEE 44 Power supply to
control contrast
, RS @ RSK* to select
command register
RSK1 to select
data register
1 RA) @ RA)K* for write
RA)K1 for read
= E @A& Ena2le
C $B* @A& T"e 042it data 2us
0 $B1 @A& T"e 042it data 2us
- $B2 @A& T"e 042it data 2us
1* $B3 @A& T"e 042it data 2us
11 $B, @A& T"e 042it data 2us
12 $B1 @A& T"e 042it data 2us
13 $B= @A& T"e 042it data 2us
=1
1, $BC @A& T"e 042it data 2us

T"e LC$ can display a c"aracter successfully 2y placing t"e
15 $ata in $ata Register
25 Command in Command Register of LC$
15 $ata corresponds to t"e ASC@@ alue of t"e c"aracter to 2e printed5 T"is can 2e done 2y
placing t"e ASC@@ alue on t"e LC$ $ata lines and selecting t"e $ata Register of t"e
LC$ 2y selecting t"e RS 9Register Select: pin5
25 Eac" and eery display location is accessed and controlled 2y placing respectie
command on t"e data lines and selecting t"e Command Register of LC$ 2y selecting t"e
9Register Select: RS pin5
T"e commonly used commands are s"own 2elow wit" t"eir operations5
TA'LE 2@ LCD Co))an% Co%es
Co%e ;-eA< Co))an% to LCD Instr!#tion Reister
1 Clear display screen
2 Return "ome
, $ecrement cursor
= @ncrement cursor
1 S"ift display rig"t
C S"ift display left
0 $isplay off7 cursor off
A $isplay off7 cursor on
C $isplay on7 cursor off
E $isplay on7 cursor on
# $isplay on7 cursor 2lin(ing
1* S"ift cursor position to left
1, S"ift cursor position to rig"t
10 S"ift t"e entire display to t"e left
1C S"ift t"e entire display to t"e rig"t
0* #orce cursor to 2eginning of 1
st
line
C* #orce cursor to 2eginning of 2
nd
line
30 2 lines and 1'C matri'

Uses@
=2
T"e LC$s used e'clusiely in watc"es7 calculators and measuring instruments are t"e
simple seen4segment displays7 "aing a limited amount of numeric data5 T"e recent adances in
tec"nology "ae resulted in 2etter legi2ility7 more information displaying capa2ility and a wider
temperature range5 T"ese "ae resulted in t"e LC$s 2eing e'tensiely used in
telecommunications and entertainment electronics5
So in t"is pro/ect7 t"e LC$ is used to display t"e instantaneous information5 T"e
information may 2e prompting or alerting or instructing t"e user5
LINEAR 4EY2AD
T"is section 2asically consists of a Linear .eypad5 Basically a .eypad can 2e classified into
2 categories5 &ne is Linear .eypad and t"e ot"er is %atri' (eypad5
15 %atri' .eypad5
25 Linear .eypad5
1. MatriA 4e3+a%H T"is .eypad got (eys arranged in t"e form of Rows and Columns5 T"at
is w"y t"e name %atri' .eypad5 According to t"is (eypad7 @n order to find t"e (ey 2eing
pressed t"e (eypad need to 2e scanned 2y ma(ing rows as iAp and columns as output or
ice ersa5
T"is .eypad is used in places w"ere one needs to connect more no5 &f
(eys wit" less no5 &f data lines5
2. Linear 4e3+a%@ T"is .eypad got RnJ no5 &f (eys connected to RnJ data lines of
microcontroller5
T"is .eypad is used in places w"ere one needs to connect less no5 &f
(eys5
@n t"is pro/ect7 Linear .eypad is used wit" 3 switc"es 2eing connected 2ecause t"e no5 &f
switc"es is less 9less t"an 0:5
=3
Xenerally7 in Linear .eypads one end of t"e switc" is connected to %icrocontroller
9Configured as iAp: and ot"er end of t"e switc" is connected to t"e common ground5 So
w"eneer a (ey of Linear .eypad is pressed t"e logic on t"e microcontroller pin will go
L&)5
+ere in t"is pro/ect7 a linear (eypad is used wit" switc"es connected in a serial manner5
Linear (eypad is used in t"is pro/ect 2ecause it ta(es less no5 &f port pins5 T"e Linear .eypad
wit" , .eys is s"own 2elow5
fig 3* H linear (eypad
=,
EE2ROM
EE2ROM 9also written E
2
2ROM and pronounced e4e4prom or simply e4s8uared:7 w"ic"
stands for Electrically Erasa2le 2rogramma2le Read4Only Memory7 is a type of non4olatile
memory used in computers and ot"er electronic deices to store small amounts of data t"at must
2e saed w"en power is remoed7 e5g57 cali2ration ta2les or deice configuration5
)"en larger amounts of more static data are to 2e stored 9suc" as in 6SB flas" dries:
ot"er memory types li(e flas" memory are more economical5
EEPR&%s are reali3ed as arrays of floating4gate transistors5
History
@n 1-037 Xree( American Xeorge Perlegos at @ntel deeloped t"e @ntel 201=7 w"ic" was
2uilt on earlier EPR&% tec"nology7 2ut used a t"in gate o'ide layer so t"at t"e c"ip could erase
its own 2its wit"out re8uiring a 6B source5 Perlegos and ot"ers later left @ntel to form See8
Tec"nology7 w"ic" used on4deice c"arge pumps to supply t"e "ig" oltages necessary for
programming EEPR&%s5
c1d
Functions of EEPROM
T"ere are different types of electrical interfaces to EEPR&% deices5 %ain categories of
t"ese interface types are H
Serial 2us
Parallel 2us
+ow t"e deice is operated depends on t"e electrical interface5
=1
Serial bus devices
%ost common serial interface types are SP@7 @eC and 14)ire5 T"ese t"ree interfaces
re8uire 2etween 2 and , controls signals for operation7 resulting in a memory deice in an 0 pin
9or less: pac(age5
T"e serial EEPR&% typically operates in t"ree p"asesH &P4Code P"ase7 Address P"ase
and $ata P"ase5 T"e &P4Code is usually t"e first 042its input to t"e serial input pin of t"e
EEPR&% deice 9or wit" most @eC deices7 is implicit:I followed 2y 0 to 2, 2its of addressing
depending on t"e dept" of t"e deice7 t"en data to 2e read or written5
Eac" EEPR&% deice typically "as its own set of &P4Code instructions to map to different
functions5 Some of t"e common operations on SP@ EEPR&% deices areH
)rite Ena2le 9)RE!:
)rite $isa2le 9)R$@:
Read Status Register 9R$SR:
)rite Status Register 9)RSR:
Read $ata 9REA$:
)rite $ata 9)R@TE:
&t"er operations supported 2y some EEPR&% deices areH
Program
Sector Erase
C"ip Erase commands
Parallel bus devices
Parallel EEPR&% deices typically "ae an 042it data 2us and an address 2us wide
enoug" to coer t"e complete memory5 %ost deices "ae c"ip select and write protect pins5
Some microcontrollers also "ae integrated parallel EEPR&%5
&peration of a parallel EEPR&% is simple and fast w"en compared to serial EEPR&%7 2ut t"ese
deices are larger due to t"e "ig"er pin count 9up to 32 pins or more: and "ae 2een decreasing
in popularity in faor of serial EEPR&% or #las"5
Failure modes
T"ere are two limitations of stored informationI endurance7 and data retention5
==
$uring rewrites7 t"e gate o'ide in t"e floating4gate transistors gradually accumulates trapped
electrons5 T"e electric field of t"e trapped electrons adds to t"e electrons in t"e floating gate7
lowering t"e window 2etween t"res"old oltages for 3eros s ones5 After sufficient num2er of
rewrite cycles7 t"e difference 2ecomes too small to 2e recogni3a2le7 t"e cell is stuc( in
programmed state7 and endurance failure occurs5 T"e manufacturers usually specify minimal
num2er of rewrites 2eing 1*
=
or more5
$uring storage7 t"e electrons in/ected into t"e floating gate may drift t"roug" t"e insulator7
especially at increased temperature7 and cause c"arge loss7 reerting t"e cell into erased state5
T"e manufacturers usually guarantee data retention of 1* years or more5
c2d
Related types
#las" memory is a later form of EEPR&%5 @n t"e industry7 t"ere is a conention to
resere t"e term EEPR&% to 2yte4wise writea2le memories compared to 2loc(4wise writa2le
flas" memories5 EEPR&% ta(es more die area t"an flas" memory for t"e same capacity 2ecause
eac" cell usually needs 2ot" a read7 write and erase transistor7 w"ile in flas" memory t"e erase
circuits are s"ared 2y large 2loc(s of cells 9often 112N0:5
!ewer non4olatile memory tec"nologies suc" as #eRA% and %RA% are slowly replacing
EEPR&%s in some applications7 2ut are e'pected to remain a small fraction of t"e EEPR&%
mar(et for t"e foreseea2le future5
Comparison with EPROM and EEPROM/Flash
T"e difference 2etween EPR&% and EEPR&% lies in t"e way t"at t"e memory
programs and erases5 EEPR&% can 2e programmed and erased electrically using field emission
9more commonly (nown in t"e industry as ?#owler4!ord"eim tunneling?:5
EPR&%s can`t 2e erased electrically7 and are programmed ia "ot carrier in/ection onto t"e
floating gate5 Erase is ia an ultraiolet lig"t source7 alt"oug" in practice many EPR&%s are
encapsulated in plastic t"at is opa8ue to 6B lig"t7 and are ?one4time programma2le?5
%ost !&R #las" memory is a "y2rid style>programming is t"roug" +ot carrier in/ection and
erase is t"roug" #owler4!ord"eim tunneling5
EEPR&% 92,C*2:H
=C
FEATURES
U Low power C%&S
> Actie current less t"an 2 mA
> Stand2y current less t"an 0 mA
U +ardware writes protection
> )rite control pin
U @nternally organi3ed as 21= ' 0
U Two4wire serial interface
> Bidirectional data transfer protocol
U 04Byte page4write mode
> %inimi3ed total write time per 2yte
U Automatic word address incrementing
> Se8uential register read
U Self4timed write cycle
> %a'imum write cycle time of 1* ms
U ,** .+3 Compati2ility
EnduranceH 17 ***7*** cycles per 2yte
U 04pin P$@P7 TSS&P7 %S&P or S&@C pac(ages
U #iltered inputs for noise suppression
OEEREIE=
T"e @S2,C*2 is a low cost 27*,042it serial EEPR&%5 @t is fa2ricated using ISSIJs adanced
C%&S EEPR&% tec"nology and operates from a single supply5 T"e @S2,C*2 is internally
organi3ed as a 21= ' 0 memory 2an(5 T"e @S2,C*2 features a serial interface and software
protocol allowing operation on a simple 24wire 2us5 6p to eig"t @S2,C*2s may 2e connected to
t"e 24wire 2us 2y programming t"e A*7 A17 and A2 inputs5
2IN CONFIGURATION
=0
2IN DESCRI2TIONS
A*4A2 Address @nputs
S$A Serial $ata @A&
SCL Serial Cloc( @nput
)C )rite Control @nput
BCC Power
X!$ Xround
A7F A1F an% A2 4 T"e address inputs are used to set t"e least significant t"ree 2its of t"e slae
address5 T"ese inputs may 2e tied +@X+ or L&)7 or t"ey may 2e actiely drien5 T"ese inputs
allow up to eig"t @S2,C*2 deices to 2e connected toget"er on t"e 2us5 )"en left floating7 A*7
A1 and A2 are pulled to ground5 T"e default alues are 3eros5
Seria" Data ;SDA< 4 T"e S$A pin is a 2idirectional pin used to transfer data into and out of t"e
deice5 $ata may c"ange only w"en SCL is L&)5 @t is an open4drain output7 and may 2e wire
&Red wit" any num2er of open4drain or open4collector outputs5
Seria" C"o#( ;SCL< 4 T"e SCL input is used to cloc( all data into and out of t"e deice5 @n t"e
)R@TE mode7 data must remain sta2le w"en SCL is +@X+5 @n t"e REA$ mode7 data is cloc(ed
out on t"e falling edge of SCL5
=rite Contro" ;)C< 4 T"e )rite Control input is used to disa2le any attempt to write to t"e
memory5 )"en +@X+7 t"e memory is protectedI w"en L&)7 t"e write function is normal5 T"e
part can 2e read independent of t"e state of )C pin5 )"en not connected7 t"is pin will 2e pulled
L&)5
=-
ENDURANCE AND DATA RETENTION
T"e @S2,C*2 is designed for applications re8uiring "ig" endurance write cycles and unlimited
read cycles5 @t proides 1* years of secure data retention7 wit" or wit"out power applied7 after t"e
e'ecution of 17***7*** write cycles5
A22LICATIONS
T"e @S2,C*2 is ideal for "ig" olume applications re8uiring low power and low density storage5
T"is deice uses a low4cost7 space4saing 04pin plastic pac(age5 Candidate applications include
ro2otics7 alarm deices7 electronic loc(s7 meters and instrumentation5
GENERAL DESCRI2TION
T"e @S2,C*2 features a SER@AL communication7 and supports 2idirectional data transmission
protocol allowing operation on a simple two4wire 2us 2etween t"e different deices connected
somew"ere on t"e system 2us5 T"e two4wire 2us is defined as a serial data line 9S$A:7 and a
serial cloc( line 9SCL:5
T"e protocol defines any deice t"at sends data onto t"e S$A 2us as a transmitter7 and t"e
receiing deice as a receier5 T"e deice controlling t"e data transmission is named %ASTER
deice7 and t"e controlled deice is named SLABE deice5 @n all cases7 t"e @S2,C*2 will 2e a
slae deice7 since it neer initiates any data transfers5 6p to eig"t @S2,C*2 can 2e connected to
t"e 2us5 $eice`s p"ysical address inputs A*4A2 must 2e connected to eit"er BCC or X!$5 )"en
left floating7 A*7 A1 and A2 are pulled to ground5 T"e default alues are 3eros5
#ollowing a START condition7 t"e %ASTER 9transmitter: deice must initiate t"e F$eice
Addressing ByteG including deice type identifier7 deice address7 and a read or write operation
to select a slae deice 9receier: connected to t"e system 2us5 T"e receier will t"en respond
wit" an Ac(nowledge 2y pulling t"e S$A line L&)5 T"e Ac(nowledge is used to indicate
C*
successful data transfers5 T"e transmitting deice will release t"e data 2us 9S$A goes +@X+:
after transmitting eig"t 2its 9one data 2it is transferred at t"e falling edge of eac" cloc( cycle:5
$uring t"e nint" cloc( cycle7 t"e receier will pull t"e S$A line L&) to ac(nowledge t"e
transmitter t"at it receied t"e eig"t 2its of data5
DEEICE O2ERATION
START an% STO2 Con%itions
Bot" S$A and SCL lines remain +@X+ w"en t"e S$A 2us is not 2usy5 A +@X+4to4L&)
transition of S$A line7 w"ile SCL is +@X+7 is defined as t"e START condition5 A L&) to4 +ig"
transition of S$A line7 w"ile SCL is +@X+7 is defined as t"e ST&P condition5
Data Ea"i%it3 2roto#o"
&ne data 2it is transferred during eac" cloc( cycle5 T"e data on t"e S$A line must remain sta2le
during t"e +@X+ period of t"e cloc( cycle7 2ecause c"anges on S$A line during t"e SCL +@X+
period will 2e interpreted as START or ST&P control signals5
C1
Devi#e A%%ressin '3te De8initions
T"e most significant four 2its of $eice Addressing Byte 9Bit C to Bit ,: are defined as t"e
deice type identifier5 #or @S2,C*27 t"is is fi'ed as 1*1*5 T"e ne't t"ree significant address 2its
9Bit 3 to Bit 1: address a particular deice5 6p to eig"t @S2,C*2 deices can 2e connected on t"e
2us5
T"ese eig"t addresses are defined 2y t"e state of t"e A*7 A17 and A2 inputs5 T"e last 2it Bit *
defines t"e write or read operation to 2e performed5 )"en set to F1G7 a REA$ operation is
selectedI w"en set to F*G a )R@TE operation is selected5
=RITE O2ERATION
'3te =rite
#or a )R@TE operation7 t"e @S2,C*2 re8uires anot"er 042it data word address following t"e
$eice Addressing Byte and Ac(nowledgement5 T"is data word address proides access to any
one of t"e 21= data words of deice`s memory array5
6pon receipt of t"e data word address7 t"e @S2,C*2 responds wit" an Ac(nowledge on S$A7 and
waits for t"e ne't 042it data word7 t"en again responding wit" an Ac(nowledge5 T"e master
deice terminates t"e Byte )rite &peration 2y generating a ST&P conditionI afterward t"e
@S2,C*2 2egins t"e internal )R@TE cycle to t"e nonolatile memory array5 Refer to )rite Cycle
Timing5 All inputs are disa2led during t"is write cycle and t"e deice will not respond to any
re8uests from t"e master5
C2
2ae =rite
T"e @S2,C*2 is capa2le of 042yte page4 )R@TE operation5 A page4)R@TE is initiated in t"e
same manner as a 2yte write7 2ut instead of terminating t"e internal write cycle after t"e first data
word is transferred7 t"e master deice can transmit up to C more words5 After t"e receipt of eac"
data word7 t"e @S2,C*2 responds immediately wit" an Ac(nowledge on S$A line7 and t"e four
lower order data word address 2its are internally incremented 2y one w"ile t"e four "ig"er order
2its of t"e data word address remain constant5 @f t"e master deice s"ould transmit more t"an 0
words7 prior to issuing t"e ST&P condition7 t"e address counter will Froll oer7G and t"e
preiously written data will 2e oerwritten5 All inputs are disa2led until completion of t"e
internal )R@TE cycle5
A#(no1"e%e 2o""in
&nce t"e internal write cycle "as started and t"e @S2,C*2 inputs are disa2led7 ac(nowledge
polling can 2e initiated5 T"is inoles sending a start condition followed 2y t"e $eice
Addressing Byte5 T"e readAwrite 2it is representation of t"e operation desired5 &nly if t"e
internal write cycle "as 2een completed will t"e @S2,C*2 respond wit" ac(nowledge on t"e S$A
2us allowing t"e read or write se8uence to continue5
READ O2ERATION
REA$ operations are initiated in t"e same manner as )R@TE operations7 e'cept t"at t"e
readAwrite 2it of t"e deice addressing 2yte is set to F1G5 T"ere are t"ree REA$ operation
optionsH current address read7 random address read and se8uential read5
C!rrent A%%ress Rea%
T"e @S2,C*2 contains an internal address counter w"ic" maintains t"e address of t"e last data
word accessed7 incremented 2y one5 #or e'ample7 if t"e preious operation eit"er a read or write
operation addressed to t"e address location n7 t"e internal address counter would increment to
C3
address location nS15 )"en t"e @S2,C*2 receies t"e $eice Addressing Byte wit" a REA$
operation 9readAwrite 2it set to F1G:7 it will respond an Ac(nowledge and transmit t"e 042it data
word stored at address location nS15 @f t"e Current Address REA$ operation only accesses a
single 2yte of data7 t"e master deice terminates t"e Current Address REA$ operation 2y pulling
Ac(nowledge +@X+ 9lac( of Ac(nowledge: indicating t"e last data word to 2e read7 followed 2y
a ST&P condition5
Ran%o) A##ess Rea%
Random Address REA$ operation allows t"e master deice to access any memory location in a
random fas"ion5 T"is operation inoles a two4step process5 #irst7 t"e master deice generates a
START condition and initiates $eice Addressing Byte wit" a dummy )R@TE operation
9readAwrite 2it sets to F*G:7 followed 2y t"e address of t"e data word t"e master deice is to
REA$5 T"is procedure stores t"e desired address of data word to t"e internal address counter of
t"e @S2,C*25
After t"e data word address Ac(nowledge is receied 2y t"e master deice7 t"e master deice
now initiates a C6RRE!T A$$RESS REA$ 2y sending $eice Addressing Byte wit" a REA$
operation 9readAwrite 2it sets to F1G:5 T"e @S2,C*2 responds wit" an Ac(nowledge and transmits
t"e eig"t data 2its stored at t"e address location w"ere t"e master deice is to REA$5 At t"is
point7 t"e master deice terminates t"e operation 2y pulling Ac(nowledge +@X+ 9lac( of
Ac(nowledge: indicating t"e last data word to 2e read7 followed 2y a ST&P condition5
C,
Se?!entia" Rea%
Se8uential Reads can 2e initiated as eit"er a Current Address Read or Random Address Read5
T"e first data word is transmitted as wit" t"e ot"er 2yte read modes7 t"e master deice now
responds wit" an AC.nowledge indicating t"at it re8uires additional data from t"e @S2,C*25 T"e
@S2,C*2 continues to output data for eac" AC.nowledge receied5 T"e master deice terminates
t"e se8uential REA$ operation 2y pulling AC.nowledge +@X+ 9lac( of AC.nowledge:
indicating t"e last data word to 2e read7 followed 2y a ST&P condition5
T"e data output is se8uentialI wit" t"e data from address n followed 2y t"e date from address
nS1 555 etc5 T"e address4counter increments 2y one automatically7 allowing t"e entire memory
contents to 2e serially read during se8uential read operation5 )"en t"e memory address
2oundary 9address 211: is reac"ed7 t"e address counter Frolls oerG to address *7 and t"e
@S2,C*2 continues to output data for eac" Ac(nowledge receied5
C1
'UIIER
T"e ?Pie3oelectric sound components? introduced "erein operate on an innoatie principle
utili3ing natural oscillation of pie3oelectric ceramics5 T"ese 2u33ers are offered in lig"tweig"t
compact si3es from t"e smallest diameter of 12mm to large Pie3o electric sounders5 Today7
pie3oelectric sound components are used in many ways suc" as "ome appliances7 &A e8uipment7
audio e8uipment telep"ones7 etc5 And t"ey are applied widely7 for e'ample7 in alarms7 spea(ers7
telep"one ringers7 receiers7 transmitters7 2eep sounds7 etc5
FIG@ T3+es o8 '!55ers
C=
Os#i""atin S3ste)@
Basically7 t"e sound source of a pie3oelectric sound component is a pie3oelectric
diap"ragm5 A pie3oelectric diap"ragm consists of a pie3oelectric ceramic plate w"ic" "as
electrodes on 2ot" sides and a metal plate 92rass or stainless steel7 etc5:5 A pie3oelectric ceramic
plate is attac"ed to a metal plate wit" ad"esies5
#ig5 2 s"ows t"e oscillating system of a pie3oelectric diap"ragm5 Applying $5C5 oltage
2etween electrodes of a pie3oelectric diap"ragm causes mec"anical distortion due to t"e
pie3oelectric effect5 #or a miss"aped pie3oelectric element7 t"e distortion of t"e pie3oelectric
element e'pands in a radial direction5 And t"e pie3oelectric diap"ragm 2ends toward t"e
direction s"own in #ig52 9a:5
T"e metal plate 2onded to t"e pie3oelectric element does not e'pand5 Conersely7 w"en
t"e pie3oelectric element s"rin(s7 t"e pie3oelectric diap"ragm 2ends in t"e direction s"own in
#ig52 92:5 T"us7 w"en AC oltage is applied across electrodes7 t"e 2ending s"own in #ig52 9a:
and #ig52 92: is repeated as s"own in #ig52 9c:7 producing sound waes in t"e air5
DESIGN 2ROCEDURES@
@n general7 man`s audi2le fre8uency range is a2out 2* +3 to 2*(+35 #re8uency ranges of
2(+3 to ,(+3 are most easily "eard5 #or t"is reason7 most pie3oelectric sound components are
used in t"is fre8uency range7 and t"e resonant fre8uency 9f*: is generally selected in t"e same
CC
range too5 As s"own in #ig5 37 t"e resonant fre8uency depends on met"ods used to support t"e
pie3oelectric diap"ragm5 @f pie3oelectric diap"ragms are of t"e same s"ape7 t"eir alues will
2ecome smaller in t"e order of 9a:7 92: and 9c:5
@n general7 t"e pie3oelectric diap"ragm is installed in a caity to produce "ig" sound
pressure5 T"e resonant fre8uency 9fca: of t"e caity in is o2tained from #ormula 91:
9+elm"olt3`s #ormula:5 Since t"e pie3oelectric diap"ragm and caity "ae proper resonant
fre8uencies7 9f*: and 9fca: respectiely7 sound pressure in specific fre8uencies can 2e increased
and a specific 2andwidt" can 2e proided 2y controlling 2ot" positions5
C0
Cir#!it Des#ri+tion

T"is section gies an oeriew of t"e w"ole circuitry and "ardware inoled in t"e
pro/ect5 T"e main aim of t"is pro/ect is to implement t"e stoc( updating T detecting t"e e'piry
date for p"armacy5 T"e purpose of t"e pro/ect is to (now t"e details of t"e stoc( and also t"e
e'piry date for t"e medicines in t"e p"armacy5
@n t"is pro/ect we are giing power supply to all units7 it 2asically consists of a
Transformer to step down t"e 23*B ac to 12B ac followed 2y diodes5 +ere diodes are used to
rectify t"e ac to dc5 After rectification t"e o2tained rippled dc is filtered using a capacitor #ilter5
A positie oltage regulator is used to regulate t"e o2tained dc oltage5
T"e o2/ectie of t"is pro/ect is to proide additional security to t"e AT% using R#@$5 T"e
Readers w"ic" reads t"e information from t"e cards are called Card Readers5 )e can use R#@$
Reader to read t"e data from t"e R#@$ card5
T"e pro/ect 2asically employs a microcontroller as a "eart of our pro/ect
w"ic" is interfaced wit" R#@$ Card Reader to get t"e data regarding t"e card 2eing read 2y t"e
Card Reader5 @f aut"entication results in Success it prompts for P@! num2er to 2e c"ec(ed wit"
pre4assigned P@! and transaction results if and only if P@! num2er matc" occurs5
T"e R#@$ card stores t"e secret information of t"e concerned
person5 )"eneer t"e card is 2eing inserted into t"e AT% mac"ine t"en t"e respectie Card
Reader reads t"e card and t"en communicates wit" t"e controller5 T"e system as(s for t"e P@!
9Personal @dentification !um2er: code w"ic" "as already gien to t"e concerned person5 )"en
t"e P@! code is entered t"roug" t"e (eypad t"en t"e transaction will 2e occurred if and only if
t"e P@! code matc"es wit" pre4stored P@! num2er5
C-
S&#T)ARE Components
A'OUT SOFT=ARE
Software used isH
P.eil software for C programming
PE'press PCB for lay out design
PE'press SC+ for sc"ematic design
4EIL JEision$
)"at`s !ew in QBision3Z
QBision3 adds many new features to t"e Editor li(e Te't Templates7 ;uic( #unction !aigation7
and Synta' Coloring wit" 2race "ig" lig"ting Configuration )i3ard for dialog 2ased startup and
de2ugger setup5 QBision3 is fully compati2le to QBision2 and can 2e used in parallel wit"
QBision25
=-at is JEision$K
QBision3 is an @$E 9@ntegrated $eelopment Enironment: t"at "elps you write7 compile7 and
de2ug em2edded programs5 @t encapsulates t"e following componentsH
A pro/ect manager5
A ma(e facility5
Tool configuration5
Editor5
A powerful de2ugger5
0*
EA+ress 2C'
E'press PCB is a Circuit $esign Software and PCB manufacturing serice5 &ne
can learn almost eeryt"ing you need to (now a2out E'press PCB from t"e "elp topics included
wit" t"e programs gien5
$etailsH
E'press PCB7 Bersion 15=5*
EA+ress SC0
T"e E'press SC+ sc"ematic design program is ery easy to use5 T"is software
ena2les t"e user to draw t"e Sc"ematics wit" drag and drop options5
A ;uic( Start Xuide is proided 2y w"ic" t"e user can learn "ow to use it5
$etailsH
E'press SC+7 Bersion 15=5*
EM'EDDED C@
T"e programming Language used "ere in t"is pro/ect is an E)be%%e% C
Language5 T"is Em2edded C Language is different from t"e generic C language in few t"ings
li(e
a: $ata types
2: Access oer t"e arc"itecture addresses5
T"e Em2edded C Programming Language forms t"e user friendly language wit" access oer Port
addresses7 S#R Register addresses etc5
Em2edded C $ata typesH
Data T3+es Si5e in 'its Data Rane>Usae
unsigned c"ar 042it *4211
signed c"ar 042it 4120 to S12C
unsigned int 1=42it * to =1131
signed int 1=42it 4327C=0 to S327C=C
s2it 142it S#R 2it addressa2le only
2it 142it RA% 2it addressa2le
only
01
sfr 042it RA% addresses 0*4##+
only
Signed c"arH
o 6sed to represent t"e M or S alues5
o As a result7 we "ae only C 2its for t"e magnitude of t"e signed num2er7 giing us alues
from 4120 to S12C5
SOFT=ARE
JEision$
QBision3 is an @$E 9@ntegrated $eelopment Enironment: t"at "elps you write7 compile7 and
de2ug em2edded programs5 @t encapsulates t"e following componentsH
A pro/ect manager5
A ma(e facility5
Tool configuration5
Editor5
A powerful de2ugger5
02
To "elp you get started7 seeral e'ample programs 9located in t"e LC*1LEAa)+"es7
LC2*1LEAa)+"es7 LC1,,LEAa)+"es7 and LARML...LEAa)+"es: are proided5
0ELLO is a simple program t"at prints t"e string ?+ello )orld? using t"e Serial
@nterface5
'!i"%in an A++"i#ation in JEision2
To 2uild 9compile7 assem2le7 and lin(: an application in QBision27 you mustH
15 Select Pro/ect 4 9for e'ample7 1,,LEXAM2LESL0ELLOL0ELLO.UE2:5
25 Select Pro/ect 4 Re2uild all target files or Build target5
QBision2 compiles7 assem2les7 and lin(s t"e files in your pro/ect5
Creatin Yo!r O1n A++"i#ation in JEision2
To #reate a ne1 +roDe#t in JEision2F 3o! )!stH
15 Select Pro/ect 4 !ew Pro/ect5
25 Select a directory and enter t"e name of t"e pro/ect file5
35 Select Pro/ect 4 Select $eice and select an 0*117 2117 or C1='AST1* deice from t"e
$eice $ata2asef5
,5 Create source files to add to t"e pro/ect5
15 Select Pro/ect 4 Targets7 Xroups7 #iles7 AddA#iles7 select Source Xroup17 and add t"e
source files to t"e pro/ect5
=5 Select Pro/ect 4 &ptions and set t"e tool options5 !ote w"en you select t"e target deice
from t"e $eice $ata2asef all special options are set automatically5 Dou typically only
need to configure t"e memory map of your target "ardware5 $efault memory model
settings are optimal for most applications5
C5 Select Pro/ect 4 Re2uild all target files or Build target5
Deb!in an A++"i#ation in JEision2
To de2ug an application created using QBision27 you mustH
15 Select $e2ug 4 StartAStop $e2ug Session5
25 6se t"e Step tool2ar 2uttons to single4step t"roug" your program5 Dou may enter GF
)ain in t"e &utput )indow to e'ecute to t"e main C function5
35 &pen t"e Serial )indow using t"e Seria" M1 2utton on t"e tool2ar5
03
$e2ug your program using standard options li(e Step7 Xo7 Brea(7 and so on5
Startin JEision2 an% #reatin a 2roDe#t
QBision2 is a standard )indows application and started 2y clic(ing on t"e program icon5 To
create a new pro/ect file select from t"e QBision2 menu
2roDe#t M !ew Pro/ectg5 T"is opens a standard )indows dialog t"at as(s you for t"e new
pro/ect file name5
)e suggest t"at you use a separate folder for eac" pro/ect5 Dou can simply use t"e icon Create
!ew #older in t"is dialog to get a new empty folder5 T"en select t"is folder and enter t"e file
name for t"e new pro/ect7 i5e5 Pro/ect15
QBision2 creates a new pro/ect file wit" t"e name PR&\ECT156B2 w"ic" contains a default
target and file group name5 Dou can see t"ese names in t"e Pro/ect
=in%o1 H Fi"es.
!ow use from t"e menu Pro/ect M Select $eice for Target and select a CP6 for your pro/ect5
T"e Select $eice dialog 2o' s"ows t"e QBision2 deice data2ase5 \ust select t"e
microcontroller you use5 )e are using for our e'amples t"e P"ilips 0*C11R$S CP65 T"is
selection sets necessary tool options for t"e 0*C11R$S deice and simplifies in t"is way t"e tool
Configuration5
'!i"%in 2roDe#ts an% Creatin a 0EX Fi"es
Typical7 t"e tool settings under &ptions M Target are all you need to start a new
application5 Dou may translate all source files and line t"e application wit" a clic( on t"e Build
Target tool2ar icon5 )"en you 2uild an application wit" synta' errors7 QBision2 will display
errors and warning messages in t"e &utput
)indow M Build page5 A dou2le clic( on a message line opens t"e source file on t"e correct
location in a QBision2 editor window5
&nce you "ae successfully generated your application you can start de2ugging5
After you "ae tested your application7 it is re8uired to create an @ntel +E< file to
download t"e software into an EPR&% programmer or simulator5 QBision2 creates +E< files
wit" eac" 2uild process w"en Create +E< files under &ptions for Target M &utput is ena2led5
Dou may start your PR&% programming utility after t"e ma(e process w"en you specify t"e
program under t"e option Run 6ser Program [15
0,
C2U Si)!"ation
QBision2 simulates up to 1= %2ytes of memory from w"ic" areas can 2e mapped for read7 write7
or code e'ecution access5 T"e QBision2 simulator traps and reports illegal memory accesses
2eing done5
@n addition to memory mapping7 t"e simulator also proides support for t"e integrated
perip"erals of t"e arious 0*11 deriaties5 T"e on4c"ip perip"erals of t"e CP6 you "ae
selected are configured from t"e $eice
Database se"e#tion
Dou "ae made w"en you create your pro/ect target5 Refer to page 10 for more @nformation a2out
selecting a deice5 Dou may select and display t"e on4c"ip perip"eral components using t"e
$e2ug menu5 Dou can also c"ange t"e aspects of eac" perip"eral using t"e controls in t"e dialog
2o'es5
Start Deb!in
Dou start t"e de2ug mode of QBision2 wit" t"e $e2ug M StartAStop $e2ug Session command5
$epending on t"e &ptions for Target M $e2ug Configuration7 QBision2 will load t"e application
program and run t"e startup code QBision2 saes t"e editor screen layout and restores t"e screen
layout of t"e last de2ug session5 @f t"e program e'ecution stops7 QBision2 opens an editor
window wit" t"e source te't or s"ows CP6 instructions in t"e disassem2ly window5 T"e ne't
e'ecuta2le statement is mar(ed wit" a yellow arrow5 $uring de2ugging7 most editor features are
still aaila2le5
#or e'ample7 you can use t"e find command or correct program errors5 Program source
te't of your application is s"own in t"e same windows5 T"e QBision2 de2ug mode differs from
t"e edit mode in t"e following aspectsH
h T"e F$e2ug %enu and $e2ug CommandsG descri2ed on page 20 are Aaila2le5 T"e additional
de2ug windows are discussed in t"e following5
h T"e pro/ect structure or tool parameters cannot 2e modified5 All 2uild Commands are disa2led5
Disasse)b"3 =in%o1
T"e $isassem2ly window s"ows your target program as mi'ed source and assem2ly
program or /ust assem2ly code5 A trace "istory of preiously e'ecuted instructions may 2e
01
displayed wit" $e2ug M Biew Trace Records5 To ena2le t"e trace "istory7 set $e2ug M
Ena2leA$isa2le Trace Recording5
@f you select t"e $isassem2ly )indow as t"e actie window all program step commands
wor( on CP6 instruction leel rat"er t"an program source lines5 Dou can select a te't line and set
or modify code 2rea(points using tool2ar 2uttons or t"e conte't menu commands5
Dou may use t"e dialog $e2ug M @nline Assem2lyg to modify t"e CP6 instructions5
T"at allows you to correct mista(es or to ma(e temporary c"anges to t"e target program you are
de2ugging5
SOURCE CODE
1. Clic( on t"e .eil uBision @con on $es(top
2. T"e following fig will appear
#ig 32H pro/ect
$. Clic( on t"e Pro/ect menu from t"e title 2ar
&. T"en Clic( on !ew Pro/ect
0=
#ig 33H new pro/ect
*. Sae t"e Pro/ect 2y typing suita2le pro/ect name wit" no e'tension in u r own folder
sited in eit"er CHi or $Hi

,. T"en Clic( on save 2utton a2oe5
.. Select t"e component for u r pro/ect5 i5e5 Atmelgg
/. Clic( on t"e S Sym2ol 2eside of Atmel
0C
#ig 3, H select target deice
6. Select AT0-C11 as s"own 2elow
#ig 31H select deice foer target
17. T"en Clic( on F&.G
11. T"e #ollowing fig will appear
00
#ig 3=H Copy 0*11 startup code
12. T"en Clic( eit"er DES or !&gggmostly F!&G
1$. !ow your pro/ect is ready to 6SE
1&. !ow dou2le clic( on t"e Target17 you would get anot"er option FSource group 1G as
s"own in ne't page5
#ig 3CH Source group 1
1*. Clic( on t"e file option from menu 2ar and select FnewG
0-
#ig 30 new file
1,. T"e ne't screen will 2e as s"own in ne't page7 and /ust ma'imi3e it 2y dou2le
clic(ing on its 2lue 2oarder5
#ig 3-H &pened new file
1.. !ow start writing program in eit"er in FCG or FAS%G
1/. #or a program written in Assem2ly7 t"en sae it wit" e'tension F5 asmG and for FCG
2ased program sae it wit" e'tension F 5CG
-*
#ig ,*H #ile Sae
16. !ow rig"t clic( on Source group 1 and clic( on FA%% 8i"es to Gro!+ So!r#eG
#ig ,1H Add files to t"e source group
27. !ow you will get anot"er window7 on w"ic" 2y default FCG files will appear5
-1
#ig ,2H Adding files to t"e source group
21. !ow select as per your file e'tension gien w"ile saing t"e file
22. Clic( only one time on option FADDG
2$. !ow Press function (ey #C to compile5 Any error will appear if so "appen5
#ig ,3 Compilation
2&. @f t"e file contains no error7 t"en press ControlS#1 simultaneously5
2*. T"e new window is as follows
-2
#ig ,,H 2uilding
2,. T"en Clic( F&.G
2.. !ow Clic( on t"e Perip"erals from menu 2ar7 and c"ec( your re8uired port as s"own
in fig 2elow
#ig ,1 H Selecting t"e Ports to 2e isuali3ed
2/. $rag t"e port a side and clic( in t"e program file5
-3
#ig ,=Hstart de2ugging
26. !ow (eep Pressing function (ey F#11G slowly and o2sere5
$7. Dou are running your program successfully5
E)be%%e% C@
=-at is an e)be%%e% s3ste)K
An em2edded system is an application t"at contains at least one programma2le computer
and w"ic" is used 2y indiiduals w"o are7 in t"e main7 unaware t"at t"e system is computer4
2ased5
=-i#- +rora))in "an!ae s-o!"% 3o! !seK
+aing decided to use an 0*11 processor as t"e 2asis of your em2edded system7 t"e ne't (ey
decision t"at needs to 2e made is t"e c"oice of programming language5 @n order to identify a
suita2le language for em2edded systems7 we mig"t 2egin 2y ma(ing t"e following o2serationsH
-,
Computers 9suc" as microcontroller7 microprocessor or $SP c"ips: only accept
instructions in Rmac"ine codeJ 9Ro2/ect codesJ:5 %ac"ine code is7 2y definition7 in t"e
language of t"e computer7 rat"er t"an t"at of t"e programmer5 @nterpretation of t"e code
2y t"e programmer is difficult and error prone5
All software7 w"et"er in assem2ly7 C7 CSS7 \aa or Ada must ultimately 2e translated into
mac"ine code in order to 2e e'ecuted 2y t"e computer5
Em2edded processors M li(e t"e 0*11 M "ae limited processor power and ery limited
memory aaila2leH t"e language used must 2e efficient5
T"e language c"osen s"ould 2e in common use5
S!))ar3 o8 C "an!ae Feat!res@
@t is Rmid4leelJ7 wit" R"ig"4leelJ features 9suc" as support for functions and modules:7 and
Rlow4leelJ features 9suc" as good access to "ardware ia pointers:5
@t is ery efficient5
@t is popular and well understood5
Een des(top deelopers w"o "ae used only \aa or CSS can soon understand C synta'5
Xood7 well4proen compilers are aaila2le for eery em2edded processor 9042it to 3242it
or more:5
'asi# C +rora) str!#t!re@
AA4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
AABasic 2lan( C program t"at does not"ing
AA @ncludes
AA4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
[include <reg115"> AA S#R declarations
Boid main 9oid:
)"ile 91:I
-1
Body of t"e loop AA @nfinite loop
!
! AA matc" t"e 2races
CONCLUSION
T"e pro/ect FFISCAL ACCESS SYSTEM USING RFIDN "as 2een successfully designed and
tested5 @ntegrating features of all t"e "ardware components used "ae deeloped it5 Presence of
eery module "as 2een reasoned out and placed carefully t"us contri2uting to t"e 2est wor(ing of
t"e unit5
Secondly7 using "ig"ly adanced @CJs and wit" t"e "elp of growing tec"nology t"e
pro/ect "as 2een successfully implemented
-=
REFERENCES
0*114%@CR&C&!TR&LLER A!$ E%BE$$E$ SDSTE%S5
%o"d5 %a3idi5
T"e 0*11 %icro controller Arc"itecture7 Programming T Applications
B4ennet- O.A3a"a
#undamentals &f %icro processors and %icro computers
B'.Ra)
%icro processor Arc"itecture7 Programming T Applications
BRa)es- S. Gaon(ar
Electronic Components
4D.E. 2rasa%
-C

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