BK

TP.HCM
2010
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Chapter 1
INTERGRATED-CIRCUIT
LOGIC FAMILIES
Faculty of Computer Science and Engineering
Department of Computer Engineering
2010, CE Department
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Outline
Digital IC Terminology
TTL Logic Family
MOS Technology
Open-Collector/Open-Drain Ouputs
Tristate (Three-State) Logic Outputs
IC Interfacing
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Digital IC Terminology
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Current and Voltage Parameters
HIGH logic:1 ; LOWlogic :0
V
IH
(min) High Level Input Voltage
V
IL
(max) Low Level Input Voltage
V
OH
(min) High Level Output Voltage
V
OL
(max) Low Level Output Voltage
I
IH
High Level Input Current
I
IL
Low Level Input Current
I
OH
High Level Output Current
I
OL
Low Level Output Current
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Fan-out
Loading factor
The maximum number of logic inputs that an
oputput can drive reliably.
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Propagation Delays
t
PLH
: Delay time in going from 0 1 (LOW HIGH)
t
PHL
: Delay time in going from 1 0 (HIGH LOW)
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Power Requirement
TTL devices: VCC
MOS devices: VDD
I
CCH
: all outputs are HIGH
I
CCL
: all outputs are LOW
I
CC(avg)
=(I
CCH
+I
CCL
)/2
P
D(avg)
=I
cc(avg)
.V
cc
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Speed-Power Product
Digital IC families desire:
Higher speed (shorter gate propagation delay) : S
Lower power dissipation: P
Measuring and comparing the overall performance of
an IC.
Speed-power product =S * P
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Noise Immunity
high-state noise margin
V
NH
= V
OH
(min) V
IH
(min)
low-state noise margin
V
NL
= V
IL
(max) V
OL
(max)
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Current-Sourcing Current-Sinking Logic
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IC Packages
DIP (dual-in-line package)
Lead pitch: spacing between pins (100 mils)
Surface-mount
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TTL Logic Family
TTL inputs: multiple-emitter
TTL outputs: totem-pole
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TTL NAND Gate
LOW State
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TTL NAND Gate
HIGH State
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TTL NAND Gate
Current-Sinking and Current Sourcing
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TTL NAND Gate
Totem-Pole Output
Advantage
Lowpower dissipation
Fast rise-time
Disadvantage
Large current spike during switching formLOWto HIGH
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TTL NOR Gate
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TTL Series
Standard TTL, 74
Schottky TTL, 74S
Low-Power Schottky TTL, 74LS (LS-TTL)
Advanced Schottky TTL, 74AS (AS-TTL)
Advanced Low-Power Schottky TTL, 74ALS
74F-Fast TTL
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TTL Data Sheets
Supply Voltage Temperature Range
Voltage Levels
V
IL
, V
OL
, V
OH
, V
IH
V
NL
, V
NH
Maximum Voltage Ratings
Power Dissipation
I
CCH
, I
CCL
I
CC
(avg) P
D
(avg)
Propagation Delays
t
PLH
, t
PHL
t
pd
(avg)
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TTL Data Sheets
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TTL Data Sheets
Loading and Fan-out
fan-out(LOW)
fan-out(HIGH)
Example: In datasheet of 74ALS00
I
OL
(max) =8 mA, I
IL
(max) =0.1 mA
I
OH
(max) =0.4 mA =400 A, I
OL
=20 A
fan-out(LOW) =80, fan-out(HIGH) =20
(max)
(max)
IL
OL
I
I
=
(max)
(max)
IH
OH
I
I
=
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TTL Data Sheets
Loading and Fan-out
I
OL
= I
IL
I
OH
= I
IH
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Other TTL Characteristics
Unconnected Inputs (Floating)
Open input acts exactly like a logical 1 (HIGH)
Unused Inputs
Left disconnected (undesirable antenna)
Connect to V
CC
(+5V) through a 1-k resistor or to
GNDto produce for a constant-output logic level
Tied to a used input
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Other TTL Characteristics
Tied-Together Inputs
Represent a load Sum of the load current rating
NAND, AND gates: LOW-state input load single
input
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Other TTL Characteristics
Biasing TTL Inputs Low
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Other TTL Characteristics
Current Transients
high-amplitude current spike occurs when a totem-
pole TTL output goes fromLOWto HIGH
Power-supply decoupling: capacitors connect from
V
CC
to GND (0.01 F or 0.1 F)
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MOSFET
Metal-oxide-semiconductor field-effect transistor.
Advantage
Simple, inexpensive to fabricate
Small, little power consumption
Suited for complex ICs
Faster than 74, 74LS, 74ALS TTL Series
Disadvantage
susceptibility to static-electricity damage
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Enhancement MOSFET
Use in digital ICs
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Basic MOSFET Switch
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Digital MOSFET Circuit
N-MOS or P-MOS
Use MOSFET as a switch
Implement all resistors using channel resistance of a
MOSFET
Simple circuits and fabrication processes
C-MOS (complementary MOS)
Use both P- and N-channel MOSFET
Increase complexity of IC fabrication process, lower
packing density
Faster and less power consumption
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N-MOS Inverter
Gate of Q1 connected to
the drain always ON
pull-up resistor 100 k
Pull-up
resistor
Switch
on/off
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Complementary MOS Logic
CMOS Inverter
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Complementary MOS Logic
CMOS NAND Gate
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Complementary MOS Logic
CMOS NOR Gate
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CMOS Series
4000/14000 Series
74C Series
74HC/HCT (High-Speed CMOS)
74AC/ACT (Advanced CMOS)
74AHC/74AHCT (Advanced High-Speed CMOS)
BICMOS 5-Volt Logic
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Low-Voltage Technology
CMOS Family
74LVC (Low-Voltage CMOS)
74ALVC (Advanced Low-Voltage CMOS)
74LV (Low-Voltage)
74AVC (Advanced Very-Low-Voltage CMOS)
BiCMOS Family
74LVT (Low-Voltage BiCMOS Technology)
74LVT (Advanced Low-Voltage BiCMOS Technology)
74ALB (Advanced Low-Voltage BiCMOS)
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CMOS Characteristics (1)
Power-Supply Voltage
Logic Voltage Levels
Not sink/source any significant amount of current
V
OL
: close to 0 V, V
OH
: close to VDD
Noise Margins: greater than TTL
V
NH
= V
OH
(min) V
IH
(min)
V
NL
= V
IL
(max) V
OL
(max)
Power Dissipation
Extremely low Suitable for applications using
battery power
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CMOS Characteristics (2)
P
D
increases with Frequency
Increase in proportion to the frequency at switching
states of the circuit (LOWto HIGH)
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CMOS Characteristics (3)
Fan-Out: depend on
Permissible maximumpropagation delay
Frequency
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CMOS Characteristics (4)
Switching Speed
Faster than N-MOS and P-MOS (lowoutput resistance
1 k vs. 100 k)
Unused Inputs
Never left disconnected : susceptible to noise and
static charges
Tie to fixed voltage level (0V or V
DD
) or to another input
Static Sentivity
Latch-Up
Transistors stay ON permanently
Solution: Clamping diodes
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Output Combination (sharing a common wire)
Conventional CMOS outputs, TTL totem pole
outputs should never be tied together
Output voltage: in the indeterminate range
Damage the ICs
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Open-Collector/Open-Drain Outputs
Solution: remove the active pull-up transistor
CMOS output circuits: open-drain ouputs
TTL totempole output circuit: open-collector ouputs
Output LOWstate: no problem
Output HIGH state: external pull-up resistor R
p
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Open-collector/drain outputs Application
Wired-AND
connection
Open-collector/drain
Buffer/Driver
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Tristate (Three-State) Logic Ouputs
Allow three possible output states:
HIGH, LOW
High-impedance (Hi-Z): both pull-up and pull-down
transistors are turned OFF
Have an enable input (OE output enable)
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Tristate (Three-State) Logic Ouputs
Advantage
Tristate ICs output can be connected together
Low-impedance, high-speed characteristic
Application: Tristate Buffers
Bus contention
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CMOS Transmission Gate (Bilateral Switch)
Pass signals in both directions
Digital and analog applications
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IC Interfacing
Connecting the output(s) to the input(s) of
different electrical charateristic systems.
Take advange of the strong points of each IC
family
High-speed, greater output current/voltage capability,
high frequency
Concerned problems
Fan-out
Voltage and current parameters
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TTL Driving CMOS
Current: no problem
Output votages
V
OH
(min) of TTL: too lowwhen compared with V
IH
(min)
of CMOS
Solution: Pull-up resistor at TTL output
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TTL Driving CMOS
Driving High-Voltage CMOS
Use TTL series from certain manufacturers that can
operate with an high-voltage output pull-up
Utilize a voltage level-translator
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CMOS Driving TTL
Driving TTL in the HIGH State: no problem
Driving TTL in the LOW State:
Excepting 4000B series, 74HC/74HCT series have no
trouble driving a single TTL load of any series
Concern fan-out problem
Use buffer to interface low-current CMOS to high-
current TTL
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CMOS Driving TTL
High-Voltage CMOS Driving TTL
Use TTL series that can withstand high-voltage input
Use voltage level-translator
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Reference
Chapter 8, Digital System Principles and
Applications, Ronald J .Tocci, Neal S. Widmer