9230 Datasheet MV-S108075-00C

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Doc No. MV-S108075-00 Rev. C
J une 21, 2013
CONFIDENTIAL
Document Classification: Proprietary
Marvell. Moving Forward Faster
88SE9230 R1.1
Two-Lane PCIe 2.0 to Four-Port
SATA 6 Gbps RAID I/O Processor
Preliminary Datasheet
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88SE9230 R1.1 Two-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Processor
No part of this document may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, for any purpose, without the express written permission of
Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes
no warranty of any kind, expressed or implied, with regard to any information contained in this document,
including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose.
Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other
items contained within this document.
Marvell products are not designed for use in life-support equipment or applications that would cause a
life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment
or applications.
With respect to the products described herein, the user or recipient, in the absence of appropriate U.S.
government authorization, agrees:
1) Not to re-export or release any such information consisting of technology, software or source code
controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR
Country Groups D:1 or E:2;
2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if
such technology or software and direct products thereof are controlled for national security reasons by the
EAR; and,
3) In the case of technology controlled for national security reasons under the EAR where the direct product
of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2
the direct product of the plant or major component thereof, if such direct product is controlled for national
security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML").
At all times hereunder, the recipient of any such information agrees that they shall be deemed to have
manually signed this document in connection with their receipt of any such information.
Copyright 19992013. Marvell International Ltd. All rights reserved. Alaska, ARMADA, CarrierSpan, Kinoma,
Link Street, LinkCrypt, Marvell logo, Marvell, Moving Forward Faster, PISC, Prestera, Qdeo (for chips), QDEO
logo (for chips), QuietVideo, Virtual Cable Tester, Xelerated, and Yukon are registered trademarks of Marvell
or its affiliates. Avanta, Avastar, DragonFly, HyperDuo, Kirkwood, Marvell Smart, Qdeo, QDEO logo, The World
as YOU See It, Vmeta and Wirespeed by Design are trademarks of Marvell or its affiliates.
Patent(s) PendingProducts identified in this document may be covered by one or more Marvell patents
and/or patent applications.
For more information, visit our website at: www.marvell.com
ii
Copyright 2013 Marvell CONFIDENTIAL Doc No. MV-S108075-00 Rev. C
J une 21, 2013 Document Classification: Proprietary
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Ordering Information
iii
ORDERING INFORMATION
Ordering Part Numbers and Package Markings
The following figure shows the ordering part numbering scheme for the 88SE9230 part. For complete
ordering information, contact your Marvell FAE or sales representative.
Sample Ordering Part Number
The standard ordering part numbers for the respective solutions are indicated in the following table.
The next figure shows a typical Marvell package marking.
88SE9230 Package Marking and Pin 1 Location
Note: The above drawing is not drawn to scale. The location of markings is approximate. Add-on marks are not
represented. Flip chips vary widely in their markings and flip chip examples are not shown here. For flip chips, the
markings may be omitted per customer requirement.
Ordering Part Numbers
Part Number Description
88SE9230A1-NAA2C000 76-pin QFN 9 mm x 9 mm, Two-Lane PCIe 2.0 to four-port 6 Gpbs SATA RAID
I/O Processor.
Part Number
Product Revision
Custom Code
Custom Code
(optional )
88XXXXX - XX - XXX - C000 - XXXX
Temperature Code
C =Commercial
I =Industrial
Environmental Code
+=RoHS 0/6
=RoHS 5/6
1 =RoHS 6/6
2 =Green)
Package Code
3-character
alphabetic code
such as BCC, TEH
Custom Code
Extended Part Number
YYWW xx@
Country of Origin
Part number, package code, environment al code e
XXXXX =Part number
AAA =Package code
e =Environmental code
(+=RoHS 0/6, no code =RoHS 5/6,
1 =RoHS 6/6, 2 =Green)
Count ry of origin
(contained in the mold ID or
marked as the last line on
the package)
Pin 1 locat ion
Marvell Logo
Lot Number
88XXXXX-AAAe
Dat e code, custom code, assembly plant code
YYWW =Date code (YY =year, WW =Work Week)
xx =Custom code or die revision
@ =Assembly plant code
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Change History
v
CHANGE HISTORY
The following table identifies the document change history for Rev. C.
Document Changes *
* The type of change is categorized as: Parameter, Revision, or Update. A Parameter change is a change to a spec value, a Revision
change is one that originates from the chip Revision Notice, and an Update change includes all other document updates.
Location Type Description Date
Global Update Renamed all instances of PCI-Express to PCIe. J une 7, 2013
Page -iii Update Updated the Ordering Part Numbers from
88SE9230A0-NAA2C000 to 88SE9230A1-NAA2C000
J une 5, 2013
Page 1-1 Update Corrected Figure 1-1, 88SE9230 Architecture (All Others) to show
(5 Gbps 1) in PCIe 2.0x2 EndPoint Controller.
J une 14, 2013
Page 2-3 Update Corrected the Communication Speed from 5.0 Gbps to 5 Gbps
in the third bulleted item in section 2.2, PCIe.
April 18, 2013
Page 2-4 Update Made the following changes to the second bulleted item in section
2.3, SATA Controller:
Corrected the Communication Speed from 6.0 Gbps to 6
Gbps.
Corrected the Communication Speed from 3.0 Gbps to 3
Gbps.
April 18, 2013
Page 3-7 Update Removed the pin description of TST0 and TST1 in Table 3-7, Test
Mode Interface Signals:
J une 25, 2013
Page 4-5 Update Corrected the capacitors dimension from 1nF to 1 F in the
following sections:
Section 4.3.1, VDD Power (1.0V)
Section 4.3.2, Analog Power Supply (1.8V)
J une 11, 2013
Page 5-3 Update Made the following changes in Table 5-2, Recommended
Operating Conditions:
Changed the maximum Ambient Operating Temperature from
65C to 70C.
Added a new parameter: J unction Operating Temperature
with the minimum to maximum of (0125 C).
April 12, 2013
Page 5-4 Update Corrected the maximum value in Table 5-3, Power Requirements
as follows:
Changed the Analog Power for PCIe PHY Transmitter from 35
to 55.
April 18, 2013
Page 5-4 Update Made the following changes in Digital Core Power of Table
5-3, Power Requirements:
Removed the minimum value.
Corrected the maximum value from 1500 to 1200.
J une 11, 2013
Page 5-6 Update Added the following note to section 5.5, Thermal Data:
In additional to the airflow requirement, a heat sink is required to
assist the thermal dissipation.
May 28, 2013
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Contents
vii
CONTENTS
1 OVERVIEW ........................................................................................................................................................ 1-1
2 FEATURES ........................................................................................................................................................ 2-1
2.1 GENERAL .................................................................................................................................................. 2-2
2.2 PCIE ......................................................................................................................................................... 2-3
2.3 SATA CONTROLLER .................................................................................................................................. 2-4
2.4 SPI INTERFACE CONTROLLER .................................................................................................................... 2-5
2.5 PERIPHERAL INTERFACE CONTROLLER ....................................................................................................... 2-6
3 PACKAGE ......................................................................................................................................................... 3-1
3.1 PIN DIAGRAM ............................................................................................................................................ 3-2
3.2 MECHANICAL DIMENSIONS ......................................................................................................................... 3-3
3.3 SIGNAL DESCRIPTIONS ............................................................................................................................... 3-5
3.3.1 Pin Type Definitions .................................................................................................................. 3-5
3.3.2 Signal Descriptions ................................................................................................................... 3-5
4 LAYOUT GUIDELINES ...................................................................................................................................... 4-1
4.1 BOARD SCHEMATIC EXAMPLE .................................................................................................................... 4-2
4.2 LAYER STACK-UP ....................................................................................................................................... 4-4
4.2.1 Layer 1Topside, Parts, Slow and High Speed Signal Routes, and Power Routes .................. 4-4
4.2.2 Layer 2Solid Ground Plane ..................................................................................................... 4-4
4.2.3 Layer 3Power Plane ................................................................................................................ 4-4
4.2.4 Layer 4Bottom Layer, Slow and High-Speed Signal Routes, and Power Routes ................... 4-4
4.3 POWER SUPPLY ........................................................................................................................................ 4-5
4.3.1 VDD Power (1.0V) ..................................................................................................................... 4-5
4.3.2 Analog Power Supply (1.8V) ..................................................................................................... 4-5
4.3.3 Bias Current Resistor (RSET) ................................................................................................... 4-5
4.4 PCB TRACE ROUTING ............................................................................................................................... 4-6
4.5 RECOMMENDED LAYOUT ............................................................................................................................ 4-7
5 ELECTRICAL SPECIFICATIONS ...................................................................................................................... 5-1
5.1 ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 5-2
5.2 RECOMMENDED OPERATING CONDITIONS ................................................................................................... 5-3
5.3 POWER REQUIREMENTS ............................................................................................................................. 5-4
5.4 DC ELECTRICAL CHARACTERISTICS ............................................................................................................ 5-5
5.5 THERMAL DATA ......................................................................................................................................... 5-6
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1-1
Overview
1 OVERVIEW
The 88SE9230 is a four-port, 3 Gbps or 6 Gbps SATA RAID I/O processor that provides a
two-lane PCIe 2.0 interface and SATA controller functions. The 88SE9230 supplies four 6
Gbps SATA ports.
The 88SE9230 brings a high-performance 3 Gbps or 6 Gbps SATA hardware RAID solution
to desktop/consumer storage applications utilizing a two-lane PCIe 2.0 interface. The
integrated Marvell 88FR111 Revision 3 (Feroceon) CPU core supports RAID and
enclosure management. The 88SE9230 supports devices compliant with the Serial ATA
International Organization: Serial ATA Revision 3.1 specification. Figure 1-1 shows the
system block diagram.
Figure 1-1 88SE9230 Architecture (All Others)
PCIe 2.0 x2 EndPoint
Controller
(5 Gbps x 2)
Function 0
BAR Interface
RAID Processor
Peripheral Interface
Controller
(SPI / GPIO)
Internal Bus and Bus Arbiter
Serial ATA
4-port AHCI
Controller
(1.5, 3 or 6 Gbps)
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2-1
Features
2 FEATURES
This chapter contains the following sections:
General
PCIe
SATA Controller
SPI Interface Controller
Peripheral Interface Controller
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2-2 General
2.1 General
55 nm CMOS process, 1.0V digital core, 1.8V analog, and 3.3V I/O power supplies.
Reference clock frequency of 25 MHz, provided by an external clock source or generated by
an external crystal oscillator.
Supports hardware RAID 0, 1, and 10
s
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Features
PCIe 2-3
2.2 PCIe
PCIe 2.0 endpoint device.
Compliant with PCIe 2.0 specifications.
Supports communication speed of 2.5 Gbps and 5 Gbps.
Supports IDE programming interface registers for the SATA controller.
Supports AHCI programming interface registers for the SATA controller.
Supports aggressive power management.
Supports error reporting, recovery and correction.
Supports Message Signaled Interrupt (MSI).
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2-4 SATA Controller
2.3 SATA Controller
Compliant with Serial ATA Specification 3.1.
Supports communication speeds of 6 Gbps, 3 Gbps, and 1.5 Gbps.
Supports programmable transmitter signal levels.
Supports Gen 1i, Gen 1x, Gen 2i, Gen 2m, Gen 2x, and Gen 3i.
Supports four SATA ports.
Supports AHCI 1.0 and IDE programming interface.
Supports Native Command Queuing (NCQ).
Supports Port Multiplier FIS based switching or command based switching.
Supports Partial and Slumber Power Management states.
Supports Staggered Spin-up.
Supports AES-256
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I
B
I
T
E
D
Features
SPI Interface Controller 2-5
2.4 SPI Interface Controller
A four-pin interface provides read and write access to an external SPI flash or SPI ROM
device.
Vendor specific information stored in the external device is read by the controller during the
chip power-up.
PCI BootROMs of PCIe function 0 can also be stored in the external SPI device and read
through the Expansion ROM BAR and the SPI interface controller.
s
7
r
y
f
p
1
7
s
-
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i
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7
2
d
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0

*

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L
L

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O
N
F
I
D
E
N
T
I
A
L
,

U
N
D
E
R

N
D
A
#

1
2
1
0
1
1
1
2
s
7
r
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1
7
s
-
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2
d
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0

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N
F
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N
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L
,

U
N
D
E
R

N
D
A
#

1
2
1
0
1
1
1
2
s
7
r
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f
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1
7
s
-
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2
d
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0

*

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D
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R

N
D
A
#

1
2
1
0
1
1
1
2
M
A
R
V
E
L
L

C
O
N
F
I
D
E
N
T
I
A
L

-

U
N
A
U
T
H
O
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D

D
I
S
T
R
I
B
U
T
I
O
N

O
R

U
S
E

S
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Y

P
R
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2-6 Peripheral Interface Controller
2.5 Peripheral Interface Controller
Eight General Purpose I/O (GPIO) ports.
Each of the GPIO pins can be assigned to act as a general input or output pin.
Each of the GPIO inputs can be programmed to generate an edge-sensitive or a
level-sensitive maskable interrupt.
Each of the GPIO outputs can be programmed for a connected LED to blink at a
user-defined fixed rate. The default rate is 100 ms.
s
7
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7
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F
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,

U
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D
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R

N
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A
#

1
2
1
0
1
1
1
2
s
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U
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D
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R

N
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A
#

1
2
1
0
1
1
1
2
s
7
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R

N
D
A
#

1
2
1
0
1
1
1
2
M
A
R
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E
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C
O
N
F
I
D
E
N
T
I
A
L

-

U
N
A
U
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H
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D

D
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T
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I
B
U
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I
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N

O
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U
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E

S
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P
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D
3-1
Package
3 PACKAGE
Pin Diagram
Mechanical Dimensions
Signal Descriptions
s
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C
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E
N
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I
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L
,

U
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E
R

N
D
A
#

1
2
1
0
1
1
1
2
s
7
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1
7
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2
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C
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N
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L
,

U
N
D
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R

N
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A
#

1
2
1
0
1
1
1
2
s
7
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D
E
R

N
D
A
#

1
2
1
0
1
1
1
2
M
A
R
V
E
L
L

C
O
N
F
I
D
E
N
T
I
A
L

-

U
N
A
U
T
H
O
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D

D
I
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B
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N

O
R

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E

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3-2 Pin Diagram
3.1 Pin Diagram
The 76-pin QFN pin diagram is illustrated in Figure 3-1.
Figure 3-1 SE9230 Pin Diagram
Note: The center area beneath the chip is the Exposed Die Pad (Epad). When designing the PCB,
create a solder pad for the Epad and connect the Epad to ground.
S
P
I
_
D
O
GPIO7
V
D
D
T
X
P
_
3
V
S
S
R
X
P
_
2
R
X
P
_
3
R
X
N
_
3
T
X
N
_
3
V
A
A
2
_
2
T
X
N
_
2
G
P
I
O
3
1234567891
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
R
X
N
_
2
S
P
I
_
C
S
S
P
I
_
C
L
K
V
D
D
I
O
S
P
I
_
D
I
V
A
A
2
_
3
T
X
P
_
2
VSS
RXN_1
VAA2_1
RXP_1
88SE9230
WAKE_N
CLKN
VDD
PERST_N
TST2
GPIO1
GPIO0
TST0
TST5
TST4
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
58
59
60
CLKP
TST6
GPIO6
VDD
VDDIO
TST3
TST1
GPIO2
TP
VDD
N/C
TXP_0
N/C
TXN_0
RXN_0
RXP_0
TXN_1
VDD
TESTMODE
GPIO5
GPIO4
V
D
D
VAA2_0
20
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P
T
X
P
1
P
T
X
N
1
V
S
S
V
D
D
X
T
L
N
_
O
S
C
4
0
3
9
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
N
/
C
V
S
S
P
R
X
P
0
A
V
D
D
1
I
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E
T
V
A
A
1
A
V
D
D
0
P
T
X
P
0
X
T
L
O
U
T
P
R
X
P
1
P
T
X
N
0
P
R
X
N
0
P
R
X
N
1
N
/
C
TXP_1
s
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1
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1
1
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#

1
2
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1
1
1
2
M
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C
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N
T
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A
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-

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H
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D
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B
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N

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Package
Mechanical Dimensions 3-3
3.2 Mechanical Dimensions
The package mechanical drawing is shown in Figure 3-2.
Figure 3-2 Package Mechanical Diagram
s
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#

1
2
1
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1
1
1
2
s
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#

1
2
1
0
1
1
1
2
s
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#

1
2
1
0
1
1
1
2
M
A
R
V
E
L
L

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N
F
I
D
E
N
T
I
A
L

-

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A
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3-4 Mechanical Dimensions
The package mechanical dimensions are shown in Figure .
Figure 3-3 Package Mechanical Dimensions
s
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#

1
2
1
0
1
1
1
2
s
7
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7
s
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2
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#

1
2
1
0
1
1
1
2
s
7
r
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f
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1
7
s
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2
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0

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A
#

1
2
1
0
1
1
1
2
M
A
R
V
E
L
L

C
O
N
F
I
D
E
N
T
I
A
L

-

U
N
A
U
T
H
O
R
I
Z
E
D

D
I
S
T
R
I
B
U
T
I
O
N

O
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Package
Signal Descriptions 3-5
3.3 Signal Descriptions
This section contains the pin types and signal descriptions for the 88SE9230 package.
3.3.1 Pin Type Definitions
Pin type definitions are shown in Table 3-1.
3.3.2 Signal Descriptions
This section outlines the 88SE9230 pin descriptions. All signals ending with the letter N
indicate an active-low signal.
Table 3-1 Pin Type Definitions
Pin Type Definition
I/O Input and output
I Input only
O Output only
A Analog
PU Internal pull-up when input
PD Internal pull-down when input
OD Open-drain pad
Table 3-2 PCIe Interface Signals
Signal Name
Signal
Number
Type Description
PERST_N 61 I, PU PCI Platform Reset.
Active low, indicates when the applied power is within the specified
tolerance and stable.
WAKE_N 60 O, OD PCI Wake-up.
An open-drain, active low signal that is driven low by a PCIe
function to reactivate the PCIe Link hierarchys main power rails
and reference clocks.+
Note: For applications that support a wake-up function, connect this
pin to the WAKE# signal of a PCIe card slot or system board. Connect
an external pull-up resistor from the PCIe card slot or system board to
the 3.3V auxiliary supply. For applications that do not support a
wake-up function, keep the WAKE_N pin on the 88SE9230 open.
CLKP
CLKN
58
59
I, A Reference Clock.
Low voltage differential signals. The clock frequency has to be 100
MHz.
s
7
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7
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L
L

C
O
N
F
I
D
E
N
T
I
A
L
,

U
N
D
E
R

N
D
A
#

1
2
1
0
1
1
1
2
s
7
r
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f
p
1
7
s
-
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7
2
d
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0

*

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L
L

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N
F
I
D
E
N
T
I
A
L
,

U
N
D
E
R

N
D
A
#

1
2
1
0
1
1
1
2
s
7
r
y
f
p
1
7
s
-
h
i
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7
2
d
c
0

*

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D
E
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N
D
A
#

1
2
1
0
1
1
1
2
M
A
R
V
E
L
L

C
O
N
F
I
D
E
N
T
I
A
L

-

U
N
A
U
T
H
O
R
I
Z
E
D

D
I
S
T
R
I
B
U
T
I
O
N

O
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E

S
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Y

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3-6 Signal Descriptions
PRXP0
PRXN0
PRXP1
PRXN1
55
54
50
49
I, A PCIe differential signals to the controllers receiver.
PTXP0
PTXN0
PTXP1
PTXN1
52
51
47
46
O, A PCIe differential signals from the controllers transmitter.
Table 3-3 Serial ATA Interface Signals
Signal Name
Signal
Number
Type Description
TXN_0
TXP_0
TXN_1
TXP_1
TXN_2
TXP_2
TXN_3
TXP_3
33
34
27
28
12
13
6
7
O, A Serial ATA Transmitter Differential Outputs.
RXN_0
RXP_0
RXN_1
RXP_1
RXN_2
RXP_2
RXN_3
RXP_3
31
30
25
24
10
9
4
3
I, A Serial ATA Receiver Differential Inputs.
Table 3-4 Reference Signals
Signal Name
Signal
Number
Type Description
ISET 42 I/O, A Reference Current for Crystal Oscillator and PLL.
This pin has to be connected to an external 6.04 k 1% resistor to
Ground.
Table 3-2 PCIe Interface Signals (continued)
Signal Name
Signal
Number
Type Description
s
7
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7
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7
2
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1
2
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1
1
1
2
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2
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1
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1
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1
1
1
2
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N
F
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N
T
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A
L

-

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N
A
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T
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D
I
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T
R
I
B
U
T
I
O
N

O
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S
T
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P
R
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D
Package
XTLOUT 41 O, A Crystal Output.
XTLIN_OSC 40 I, A Reference Clock Input.
This signal can be from an oscillator, or connected to a crystal with
the XTLOUT pin. The clock frequency must be 25 MHz 80 ppm.
Table 3-5 General Purpose I/O Signals
Signal Name
Signal
Number
Type Description
GPIO0
GPIO1
GPIO2
GPIO3
GPIO5
GPIO4
GPIO6
GPIO7
63
69
70
18
21
20
75
76
I/O, PU General Purpose I/O.
Table 3-6 SPI Flash Interface Signals
Signal Name
Signal
Number
Type Description
SPI_CLK 17 O SPI Interface Clock.
SPI_DI 15 I, PU Serial Data In.
Connect to the serial flash devices serial data output (DO).
SPI_CS 14 O SPI Interface Chip Select.
SPI_DO 2 O Serial Data Out.
Connect to the serial flash devices serial data input (DI).
Table 3-7 Test Mode Interface Signals
Signal Name
Signal
Number
Type Description
TP 38 I/O, A Analog Test Point for PCIe PHY, SATA PHY, crystal oscillator, and
PLL.
TST0 64 I/O Test Pin 0.
Table 3-4 Reference Signals (continued)
Signal Name
Signal
Number
Type Description
s
7
r
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f
p
1
7
s
-
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i
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7
2
d
c
0

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1
2
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1
1
1
2
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7
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7
2
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1
2
1
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1
1
1
2
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7
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7
2
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1
2
1
0
1
1
1
2
M
A
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V
E
L
L

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O
N
F
I
D
E
N
T
I
A
L

-

U
N
A
U
T
H
O
R
I
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E
D

D
I
S
T
R
I
B
U
T
I
O
N

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E

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This pin is reserved for chip test purposes only. Keep floating.
TESTMODE 22 I, PD Test Mode.
Enables chip test modes.
Table 3-8 Power and Ground Pins
Signal Name
Signal
Number
Type Description
VAA2_0
VAA2_1
VAA2_2
VAA2_3
32
26
11
5
Power Analog power.
1.8V analog power supply for SATA PHY.
VAA1 39 Power Analog power
1.8V analog power for crystal oscillator, reference current
generator, and PLL.
AVDD0
AVDD1
53
48
Power Analog power.
1.8V analog power supply for PCIe PHY.
VDDIO 16, 68 Power I/O Power.
3.3V analog power supply for digital I/Os.
VDD 1, 19, 23,
36, 44, 62,
71
Power 1.0V Core Digital Power.
VSS 8, 29, 45,
56
Power Ground.
The main ground is the exposed die-pad (ePad) on the bottom
side of the package.
Table 3-9 No Connect Signals
Signal Name
Signal
Number
Type Description
N/C 35, 37,
43, 57
No Connect
Table 3-7 Test Mode Interface Signals (continued)
Signal Name
Signal
Number
Type Description
s
7
r
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f
p
1
7
s
-
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7
2
d
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0

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1
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Package
s
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4-1
Layout Guidelines
4 LAYOUT GUIDELINES
This chapter describes the system recommendations from the Marvell Semiconductor
design and application engineers who work with the 88SE9230. It is written for those who are
designing schematics and printed circuit boards for an 88SE9230-based system. Whenever
possible, the PCB designer should try to follow the suggestions provided in this chapter.
The information in this chapter is preliminary. Please consult with Marvell Semiconductor
design and application engineers before starting your PCB design.
The chapter contains the following sections:
Board Schematic Example
Layer Stack-up
Power Supply
PCB Trace Routing
Recommended Layout
Refer to Chapter 3, Package, for package information.
s
7
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1
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1
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4-2 Board Schematic Example
4.1 Board Schematic Example
The board schematic consists of the major interfaces of the 88SE9230 including SATA and
PCIe. Figure 4-1 shows an example of board schematic.
Figure 4-1 SE9230 Example Board Schematic
1
S
_
T
X
P
0
S
0
_
T
X
P
S
0
_
T
X
N
S
0
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S
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1
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S
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1
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1
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N
P R X _ 1 P
S
_
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X
N
0
T
E
S
T
M
O
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P T X _ 1 P
P R X _ 1 N
A V D D 1
S
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S
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1
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D
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0
V
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0
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P R X _ 0 P
P R X _ 0 N
X T L I
P T X _ 1 N
V D D _ 1 0
P
E
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N
A V D D 0
P T X _ 0 N
P T X _ 0 P
S
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A
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A
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1
I S E T
G
N
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P
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P
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2
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2
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2
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N
2
S
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2
S
2
_
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X
N
S
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P
2
S
3
_
T
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S
3
_
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N
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3
_
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3
S
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3
S
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3
S
3
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3
X T L O U T
P
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4
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G
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3
G
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G P I O 3
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V D D _ 1 0
S _ T X N 2
V A A 2 _ 2
S _ R X N 2
G N D
S _ T X N 3
S _ R X N 3
S _ R X P 3
V D D _ 1 0
S _ T X P 3
S _ T X P 2
V A A 2 _ 3
V D D I O
S
P
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3
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3
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8
1
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3
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Layout Guidelines
Board Schematic Example 4-3
Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest
schematics.
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4-4 Layer Stack-up
4.2 Layer Stack-up
The following layer stack up is recommended:
Layer 1Topside, Parts, Slow and High Speed Signal Routes, and Power Routes
Layer 2Solid Ground Plane
Layer 3Power Plane
Layer 4Bottom Layer, Slow and High-Speed Signal Routes, and Power Routes
5 mil traces and 5 mil spacing are the recommended minimum requirements.
4.2.1 Layer 1Topside, Parts, Slow and High Speed Signal Routes, and Power
Routes
All active parts are to be placed on the topside. Some of the differential pairs for SATA and
PCIe are routed on the top layer, differential 100 ohm impedance needs to be maintained for
those high speed signals.
4.2.2 Layer 2Solid Ground Plane
A solid ground plane should be located directly below the top layer of the PCB. This layer
should be a minimum distance below the top layer in order to reduce the amount of crosstalk
and EMI. There should be no cutouts in the ground plane. Use of 1 ounce copper is
recommended.
4.2.3 Layer 3Power Plane
Use solid planes on layer 3 to supply power to the ICs on the PCB. Avoid narrow traces and
necks on this plane.
4.2.4 Layer 4Bottom Layer, Slow and High-Speed Signal Routes, and Power Routes
Some of the differential pairs for SATA and PCIe are routed on the top layer, differential 100
impedance needs to be maintained for those high speed signals. The high speed signals
have the return current on the third layer, which is the power plane. Make sure there is no
cut-out under the signal path.
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Layout Guidelines
Power Supply 4-5
4.3 Power Supply
The 88SE9230 operates using the following power supplies:
VDD Power (1.0V) for the digital core
Analog Power Supply (1.8V)
4.3.1 VDD Power (1.0V)
All digital power pins (VDD pins) must be connected directly to a VDD plane in the power
layer with short and wide traces to minimize digital power-trace inductances.
Use vias close to the VDD pins to connect to this plane and avoid using the traces on the top
layer. Marvell recommends placing capacitors around the three sides of the PCB near VDD
pins with the following dimensions:
1 F (1 capacitor)
0.1 F (2 capacitors)
2.2 F (1 ceramic capacitor)
The 2.2 F ceramic decoupling capacitor is needed to filter the lower frequency power-supply
noise.
To reduce system noise, the use of high-frequency surface-mount monolithic ceramic bypass
capacitors should be placed as close as possible to the channel VDD pins. At least one
decoupling capacitor should be placed on each side of the IC package.
Short and wide copper traces should be used to minimize parasitic inductances. Low-value
capacitors (1,00010,000 pF) are preferable over higher values because they are more
effective at higher frequencies.
4.3.2 Analog Power Supply (1.8V)
The PCIe analog supply provides power for the PCIe links high speed serial signals. To
ensure high speed link operation, use a series of bypass capacitors for the supplies. A typical
capacitor value combination is 1 F, 0.1F, and 2.2 F.
4.3.3 Bias Current Resistor (RSET)
Connect a 6.04K (1%) resistor between the ISET pin and the adjacent top ground plane.
This resistor should lie as close as possible to the ISET pin.
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4-6 PCB Trace Routing
4.4 PCB Trace Routing
The stack-up parameters for the reference board are shown in Table 4-1.
Table 4-1 PCB Board Stack-up Parameters
Layer
Layer
Description
Copper Weight
(oz)
Target Impedance
(10%)
1 Signal 0.5 50
2 GND 1 N/A
3 Power 1 N/A
4 Signal 0.5 50
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Layout Guidelines
Recommended Layout 4-7
4.5 Recommended Layout
Solid ground planes are recommended. However, special care should be taken when routing
VAA and VSS pins.
The following general tips describe what should be considered when determining your
stack-up and board routing. These tips are not meant to substitute for consulting with a
signal-integrity expert or doing your own simulations.
Note: Specific numbers or rules-of-thumb are not used here because they might not be applicable in
every situation.
Do not split ground planes.
Keep good spacing between possible sensitive analog circuitry on your board and the digital
signals to sufficiently isolate noise. A solid ground plane is necessary to provide a good return
path for routing layers. Try to provide at least one ground plane adjacent to all routing layers
(see Figure 4-2).
Keep trace layers as close as possible to the adjacent ground or power planes.
This helps minimize crosstalk and improve noise control on the planes.
Figure 4-2 Trace Has At Least One Solid Plane For Return Path
When routing adjacent to only a power plane, do not cross splits.
Route traces only over the power plane that supplies both the driver and the load. Otherwise,
provide a decoupling capacitor near the trace at the end that is not supplied by the adjacent
power plane.
Critical signals should avoid running parallel and close to or directly over a gap.
This would change the impedance of the trace.
Separate analog powers onto opposing planes.
This helps minimize the coupling area that an analog plane has with an adjacent digital plane.
For dual strip-line routing, traces should only cross at 90 degrees.
Avoid more than two routing layers in a row to minimize tandem crosstalk and to better control
impedance.
Planes should be evenly distributed in order to minimize warping.
Calculating or modeling impedance should be made prior to routing.
This helps ensure that a reasonable trace thickness is used and that the desired board
thickness is available. Consult with your board fabricator for accurate impedance.
GND
V2
V1
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4-8 Recommended Layout
Allow good separation between fast signals to avoid crosstalk.
Crosstalk increases as the parallel traces get longer.
When packages become smaller, route traces over a split power plane
Smaller packages force vias to become smaller, thereby reducing board thickness and layer
counts, which might create the need to route traces over a split power plane. Some
alternatives to provide return path for these signals are listed below.
Caution must be used when applying these techniques. Digital traces should not cross over
analog planes, and vice-versa. All of these rules must be followed closely to prevent noise
contamination problems that might arise due to routing over the wrong plane.
By tightly controlling the return path, control noise on the power and ground planes can be
controlled.
Place a ground layer close enough to the split power plane in order to couple enough to
provide buried capacitance, such as SIG-PWR-GND (see Figure 4-3). Return signals that
encounter splits in this situation simply jumps to the ground plane, over the split, and back
to the other power plane. Buried capacitance provides the benefit of adding low
inductance decoupling to your board. Your fabricator may charge for a special license fee
and special materials. To determine the amount of capacitance your planes provide, use
the following equation:
Where E
R
is the dielectric coefficient, L W represents the area of copper, and H is the
separation between planes.
Provide return-path capacitors that connect to both power planes and jumps the split.
Place them close to the traces so that there is one capacitor for every four or five traces.
The capacitors would then provide the return path (see Figure 4-4).
Allow only static or slow signals on layers where they are adjacent to split planes.
Figure 4-3 shows the ground layer close to the split power plane.
Figure 4-3 Close Power and Ground Planes Provide Coupling For Good Return Path
Figure 4-4 shows the thermal ground plane in relation to the return-path capacitor.
Figure 4-4 Suggested Thermal Ground Plane On Opposite Side of Chip
C 1.249 10
13
E
r
L W H =
V2 PLANE
GND PLANE
V1 PLANE
H
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5-1
Electrical Specifications
5 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Recommended Operating Conditions
Power Requirements
DC Electrical Characteristics
Thermal Data
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5-2 Absolute Maximum Ratings
5.1 Absolute Maximum Ratings
Table 5-1 defines the absolute maximum ratings for the 88SE9230.
Table 5-1 Absolute Maximum Ratings*
* Estimated values are provided until characterization is complete.
Parameter Symbol Min Typ Max Units
Absolute Analog Power for PCIe PHY AVDD0
abs
-0.5 1.98
Absolute Analog Power for PCI-E Phy AVDD1
abs
-0.5 1.98
Absolute Analog Power for Crystal Oscillator and
PLL
VAA1
abs
-0.5 1.98 V
Absolute Analog Power for SATA PHY VAA2_0
abs
-0.5 1.98 V
abs
-0.5 1.98 V
abs
-0.5 1.98 V
abs
-0.5 1.98 V
Absolute Digital Core Power VDD
abs
-0.5 1.10 V
Absolute Digital I/O Power VDDIO
abs
-0.5 3.63 V
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A
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Recommended Operating Conditions 5-3
5.2 Recommended Operating Conditions
Table 5-2 defines the recommended operating conditions for the 88SE9230.
Table 5-2 Recommended Operating Conditions*
Analog Power for PCIe PHY AVDD0
op
1.71 1.8 1.89 V
Analog Power for PCIe PHY AVDD1
op
1.71 1.8 1.89 V
Analog Power for Crystal Oscillator and PLL VAA1
op
1.71 1.8 1.89 V
Analog Power for SATA PHY VAA2_0
op
1.71 1.8 1.89 V
Analog Power for SATA PHY VAA2_1
op
1.71 1.8 1.89 V
Analog Power for SATA Phy VAA2_2
op
1.71 1.8 1.89 V
Analog Power for SATA Phy VAA2_3
op
1.71 1.8 1.89 V
Digital Core Power VDD
op
0.95 1.0 1.05 V
Digital I/O Power VDDIO
op
3.135 3.3 3.465 V
Internal Bias Reference ISET
op
5.738 6.04 6.342 K
Ambient Operating Temperature 0 70 C
J unction Operating Temperature 0 125 C
s
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5-4 Power Requirements
5.3 Power Requirements
Table 5-3 defines the power requirements for the 88SE9230.
Table 5-3 Power Requirements*
Analog Power for PCIe PHY Transmitter I
AVDD0
55 mA
Analog Power for PCI-E Phy Transmitter I
AVDD1
55 mA
Analog Power for Crystal Oscillator and PLL I
VAA1
10 mA
Analog Power for SATA PHY I
VAA2_0
70 mA
Analog Power for SATA PHY I
VAA2_1
70 mA
Analog Power for SATA Phy I
VAA2_2
70 mA
Analog Power for SATA Phy I
VAA2_3
70 mA
Digital Core Power I
VDD
1200 mA
Digital I/O Power (3.3V)
The digital I/O power supply can be either 3.3V or 1.8V.
I
VDDIO
50 mA
s
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DC Electrical Characteristics 5-5
5.4 DC Electrical Characteristics
Table 5-4 defines the DC electrical characteristics for the 88SE9230.
Table 5-4 DC Electrical Characteristics*
Parameter Symbol Test Condition Min Typ Max Units
Input Low Level Voltage V
IL
-0.4 0.25 x
VDDIO
V
Input High Level Voltage V
IH
0.8 x
VDDIO
5.5 V
Output Low Level Current I
OL
V
PAD
=0.4V 5 mA
Output High Level Current I
OH
V
PAD =
VDDIO 0.4V 5 mA
Pull Up Strength I
PU
V
PAD =
0.5 x VDDIO 10 A
Pull Down Strength I
PD
V
PAD =
0.5 x VDDIO 10 A
Input Leakage Current I
LK
0 <V
PAD
<VDDIO 10 A
Input Capacitance C
IN
0 <V
PAD
<5.5V 5 pF
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5-6 Thermal Data
5.5 Thermal Data
It is recommended to read application note AN-63 Thermal Management for Selected
Marvell Products (Document Number MV-S300281-00) and the ThetaJC, ThetaJA, and
Temperature Calculations White Paper, available from Marvell, before designing a system.
These documents describe the basic understanding of thermal management of integrated
circuits (ICs) and guidelines to ensure optimal operating conditions for Marvell products.
Note: In additional to the airflow requirement, a heat sink is required to assist the thermal dissipation.
Table 5-5 provides the thermal data for the 88SE9230. The simulation was performed
according to J EDEC standards.
Table 5-5 shows the values for the package thermal parameters for the 76-lead Quad Flat
Non-Lead package (QFN 76) mounted on a 4-layer PCB.
Table 5-5 Package Thermal Data
Parameter Definition
Airflow Value
0 m/s 1 m/s 2 m/s 3 m/s
J A
Thermal resistance: junction to
ambient
29.9 C/W 26.6 C/W 25.5 C/W 24.8 C/W
J B
Thermal characterization
parameter: junction to bottom
surface center of the package.
15.60 C/W 15.59 C/W 15.58 C/W 15.57 C/W
J T
Thermal characterization
parameter: junction to top center
0.63 C/W 0.93 C/W 1.17 C/W 1.34 C/W
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#

1
2
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1
1
1
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M
A
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L

C
O
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F
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D
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Marvell Semiconductor, Inc.
5488 Marvell Lane
Santa Clara, CA 95054, USA
Tel: 1.408.222.2500
Fax: 1.408.752.9028
www.marvell.com
Marvell. Moving Forward Faster

9230 Datasheet MV-S108075-00C

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