Digital Unit - IV

Digital Electronics
UINT IV
Sequential Logic Basics
Unlike Combinational Logic circuits that change state depending upon the actual signals being
applied to their inputs at that time, Seuential Logic circuits ha!e some "orm o" inherent
#$emor%# built in to them and the% are able to take into account their pre!ious input state as
&ell as those actuall% present, a sort o" #be"ore# and #a"ter# is in!ol!ed' The% are generall%
termed as T&o State or (istable de!ices &hich can ha!e their output set in either o" t&o basic
states, a logic le!el #)# or a logic le!el #*# and &ill remain #latched# inde"initel% in this current
state or condition until some other input trigger pulse or signal is applied &hich &ill cause it to
change its state once again'
Sequential Logic Circuit
The &ord #Seuential# means that things happen in a #seuence#, one a"ter another and in
Seuential Logic circuits, the actual clock signal determines &hen things &ill happen ne+t'
Simple seuential logic circuits can be constructed "rom standard (istable circuits such as ,lip-
"lops, Latches or Counters and &hich themsel!es can be made b% simpl% connecting together
N.ND /ates and0or N12 /ates in a particular combinational &a% to produce the reuired
seuential circuit'
Sequential Logic circuits can be divided into 3 main categories:
)' Clock Dri!en - S%nchronous Circuits that are S%nchronised to a speci"ic clock signal'
3' E!ent Dri!en - .s%nchronous Circuits that react or change state &hen an e+ternal e!ent
occurs'
4' 5ulse Dri!en - 6hich is a Combination o" S%nchronous and .s%nchronous'
Department o" Electronics 7arpagam Uni!ersit%
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Digital Electronics
Classification of Sequential Logic
.s &ell as the t&o logic states mentioned abo!e logic le!el #)# and logic le!el #*#, a third
element is introduced that separates Seuential Logic circuits "rom their Combinational Logic
counterparts, namel% TI$E' Seuential logic circuits that return back to their original state once
reset, i'e' circuits &ith loops or "eedback paths are said to be #C%clic# in nature'
Flip-Flops
,lip-"lops are s%nchronous bistable de!ices' The term s%nchronous means the output changes
state onl% &hen the clock input is triggered' That is, changes in the output occur in
s%nchroni8ation &ith the clock'
,lip-"lop is a kind o" multi!ibrator' There are three t%pes o" multi!ibrators9
)' $onostable multi!ibrator :also called one-shot; has onl% one stable state' It produces a
single pulse in response to a triggering input'
3' (istable multi!ibrator e+hibits t&o stable states' It is able to retain the t&o SET and
2ESET states inde"initel%' It is commonl% used as a basic building block "or counters,
registers and memories'
4' .stable multi!ibrator has no stable state at all' It is used primaril% as an oscillator to
generate periodic pulse &a!e"orms "or timing purposes'
Edge-Triggered Flip-flops
.n edge-triggered "lip-"lop changes states either at the positi!e edge :rising edge; or at the
negati!e edge :"alling edge; o" the clock pulse on the control input' The three basic t%pes are
introduced here9 S-2, <-7 and D'
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Digital Electronics
The S-2, <-7 and D inputs are called s%nchronous inputs because data on these inputs are
trans"erred to the "lip-"lop=s output onl% on the triggering edge o" the clock pulse' 1n the other
hand, the direct set :SET; and clear :CL2; inputs are called as%nchronous inputs, as the% are
inputs that a""ect the state o" the "lip-"lop independent o" the clock' ,or the s%nchronous
operations to &ork properl%, these as%nchronous inputs must both be kept L16'
Edge-triggered S-R flip-flop
The basic operation is illustrated belo&, along &ith the truth table "or S-2 "lip-"lop' The
operation and truth table "or a negati!e edge-triggered "lip-"lop are the same as those "or a
positi!e e+cept that the "alling edge o" the clock pulse is the triggering edge'
.s S > ), 2 > *' ,lip-"lop SETS on the rising
clock edge'
Note that the S and 2 inputs can be changed at an% time &hen the clock input is L16 or ?I/?
:e+cept "or a !er% short inter!al around the triggering transition o" the clock; &ithout a""ecting
the output' This is illustrated in the timing diagram belo&9
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Digital Electronics
Edge-triggered -! flip-flop
The <-7 "lip-"lop &orks !er% similar to S-2 "lip-"lop' The onl% di""erence is that this "lip-"lop
has N1 in!alid state' The outputs toggle :change to the opposite state; &hen both < and 7 inputs
are ?I/?' The truth table is sho&n belo&'
Edge-triggered " flip-flop
The operations o" a D "lip-"lop is much more simpler' It has onl% one input addition to the clock'
It is !er% use"ul &hen a single data bit :* or ); is to be stored' I" there is a ?I/? on the D input
&hen a clock pulse is applied, the "lip-"lop SETs and stores a )' I" there is a L16 on the D input
&hen a clock pulse is applied, the "lip-"lop 2ESETs and stores a *' The truth table belo&
summari8e the operations o" the positi!e edge-triggered D "lip-"lop' .s be"ore, the negati!e
edge-triggered "lip-"lop &orks the same e+cept that the "alling edge o" the clock pulse is the
triggering edge'
#ulse-Triggered $%aster-Slave& Flip-flops
The term pulse-triggered means that data are entered into the "lip-"lop on the rising edge o" the
clock pulse, but the output does not re"lect the input state until the "alling edge o" the clock pulse'
.s this kind o" "lip-"lops are sensiti!e to an% change o" the input le!els during the clock pulse is
still ?I/?, the inputs must be set up prior to the clock pulse=s rising edge and must not be
changed be"ore the "alling edge' 1ther&ise, ambiguous results &ill happen'
The three basic t%pes o" pulse-triggered "lip-"lops are S-2, <-7 and D' Their logic s%mbols are
sho&n belo&' Notice that the% do not ha!e the d%namic input indicator at the clock input but
ha!e postponed output s%mbols at the outputs'
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Digital Electronics
The truth tables "or the abo!e pulse-triggered "lip-"lops are all the same as that "or the edge-
triggered "lip-"lops, e+cept "or the &a% the% are clocked' These "lip-"lops are also called $aster-
Sla!e "lip-"lops simpl% because their internal construction are di!ided into t&o sections' The
sla!e section is basicall% the same as the master section e+cept that it is clocked on the in!erted
clock pulse and is controlled b% the outputs o" the master section rather than b% the e+ternal
inputs' The logic diagram "or a basic master-sla!e S-2 "lip-"lop is sho&n belo&'
The master0sla!e "lip-"lop o!ercomes the "ollo&ing problems'
2I55LE T?21U/?' .n input changes le!el during the clock period, and the change
appears at the output'
5215./.TI1N DEL.A' The time bet&een appl%ing a signal to an input, and the
resulting change in the output'
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Digital Electronics
These can gi!e problems in logic circuits' The maste0sla!e "lip"lop consists o" t&o rising edge
triggered D t%pe "lip-"lops' The clock o" the sla!e is "ed !ia an in!erter so that the "alling edge o"
the origonal clock pulse becomes a rising edge' The sla!e clock pulse is an in!erted !ersion o"
the clock pulse sho&n in the lo&er diagram' The "lip-"lops are triggered at di""erent le!els o" the
clock pulse edge' 6hen data is to be entered, the sla!e is isolated "rom the master, so that
changes at the input do not appear at the output'Data on D is passed to C o" the master' The
master is then isolated "rom the D input' Data, "rom the C o" the master, is passed to C o" the
sla!e'
t)' Sla!e isolated "rom $aster'
t3' $aster connected to D input'
t4' $aster isolated "rom D input'
t@' $aster C connected Sla!e D'
Toggle Flip-Flop
This "lip-"lop toggles :C changes state; on the negati!e going edge o" the clock pulse' T acts as
an EN.(LE 0 IN?I(IT control' C &ill onl% toggle on the negati!e edge o" the clock pulse, &hen
T is high' (elo& is sho&n a D t%pe "lip-"lop connected as a toggle t%pe' 1n each clock pulse
positi!e going edge, C &ill go to the state bar C &as be"ore the clock pulse arri!ed' 2emember
that bar C is the opposite le!el to C' There"ore C &ill toggle' This t%pe o" "lip-"lop is a simpli"ied
!ersion o" the <7 "lip-"lop' It is not usuall% "ound as an IC chip b% itsel", but is used in man%
kinds o" circuits, especiall% counter and di!iders' Its onl% "unction is that it toggles itsel" &ith
e!er% clock pulse :on either the leading edge, on the trailing edge; it can be constructed "rom the
2S "lip-"lop as sho&n in ,igure :a;'
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Digital Electronics
This "lip "lop is normall% set, or EEloaded== &ith the preset and clear inputs' It can be used to
obtain an output pulse train &ith a "reuenc% o" hal" that o" the clock pulse train, as seen "rom the
timing diagram, ,igure :b;' In this e+ample, the T "lip "lop is triggered on the "alling edge o" the
clock pulse' Se!eral T "lip-"lops are o"ten connected together in a simple IC to "orm a EEdi!ide b%
N== counter, &here N is usuall% B, )*, )3 or a po&er o" 3'
'verall Be(avior
Each "lip-"lop stores a single bit o" data, &hich is emitted through the Q output on the east side'
Normall%, the !alue can be controlled !ia the inputs to the &est side' In particular, the !alue
changes &hen the cloc) input, marked b% a triangle on each "lip-"lop, rises "rom * to )F on this
rising edge, the !alue changes according to the corresponding table belo&'
" Flip-Flop T Flip-Flop -! Flip-Flop S-R Flip-Flop
D Q
* *
) )
T Q
* Q
) Q=
J K Q
* * Q
* ) *
) * )
) ) Q=
S R Q
* * Q
* ) *
) * )
) ) ??
.nother &a% o" describing the di""erent beha!ior o" the "lip-"lops is as "ollo&s9
" Flip-Flop: 6hen the clock rises "rom * to ), the !alue remembered b% the "lip-"lop
becomes the !alue o" the D input :Data; at that instant'
T Flip-Flop: 6hen the clock rises "rom * to ), the !alue remembered b% the "lip-"lop
either toggles or remains the same depending on &hether the T input :Toggle; is ) or *'
-! Flip-Flop: 6hen the clock rises "rom * to ), the !alue remembered b% the "lip-"lop
toggles i" the J and K inputs are both ), remains the same i" the% are both *, and changes
to the K input !alue i" J and K are not eual' :The names J and K do not stand "or
an%thing';
R-S Flip-Flop: 6hen the clock rises "rom * to ), the !alue remembered b% the "lip-"lop
remains unchanged i" R and S are both *, becomes * i" the R input :Reset; is ), and
becomes ) i" the S input :Set; is )' The beha!ior in unspeci"ied i" both inputs are )' :In
Logisim, the !alue in the "lip-"lop remains unchanged';
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Digital Electronics
S(ift Registers
Shi"t 2egisters consists o" a number o" single bit #D-T%pe Data Latches# connected together in a
chain arrangement so that the output "rom one data latch becomes the input o" the ne+t latch and
so on, thereb% mo!ing the stored data seriall% "rom either the le"t or the right direction' The
number o" indi!idual Data Latches used to make up Shi"t 2egisters are determined b% the
number o" bits to be stored' The most common used is H-bits &ide' Shi"t 2egisters are mainl%
used to store data and to con!ert data "rom either a serial to parallel or parallel to serial "ormat
&ith all the latches being dri!en b% a common clock :Clk; signal making them S%nchronous
de!ices' The% are generall% pro!ided &ith a Clear or 2eset connection so that the% can be #SET#
or #2ESET# as reuired'
/enerall%, Shi"t 2egisters operate in one o" "our di""erent modes9
Serial-in to 5arallel-out :SI51;
Serial-in to Serial-out :SIS1;
5arallel-in to 5arallel-out :5I51;
5arallel-in to Serial-out :5IS1;
Serial-in to #arallel-out*
,ig9 @-bit Serial-in to 5arallel-out :SI51; Shi"t 2egister
Lets assume that all the "lip-"lops :,,. to ,,D; ha!e Iust been 2ESET :CLE.2 input; and that
all the outputs C. to CD are at logic le!el #*# ie, no parallel data output' I" a logic #)# is
connected to the D.T. input pin o" ,,. then on the "irst clock pulse the output o" ,,. and the
resulting C. &ill be set ?I/? to logic #)# &ith all the other outputs remaining L16 at logic
#*#' .ssume no& that the D.T. input pin o" ,,. has returned L16 to logic #*#' The ne+t clock
pulse &ill change the output o" ,,. to logic #*# and the output o" ,,( and C( ?I/? to logic
#)#' The logic #)# has no& mo!ed or been #Shi"ted# one place along the register to the right'
6hen the third clock pulse arri!es this logic #)# !alue mo!es to the output o" ,,C :CC; and so
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Digital Electronics
on until the arri!al o" the "i"th clock pulse &hich sets all the outputs C. to CD back again to
logic le!el #*# because the input has remained at a constant logic le!el #*#'
The e""ect o" each clock pulse is to shi"t the D.T. contents o" each stage one place to the right,
and this is sho&n in the "ollo&ing table until the complete D.T. is stored, &hich can no& be
read directl% "rom the outputs o" C. to CD' Then the D.T. has been con!erted "rom a Serial
Data signal to a 5arallel Data &ord'
Clock 5ulse No C. C( CC CD
* * * * *
) ) * * *
3 * ) * *
4 * * ) *
@ * * * )
B * * * *
Serial-in to Serial-out
This Shi"t 2egister is !er% similar to the one abo!e e+cept &here as the data &as read directl% in
a parallel "orm "rom the outputs C. to CD, this time the D.T. is allo&ed to "lo& straight
through the register' Since there is onl% one output the D.T. lea!es the shi"t register one bit at a
time in a serial pattern and hence the name Serial-in to Serial-1ut Shi"t 2egister'
,ig9 @-bit Serial-in to Serial-out :SIS1; Shi"t 2egister
This t%pe o" Shi"t 2egister also acts as a temporar% storage de!ice or as a time dela% de!ice, &ith
the amount o" time dela% being controlled b% the number o" stages in the register, @, H, )D etc or
b% !ar%ing the application o" the clock pulses' Commonl% a!ailable IC=s include the G@?CBJB H-
bit Serial-in0Serial-out Shi"t 2egister &ith 4-state outputs'
#arallel-in to Serial-out
5arallel-in to Serial-out Shi"t 2egisters act in the opposite &a% to the Serial-in to 5arallel-out one
abo!e' The D.T. is applied in parallel "orm to the parallel input pins 5. to 5D o" the register
and is then read out seuentiall% "rom the register one bit at a time "rom 5. to 5D on each clock
c%cle in a serial "ormat'
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Digital Electronics
,ig9 @-bit 5arallel-in to Serial-out :5IS1; Shi"t 2egister
.s this t%pe o" Shi"t 2egister con!erts parallel data, such as an H-bit data &ord into serial data it
can be used to multiple+ man% di""erent input lines into a single serial D.T. stream &hich can
be sent directl% to a computer or transmitted o!er a communications line' Commonl% a!ailable
IC=s include the G@?C)DB H-bit 5arallel-in0Serial-out Shi"t 2egisters'
#arallel-in to #arallel-out
5arallel-in to 5arallel-out Shi"t 2egisters also act as a temporar% storage de!ice or as a time dela%
de!ice' The D.T. is presented in a parallel "ormat to the parallel input pins 5. to 5D and then
shi"ts it to the corresponding output pins C. to CD &hen the registers are clocked'
,ig 9 @-bit 5arallel-in05arallel-out :5I51; Shi"t 2egister
.s &ith the Serial-in to Serial-out shi"t register, this t%pe o" register also acts as a temporar%
storage de!ice or as a time dela% de!ice, &ith the amount o" time dela% being !aried b% the
"reuenc% o" the clock pulses'
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Digital Electronics
Toda%, high speed bi-directional uni!ersal t%pe Shi"t 2egisters such as the TTL G@LS)J@,
G@LS)JB or the C$1S @*4B are a!ailable as a @-bit multi-"unction de!ices that can be used in
serial-serial, shi"t le"t, shi"t right, serial-parallel, parallel-serial, and as a parallel-parallel Data
2egisters, hence the name #Uni!ersal#'
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Digital Electronics
C'+,TERS
Ring counters
I" the output o" a shi"t register is "ed back to the input' a ring counter results' The data pattern
contained &ithin the shi"t register &ill recirculate as long as clock pulses are applied' ,or
e+ample, the data pattern &ill repeat e!er% "our clock pulses in the "igure belo&' ?o&e!er, &e
must load a data pattern' .ll *=s or all )=s doesn=t count' Is a continuous logic le!el "rom such a
condition use"ulK
6e make pro!isions "or loading data into the parallel-in0 serial-out shi"t register con"igured as a
ring counter belo&' .n% random pattern ma% be loaded' The most generall% use"ul pattern is a
single )'
Loading binar% )*** into the ring counter, abo!e, prior to shi"ting %ields a !ie&able pattern' The
data pattern "or a single stage repeats e!er% "our clock pulses in our @-stage e+ample' The
&a!e"orms "or all "our stages look the same, e+cept "or the one clock time dela% "rom one stage
to the ne+t' See "igure belo&'
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Digital Electronics
The circuit abo!e is a di!ide b% @ counter' Comparing the clock input to an% one o" the outputs,
sho&s a "reuenc% ratio o" @9)' ?o& ma% stages &ould &e need "or a di!ide b% )* ring counterK
Ten stages &ould recirculate the ) e!er% )* clock pulses'
o(nson counters
The s&itch-tail ring counter, also kno& as the <ohnson counter, o!ercomes some o" the
limitations o" the ring counter' Like a ring counter a <ohnson counter is a shi"t register "ed back
on its= sel"' It reuires hal" the stages o" a comparable ring counter "or a gi!en di!ision ratio' I"
the complement output o" a ring counter is "ed back to the input instead o" the true output, a
<ohnson counter results' The di""erence bet&een a ring counter and a <ohnson counter is &hich
output o" the last stage is "ed back :C or C=;' Care"ull% compare the "eedback connection belo&
to the pre!ious ring counter'
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Digital Electronics
This #re!ersed# "eedback connection has a pro"ound e""ect upon the beha!ior o" the other&ise
similar circuits' 2ecirculating a single ) around a ring counter di!ides the input clock b% a "actor
eual to the number o" stages' 6hereas, a <ohnson counter di!ides b% a "actor eual to t&ice the
number o" stages' ,or e+ample, a @-stage ring counter di!ides b% @' . @-stage <ohnson counter
di!ides b% H'
Start a <ohnson counter b% clearing all stages to *s be"ore the "irst clock' This is o"ten done at
po&er-up time' 2e"erring to the "igure belo&, the "irst clock shi"ts three *s "rom : C. C( CC; to
the right into : C( CC CD;' The ) at CD= :the complement o" C; is shi"ted back into C.' Thus, &e
start shi"ting )s to the right, replacing the *s' 6here a ring counter recirculated a single ), the @-
stage <ohnson counter recirculates "our *s then "our )s "or an H-bit pattern, then repeats'
The abo!e &a!e"orms illustrates that multi-phase suare &a!es are generated b% a <ohnson
counter' The @-stage unit abo!e generates "our o!erlapping phases o" B*L dut% c%cle' ?o& man%
stages &ould be reuired to generate a set o" three phase &a!e"ormsK ,or e+ample, a three stage
<ohnson counter, dri!en b% a 4D* ?ert8 clock &ould generate three )3*
o
phased suare &a!es at
D* ?ert8'
The outputs o" the "lop-"lops in a <ohnson counter are eas% to decode to a single state' (elo& "or
e+ample, the eight states o" a @-stage <ohnson counter are decoded b% no more than a t&o input
gate "or each o" the states' In our e+ample, eight o" the t&o input gates decode the states "or our
e+ample <ohnson counter'
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Digital Electronics
T(e "ecade Counter
. decade counter counts "rom * to J and then resets to 8ero'
The counter output can be set to 8ero b% pulsing the reset line lo&'
The count then increments on each clock pulse until it reaches )**) :decimal J;'
6hen it increments to )*)* :decimal )*; both inputs o" the N.ND gate go high'
The result is that the N.ND output goes lo&, and resets the counter to 8ero'
D going lo& can be a C.22A 1UT signal, indicating that there has been a count o" ten'
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Digital Electronics
Binar- S-nc(ronous Counter
In the pre!ious .s%nchronous binar% counter tutorial, &e sa& that the output o" one counter stage
is connected directl% to the clock input o" the ne+t counter stage and so on along the chain, and
as a result the as%nchronous counter su""ers "rom &hat is kno&n as #5ropagation Dela%#'
?o&e!er, &ith the S%nchronous Counter, the e+ternal clock signal is connected to the clock
input o" EVE2A indi!idual "lip-"lop &ithin the counter so that all o" the "lip-"lops are clocked
together simultaneousl% :in parallel; at the same time gi!ing a "i+ed time relationship' In other
&ords, changes in the output occur in #s%nchroni8ation# &ith the clock signal' This results in all
the indi!idual output bits changing state at e+actl% the same time in response to the common
clock signal &ith no ripple e""ect and there"ore, no propagation dela%'
,ig9 (inar% @-bit S%nchronous Counter
It can be seen that the e+ternal clock pulses :pulses to be counted; are "ed directl% to each <-7
"lip-"lop in the counter chain and that both the < and 7 inputs are all tied together in toggle mode,
but onl% in the "irst "lip-"lop, "lip-"lop . :LS(; are the% connected ?I/?, logic #)# allo&ing the
"lip-"lop to toggle on e!er% clock pulse' Then the s%nchronous counter "ollo&s a predetermined
seuence o" states in response to the common clock signal, ad!ancing one state "or each pulse'
The < and 7 inputs o" "lip-"lop ( are connected to the output #C# o" "lip-"lop ., but the < and 7
inputs o" "lip-"lops C and D are dri!en "rom .ND gates &hich are also supplied &ith signals
"rom the input and output o" the pre!ious stage' I" &e enable each <-7 "lip-"lop to toggle based
on &hether or not all preceding "lip-"lop outputs :C; are #?I/?# &e can obtain the same
counting seuence as &ith the as%nchronous circuit but &ithout the ripple e""ect, since each "lip-
"lop in this circuit &ill be clocked at e+actl% the same time' .s there is no propagation dela% in
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Digital Electronics
s%nchronous counters because all the counter stages are triggered in parallel the ma+imum
operating "reuenc% o" this t%pe o" counter is much higher than that o" a similar as%nchronous
counter'
,ig9 @-bit S%nchronous Counter 6a!e"orm Timing Diagram'
(ecause this @-bit s%nchronous counter counts seuentiall% on e!er% clock pulse the resulting
outputs count up&ards "rom * : #****# ; to )B : #))))# ;' There"ore, this t%pe o" counter is also
kno&n as a @-bit S%nchronous Up Counter'
.s s%nchronous counters are "ormed b% connecting "lip-"lops together and an% number o" "lip-
"lops can be connected or #cascaded# together to "orm a #di!ide-b%-n# binar% counter, the
modulo=s or #$1D# number still applies as it does "or as%nchronous counters so a Decade
counter or (CD counter &ith counts "rom * to 3
n
-) can be built along &ith truncated seuences'
"ecade .-bit S-nc(ronous Counter
. @-bit decade s%nchronous counter can also be built using s%nchronous binar% counters to
produce a count seuence "rom * to J' . standard binar% counter can be con!erted to a decade
:decimal )*; counter &ith the aid o" some additional logic to implement the desired state
seuence' ."ter reaching the count o" #)**)#, the counter rec%cles back to #****#' 6e no& ha!e
a decade or $odulo-)* counter'
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Digital Electronics
,ig9 Decade @-bit S%nchronous Counter
The additional .ND gates detect &hen the seuence reaches #)**)#, :(inar% )*; and causes "lip-
"lop ,,4 to toggle on the ne+t clock pulse' ,lip-"lop ,,* toggles on e!er% clock pulse' Thus, the
count starts o!er at #****# producing a s%nchronous decade counter' 6e could uite easil% re-
arrange the additional .ND gates to produce other counters such as a $od-)3 Up counter &hich
counts )3 states "rom#****# to #)*))# :* to )); and then repeats making them suitable "or
clocks'
S%nchronous Counters use edge-triggered "lip-"lops that change states on either the #positi!e-
edge# :rising edge; or the #negati!e-edge# :"alling edge; o" the clock pulse on the control input
resulting in one single count &hen the clock input changes state' /enerall%, s%nchronous
counters count on the rising-edge &hich is the lo& to high transition o" the clock signal and
as%nchronous ripple counters count on the "alling-edge &hich is the high to lo& transition o" the
clock signal'
It ma% seem unusual that ripple counters use the "alling-edge o" the clock c%cle to change state,
but this makes it easier to link counters together because the most signi"icant bit :$S(; o" one
counter can dri!e the clock input o" the ne+t' This &orks because the ne+t bit must change state
&hen the pre!ious bit changes "rom high to lo& - the point at &hich a carr% must occur to the
)H
Digital Electronics
ne+t bit' S%nchronous counters usuall% ha!e a carr%-out and a carr%-in pin "or linking counters
together &ithout introducing an% propagation dela%s'
Then to summarise9
S%nchronous Counters can be made "rom Toggle or D-t%pe "lip-"lops'
The% are called s%nchronous counters because the clock input o" the "lip-"lops are
clocked &ith the same clock signal'
Due to the same clock pulse all outputs change simultaneousl%'
S%nchronous counters are also called parallel counters as the clock is "ed in parallel to
all "lip-"lops'
S%nchronous binar% counters use both seuential and combinational logic elements'
The memor% section keeps track o" the present state'
The seuence o" the count is controlled b% combinational logic'
/dvantages of S-nc(ronous Counters:
S%nchronous counters are easier to design'
6ith all clock inputs &ired together there is no inherent propagation dela%'
1!erall "aster operation ma% be achie!ed compared to .s%nchronous counters'
"ecade Counter
. decade counter is a binar% counter that is designed to count to )*)*, or )*)*3' .n ordinar% "our-
stage counter can be easil% modi"ied to a decade counter b% adding a N.ND gate as sho&n in
"igure 4-3B' Notice that ,,3 and ,,@ pro!ide the inputs to the N.ND gate' The N.ND gate
outputs are connected to the CL2 input o" each o" the ,,s'
,ig9 Decade counter'
)J
Digital Electronics
The counter operates as a normal counter until it reaches a count o" )*)*3, or )*)*' .t that time,
both inputs to the N.ND gate are ?I/?, and the output goes L16' This L16 applied to the
CL2 input o" the ,,s causes them to reset to *' 2emember "rom the discussion o" <-7 ,,s that
CL2 and 5S or 52 o!erride an% e+isting condition o" the ,,' 1nce the ,,s are reset, the count
ma% begin again' The "ollo&ing table sho&s the binar% count and the inputs and outputs o" the
N.ND gate "or each count o" the decade counter9
(IN.2A C1UNT N.ND /.TE IN5UTS N.ND /.TE 1UT5UT
MMMMMMM . ( MMMMMMM
**** * * )
***) * * )
**)* ) * )
**)) ) * )
*)** * * )
*)*) * * )
*))* ) * )
*))) ) * )
)*** * ) )
)**) * ) )
Changing the inputs to the N.ND gate can cause the ma+imum count to be changed' ,or
instance, i" ,,@ and ,,4 &ere &ired to the N.ND gate, the counter &ould count to ))**3 :)3)*;,
and then reset'
/s-nc(ronous Counter
In the pre!ious tutorial &e sa& that an .s%nchronous counter can ha!e 3n-) possible counting
states e'g' $1D-)D "or a @-bit counter, :*-)B; making it ideal "or use in ,reuenc% Di!ision' (ut
it is also possible to use the basic as%nchronous counter to construct special counters &ith
counting states less than their ma+imum output number b% "orcing the counter to reset itsel" to
8ero at a pre-determined !alue producing a t%pe o" as%nchronous counter that has truncated
seuences' Then an n-bit counter that counts up to its ma+imum modulus :3n; is called a "ull
seuence counter and a n-bit counter &hose modulus is less than the ma+imum possible is called
a truncated counter'
(ut &h% &ould &e &ant to create an as%nchronous truncated counter that is not a $1D-@,
$1D-H, or some other modulus that is eual to the po&er o" t&o' The ans&er is that &e can b%
using combinational logic to take ad!antage o" the as%nchronous inputs on the "lip-"lop' I" &e
3*
Digital Electronics
take the modulo-)D as%nchronous counter and modi"ied it &ith additional logic gates it can be
made to gi!e a decade :di!ide-b%-)*; counter output "or use in standard decimal counting and
arithmetic circuits' Such counters are generall% re"erred to as Decade Counters' . decade counter
reuires resetting to 8ero &hen the output count reaches the decimal !alue o" )*, ie' &hen DC(.
> )*)* and to do this &e need to "eed this condition back to the reset input' . counter &ith a
count seuence "rom binar% #****# :(CD > #*#; through to #)**)# :(CD > #J#; is generall%
re"erred to as a (CD binar%-coded-decimal counter because its ten state seuence is that o" a
(CD code but binar% decade counters are more common'
,ig9 .s%nchronous Decade Counter
This t%pe o" as%nchronous counter counts up&ards on each leading edge o" the input clock signal
starting "rom #****# until it reaches an output #)*)*# :decimal )*;' (oth outputs C( and CD are
no& eual to logic #)# and the output "rom the N.ND gate changes state "rom logic #)# to a
logic #*# le!el and &hose output is also connected to the CLE.2 :CL2; inputs o" all the <-7
,lip-"lops' This causes all o" the C outputs to be reset back to binar% #****# on the count o" )*'
1nce C( and CD are both eual to logic #*# the output o" the N.ND gate returns back to a logic
le!el #)# and the counter restarts again "rom #****#' 6e no& ha!e a decade or $odulo-)*
counter'
3)
Digital Electronics
"ecade Counter Trut( Table
Clock
Count
1utput bit 5attern
Decimal
Value
CD CC C( C.
) * * * * *
3 * * * ) )
4 * * ) * 3
@ * * ) ) 4
B * ) * * @
D * ) * ) B
G * ) ) * D
H * ) ) ) G
J ) * * * H
)* ) * * ) J
)) Counter 2esets its 1utputs back to Nero
"ecade Counter Timing "iagram
33
Digital Electronics
Using the same idea o" truncating counter output seuences, the abo!e circuit could easil% be
adapted to other counting c%cles be simpl% changing the connections to the .ND gate' ,or
e+ample, a scale-o"-t&el!e :modulo-)3; can easil% be made b% simpl% taking the inputs to the
.ND gate "rom the outputs at #CC# and #CD#, noting that the binar% eui!alent o" )3 is #))**#
and that output #C.# is the least signi"icant bit :LS(;' Since the ma+imum modulus that can be
implemented &ith n "lip-"lops is 3n, this means that &hen %ou are designing truncated counters
%ou should determine the lo&est po&er o" t&o that is greater than or eual to %our desired
modulus' ,or e+ample, lets sa% %ou &ish to count "rom * to 4J, or mod-@*' Then the highest
number o" "lip-"lops reuired &ould be si+, n > D gi!ing a ma+imum $1D o" D@ as "i!e "lip-
"lops &ould onl% eual $1D-43'
Then suppose &e &anted to build a #di!ide-b%-)3H# counter "or "reuenc% di!ision &e &ould
need to cascade se!en "lip-"lops since )3H > 3
G
' Using dual "lip-"lops such as the G@LSG@ &e
&ould still need "our IC=s to complete the circuit' 1ne eas% alternati!e method &ould be to use
t&o TTL G@J4=s as @-bit ripple counter0di!iders' Since )3H > )D + H, one G@J4 could be
con"igured as a #di!ide-b%-)D# counter and the other as a #di!ide-b%-H# counter' The t&o IC=s
&ould be cascaded together to "orm a #di!ide-b%-)3H# "reuenc% di!ider as sho&n'
1" course standard IC as%nchronous counters are a!ailable such as the TTL G@LSJ*
programmable ripple counter0di!ider &hich can be con"igured as a di!ide-b%-3, di!ide-b%-B or
an% combination o" both' The G@LS4J* is a !er% "le+ible dual decade dri!er IC &ith a large
number o" #di!ide-b%# combinations a!ailable ranging "orm di!ide-b%-3, @, B, )*, 3*, 3B, B*, and
)**'
34
Digital Electronics
Summari0ation
.s%nchronous Counters can be made "rom Toggle or D-t%pe "lip-"lops'
The% are called as%nchronous counters because the clock input o" the "lip-"lops are
not all dri!en b% the same clock signal'
Each output in the chain depends on a change in state "rom the pre!ious "lip-"lops
output'
.s%nchronous counters are sometimes called ripple counters because the data appears
to #ripple# "rom the output o" one "lip-"lop to the input o" the ne+t'
The% can be implemented using #di!ide-b%-n# circuits'
Truncated counters can produce an% modulus number count'
"isadvantages of /s-nc(ronous Counters
.n e+tra #re-s%nchroni8ing# output "lip-"lop ma% be reuired'
To count a truncated seuence not eual to 3n, e+tra "eedback logic is reuired'
Counting a large number o" bits, propagation dela% b% successi!e stages ma% become
undesirabl% large'
This dela% gi!es them the nickname o" #5ropagation Counters#'
Counting errors at high clocking "reuencies'
S%nchronous Counters are "aster using the same clock signal "or all "lip-"lops'
3@
Digital Electronics
+p-"o1n Counters
. circuit o" a 4-bit s%nchronous up-do&n counter and a table o" its seuence are sho&n belo&'
Similar to an as%nchronous up-do&n counter, a s%nchronous up-do&n counter also has an up-
do&n control input' It is used to control the direction o" the counter through a certain seuence'
.n e+amination o" the seuence table sho&s9
"or both the U5 and D16N seuences, C* toggles on
each clock pulse'
"or the U5 seuence, C) changes state on the ne+t clock
pulse &hen C*>)'
"or the D16N seuence, C) changes state on the ne+t
clock pulse &hen C*>*'
"or the U5 seuence, C3 changes state on the ne+t clock
pulse &hen C*>C)>)'
"or the D16N seuence, C3 changes state on the ne+t
clock pulse &hen C*>C)>*'
3B
Digital Electronics
%'" 3 Counter
6e can design the $1D 4 counter using 3 ,,s as 4 is less than @ i'e' 3
3
and greater than 3' 6e
can see directl% that as &e ha!e to reset the counter onl% a"ter 3 i'e' &hen output is 4 &e reset the
counter and hence &e need to reset onl% &hen &e ha!e C*> ) O C)>)' No& "irstl% design
$1D-@ counter using 3 ,,s and then take N.ND o" C* O C) and "eed the output to CLE.2 o"
both ,,s'
:b; 6e "irst dra& state diagram o" the counter reuired as9
.nd &e ha!e the general circuit to design the other than $1D 3
n
then &e ha!e the
general circuit as
.nd no& &e dra& a table to list the di""erent input combinations to Combinational circuit
and their corresponding output as9
C) C* 1UT5UT o" reset logic
* * )
* ) )
) * )
) ) *

3D
Digital Electronics

.nd using 7-map as
.nd hence &e get the &hole circuit "or $1D-4 counter as
3G

Digital Unit - IV

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