EEEB273 N09 - Output Stages x6

EEEB273 Electronics Analysis & Design II
Lecturer: Dr Jamaludin Bin Omar 9-1

Output Stages:
Classes of
Amplifiers
Reference: Neamen, Chapter 8
(9)
I
Learning Outcome
Able to:
Define the various classes of power
amplifiers and determine the maximum
power efficiency of each class of
amplifier.
Analyze circuit configuration of:
Class-A operation,
Class-B operation,
Class-AB operation.
Z
3
Power amplifiers in the output stage are classified
according to the percent (%) of time the output
transistors are conducting (turned on):
Class A: Output transistor is biased at a
quiescent current I
Q
and conducts for the entire
cycle of the input signal.
Class B: Output transistor conducts for only
one-half of each sine-wave input cycle.
Class AB: Output transistor biased at a small
quiescent current I
Q
, and conducts for slightly
more than half a cycle.
Class C: Output transistors conducts for less
than half a cycle.
9.0) Classes of Amplifiers
4
Figure 8.15: Collector current versus time
characteristics: (a) class-A amp, (b) class-B amp,
(c) class-AB amp, and (d) class-C amp
9.0) Classes of Amplifiers (Cont)
C CE Q
B BE C CE Q
i v P
i v i v P
+ =
b
9.1.1) Instantaneous power dissipation:
Is given by
(8.1)
Generally i
B
<< i
C
, then
(8.2)
9.1.2) Average power:
Is obtained by integrating the instantaneous
power dissipation over one cycle of the
signal. So,
(8.3)
9.1) Power Dissipation in BJT
}
=
T
C CE
Q dt i v
T
P
0
1
S
L
S
L
P
P
P
P
=
o
9.1.3) Power conversion efficiency:
Is defined as
(8.12)
where = average ac power delivered to load.
= average power supplied by PSU.
9.1) Power Dissipation in BJT (Cont)
7
Emitter follower circuit, Fig
S1 low output resistance.
Emitter follower Q
1
is biased
with a constant current source
I (supplied by transistor Q
2
).
Since i
E1
= I + i
L
I largest negative
load current
Else Q
1
cuts off, and
class-A operation no longer
maintained.
9.2) Class-A Operation (Ref: Sedra pp. 1231-1235)
9.2.1) Circuit diagram
Figure S1
8
TC is described by:
v
O
= v
i
- v
BE1
where v
BE1
depends on i
E1
and thus the load current i
L
.
9.2) Class-A Operation (Cont)
9.2.2) Transfer Characteristics (TC)
O
S
L
O
T i
v
I
R
v
I
V v +
(
(
(
(
+
= ln
Neglecting small changes
in v
BE1
the linear curve as
shown above is obtained.
9
Positive limit determined by the saturation of Q
1
:
v
Omax
= V
CC
- V
CE1sat
Negative limit depends on the values of I
Q
and R
L
:
Q
1
turns off (small R
L
): v
Omin
= -I R
L
Q
2
saturating (large R
L
): v
Omin
= -V
CC
+ V
CE2sat
Absolute lowest output voltage is when Q
2
saturating provided that:
9.2.2) Transfer Characteristics (Cont)
L
CE CC
R
V V
I
sat 2
+
I0
9.2.3) Signal Waveforms
Assume a sine-wave input is applied to the Class A emitter follower circuit.
Maximum signal waveforms in class A output stage
of Figure S1 under the condition I = V
CC
/ R
L
II
Maximum instantaneous power dissipation in
the Q
1
is V
CC
I
V
CC
I = quiescent power dissipation in Q
1
Largest amount of power is dissipated when
v
O
= 0 (no-input signal).
Q
1
must be able to withstand a continuous
power dissipation of V
CC
I since this condition
(no-input signal) can easily prevail for
prolonged periods of time.
9.2.4) Power Dissipation
IZ
Power dissipation in Q
1
depends on R
L
R
L
= (open circuit)
I
C1
= I = constant
Instantaneous power dissipation in Q
1
depends on v
O
Max. power dissipation occurs when
v
O
= -V
CC
o V
CE1
= 2V
CC
p
D1
= 2V
CC
I
o But condition is not prolonged
Average power dissipation in Q
1
is V
CC
I.
9.2.4) Power Dissipation (Cont)
I3
1
depends on R
L
(Cont)
R
L
= 0 (output short circuit) ~ dangerous!
Positive input voltage theoretically results
in infinite () load current.
Large power dissipation in Q
1
increases its
temperature causing Q
1
to burn up.
Therefore, need short circuit protection!
I4
2
Also significant in emitter follower design.
Q
2
conducts constant current I.
V
CE2
(max) = 2V
CC
(occurs when v
O
= V
CC
)
Maximum instantaneous power dissipation
in Q
2
is 2V
CC
I and condition is not prolonged.
Average power dissipation in Q
2
is V
CC
I
Ib
For the emitter follower of Figure S1, the output
voltage is assumed a sinusoid with peak value V
p
The average load power will be:
Total average supply power is:
9.2.5) Power Conversion Efficiency
( )
L
p
L
p
L
R
V
R
V
P
2
2
2
1
2 /
= =
I V P P P
CC
S S S 2 = + = +
Io
Since current in Q
2
is constant at I,
average power drawn from the negative
supply is V
CC
I (exclude other bias circuitry).
The average current in Q
1
is equal to I,
thus average power drawn from the positive
supply is V
CC
I
Therefore, power conversion efficiency
for Class A emitter follower:
9.2.5) Power Conversion Efficiency (Cont)
|
|
.
|
\
|
|
|
.
|
\
|
= =
CC
p
L
p
S
L
V
V
IR
V
P
P
4
1
I7
Since V
p
V
CC
and V
p
IR
L
, maximum
efficiency is obtained when
V
p
= V
CC
= IR
L
(max) = 1/4 25%
Low (max) Class A is rarely used in
high-power applications of more than 1W.
In practice, output voltage swing is also
limited to lower values to avoid transistor
saturation.
Typical efficiency is between 10% to 20%.
9.2.5) Power Conversion Efficiency (Cont)
I8
Example Past question
A class-A emitter follower biased with a constant-
current source is shown in the following Figure.
Study the Figure carefully. Transistor parameters
are: = 180, V
BE
= 0.7 V, and V
CE
(sat) = 0.2V.
Neglecting base currents, find:
(i) The value of I
Q
.
(ii) The maximum and minimum values of i
E1
and i
L
.
(iii) The value of R that will produce the maximum
possible output signal swing.
(iv) The conversion efficiency.
I9
Example Past question (Cont)
Z0
(i) v
O
(max) = V
+
- V
CE
(sat) = 10 0.2 = 9.8 V
I
Q
= i
L
(max) = v
O
(max) / R
L
= 9.8 / 1k = 9.8 mA
(ii) i
E1
(max) = 2 I
Q
= 19.6 mA
i
E1
(min) = 0
i
L
(max) = I
Q
= 9.8 mA
i
L
(min) = -I
Q
= -9.8 mA
(iii) R = (0 - V
BE
(-10)) / I
Q
= 9.3 / 9.8m = 949
ZI
(iv)
( ) ( )
% 3 . 16
m 294
m 02 . 48
mW 294 ) 10 ( m 8 . 9 ) 20 ( m 8 . 9
) 0 ( ) (
mW 02 . 48
) k 1 ( m 8 . 9
2
1
(max)
2
1
2 2
= = =
= + =
+ =
=
= =
+
S
L
S
Q Q
S
L
L L
L
P
P
P
V I V V I P
P
R i P
ZZ
Exercises
Fig S1,
Z3
Exercises (Cont)
Fig S1,
Fig S1,
Z4
9.3) Class-B Operation
9.3.1) Idealized Class-B Output Stage
Figure 8.18: Idealized complementary
pair of electronic devices
Fig (a): v
I
= 0, both devices
off, v
O
= 0
Fig (b): v
I
>0, device A turns
on, supply current to load.
Fig (c): v
I
<0, device B turns
on, sink current from load.
Fig (d): Voltage transfer
characteristics Unity
voltage gain.
Zb
9.3) Class-B Operation (Cont)
9.3.2) Approximate Class-B Circuit
v
I
= 0,
both Q
n
& Q
p
cut-off,
v
O
= 0
Assume V
BE
(on)=0.6V
v
O
remains 0 as long as
-0.6V v
I
+0.6V
Figure 8.19: Basic
complementary BJT
push-pull output stage.
Zo
v
I
> +0.6V, Q
n
turns on and
operates as emitter follower
I
L
is positive,
supplied thru Q
n
B-E junction of Q
p
is
reverse-biased
Figure 8.19: Basic
complementary BJT
9.3.2) Approximate Class-B Circuit (Cont)
Z7
9.3.2) Approximate Class-B Circuit (Cont)
v
I
< -0.6V, Q
p
turns on and
operates as emitter follower
Q
p
sinks I
L
, which is
negative
B-E junction of Q
n
is
reverse-biased
Figure 8.19: Basic
complementary BJT
Z8
Complementary push-
pull output stage:
Q
n
conducts during
positive cycle.
Q
p
conducts during
negative cycle.
Q
n
& Q
p
do not conduct
both at the same time.
Figure 8.19: Basic
complementary BJT
Z9
Voltage gain of emitter
follower 1.
Each transistor actually
conducts for slightly less
than half the input voltage
cycle.
Dead band: range of input
voltage where v
O
is zero
Where both transistors
are cut-off.
9.3.3) Transfer Characteristics
Figure 8.20: Voltage
transfer characteristics of
basic complementary
30
Dead band produces a
crossover distortion,
Figure 8.21.
Crossover distortion can
be virtually eliminated by
biasing both transistors
with a small quiescent
collector current when v
I
is zero (class-AB output
stage ~~ next topic!).
9.3.4) Crossover Distortion
Figure 8.21: Crossover
distortion of basic
complementary push-pull
output stage.
3I
Figure 8.22 shows the
effective dc load line for
ideal Class B output stage
(Fig 8.18), i.e. V
BE
(on)=0 V.
The Q-point is at zero
collector current, or at
cutoff for both transistors.
The quiescent power
dissipation is then zero
since p
Q
= v
CE
i
C
9.3.5) Idealized Power Efficiency
Figure 8.22: Effective load
line of class-B output stage.
3Z
Output voltage for the idealized class-B output
stage:
v
O
= V
p
sin t (8.16)
where maximum possible value of V
p
is V
CC
The instantaneous power dissipation in Q
n
is
p
Qn
= v
CEn
i
Cn
(8.17)
where the collector current is
i
Cn
= (V
p
/ R
L
) sin t for 0 t ,
and i
Cn
= 0 for t 2
9.3.5) Idealized Power Efficiency (Cont)
9.3.5.1) Average Power Dissipation
33
From Figure 8.22, C-E voltage can be written as:
v
CEn
= V
CC
- V
p
sin t (8.19)
Therefore, the total instantaneous power
dissipation in Q
n
is
p
Qn
=(V
CC
-V
p
sint)(V
p
/R
L
)sint for 0 t ,
and p
Qn
= 0 for t 2
The average power dissipation is therefore
(8.21)
9.3.5.1) Average Power Dissipation (Cont)
L
p
L
p CC
Qn
R
V
R
V V
P
4
2
=
34
The average power dissipation in Q
p
is exactly
the same as that for Q
n
because of symmetry.
A plot of the average power dissipation in each
transistor as a function of V
p
is shown in Fig 8.23
Figure 8.23: Average power
dissipation in each transistor
versus peak output voltage
for class-B output stage.
CC
P
p
L
CC
Qn
V
V
R
V
P
Qn
2
(max)
(max)
2
2
=
=
3b
The power dissipation first increases with
increasing output voltage, reaches a maximum at
V
p
=2V
CC
/, and finally decreases with increasing V
p
.
The maximum average power dissipation is
given by
(8.22)
which occurs when
(8.23)
|
|
.
|
\
|
= =
=
+
L
p
CC
S S
L p
L
p
L
R
V
V P P
R V
R
V
P
) /(
2
1
2
3o
The average power delivered to the load is
(8.24)
Since the average current supplied by each PS is
The average power supplied by each PS
source is therefore
(8.25)
9.3.5.2) Power Conversion Efficiency ()
CC
p
L
p
CC
L
p
L
p
CC
S
V
V
R
V
V
R
V
R
V
V P
4
2
2
1
2
2
=
|
|
.
|
\
|
=
|
|
.
|
\
|
=
37
The total average power supplied by the two
sources is
(8.26)
The conversion efficiency (from 8.12) is then
(8.27)
9.3.5.2) Power Conversion Efficiency () (Cont)
38
The maximum possible efficiency occurs when
V
CC
=V
p
is
(8.28)
This maximum efficiency value is substantially
larger than of standard class-A amplifier.
From (8.24), maximum possible average power
that can be delivered to the load is
(8.29)
% 5 . 78
4
(max) =

L
CC
L
R
V
P
2
2
1
(max) =
39
Practically, the conversion efficiency obtained is
less than the 78.5% due to other circuit losses,
and because V
p
< V
CC
to avoid transistor
saturation.
Conversion efficiency at maximum transistor
power dissipation (i.e. V
p
= 2 V
cc
/) is
% 50
2
1 2
.
4
.
4
= |
.
|
\
|
|
|
.
|
\
|
= =
CC
CC
p
CC
V
V
V
V
40
An idealized class B output stage is to deliver 35 W
of average power to a 25 load for a symmetrical
input sine wave. The maximum output voltage is
required to be 80% of the power supply voltage.
Find the power supply voltage.
With that power supply voltage, calculate the
value of the power conversion efficiency .
4I
P
L
* = 35 W, R
L
= 25
P
L
* = (1/2)(V
2
P
/R
L
) 35=(1/2)(V
2
P
/25)
V
P
= 41.83 V = 0.8 V
CC
V
CC
= V
P
/ 0.8 = 52.3 V
P
S
* = (2 V
CC
)(V
P
/R
L
) = (2x52.3)(41.83/(25))
P
S
* = 55.7 W
= P
L
*/ P
S
* = 35/55.7 = 0.628 or 62.8%
4Z
9.4) Class-AB Operation
9.4.1) Circuit diagram
Crossover distortion can be virtually
eliminated by applying a small
quiescent bias on each output
transistor, for a zero input signal.
This creates a class-AB output
stage as shown in Figure 8.24.
If Q
n
& Q
p
are matched: For v
I
= 0,
V
BEn
= V
EBp
= V
BB
/ 2,
and v
O
= 0
Quiescent collector current
I
CQ
= i
Cn
= i
Cp
= I
S
exp(V
BB
/ 2V
T
)
Figure 8.24:
Bipolar class-AB
output stage
43
9.4) Class-AB Operation (Cont)
9.4.2) Circuit operation
As v
I
, v
BEn
and v
O

Q
n
operates as emitter follower, supplying i
L
to R
L
Output voltage is
v
O
= v
I
+ V
BB
/ 2 - v
BEn
Collector current of Q
n
i
Cn
= i
L
+ i
Cp
Since i
Cn
must to supply i
L
, v
BEn
. As V
BB
constant, v
BEn
causes v
EBp
, hence i
Cp
.
As v
I
goes negative, v
BEp
and v
O
Q
p
sinks i
L
from R
L
Since i
Cp
, v
EBp
, causes v
BEn
, hence i
Cn
.
44
9.4.3) Characteristics
Figure 8.25:
(a) Voltage transfer curve
(b) Sinusoidal input signal
(c) Collector currents
(d) Output current
Figure 8.25 shows voltage transfer characteristics
for the class-AB output stage.
If v
BEn
and v
EBp
do not
change significantly,
then the voltage gain is
essentially unity.
Each Q conducts for
more than cycle.
2
ln 2 ln ln
CQ Cp Cn
S
CQ
T
S
Cp
T
S
Cn
T
BB EBp BEn
I i i
I
I
V
I
i
V
I
i
V
V v v
=
|
|
.
|
\
|
=
|
|
.
|
\
|
+
|
|
.
|
\
|
= +
4b
9.4.4) Relationship between i
Cp
and i
Cn
It is known
which can be written as
Combining terms, yields
(8.35)
The product of i
Cn
and i
Cp
is a constant.
Therefore, if i
Cn
then i
Cp
, but does not go to 0.
4o
Cp
and i
Cn
(Cont)
For the class AB output stage in Figure 8.24, given
that V
CC
=15 V and V
BB
=1.40 V. R
L
=1 k. The
reverse-bias saturation current for the transistors,
I
S
=2 x 10
-15
A. Assume >> 1.
For the output voltage v
O
= -10V:
Determine i
L
, i
Cn
, and i
Cp
.
Find the power dissipated in transistor Q
n
.
47
Cp
and i
Cn
(Cont)
v
O
= -10V = i
L
R
L
i
L
= v
O
/R
L
= (-10V) /(1k) = -10 mA
Therefore, Q
p
is conducting and Q
n
is OFF.
i
L
i
Cp
= I
S
exp(V
EBP
/V
T
)
V
EBP
= V
T
ln(i
Cp
/ I
S
) = 26m ln(10m/ 2x10
-15
)
V
EBP
= 0.7603 V
V
BEN
= V
BB
- V
EBP
= 1.4 - 0.7603 = 0.6397 V
i
Cn
= I
S
exp(V
BEN
/V
T
) = 96.9 A
48
Cp
and i
Cn
(Cont)
i
Cn
= i
Cp
+ i
L
Actual value of i
Cp
= i
Cn
i
L
= 96.9 - (-10m)
i
Cp
= 10.0969 mA
P
Qn
= i
Cn
V
CEn
V
CEn
= +V
CC
- v
O
= +15 (-10) = 25 V
P
Qn
= (96.9 A)(25 V) = 2.42 mW
49
Example 2 Past question
For the class AB output stage in Figure 8.24,
given that V
CC
=12 V and V
BB
=1.20 V. R
L
=100 .
The reverse-bias saturation current for the
transistors, I
S
=4 x 10
-13
A. Assume >> 1.
b0
Example 2 Past question (Cont)
i. For the case of the input voltage v
I
= 0, calculate the
quiescent collector currents, i
Cn
and i
Cp
, and the
power dissipated in transistors Q
p
and Q
n
.
ii. What is the maximum amplitude of the output
voltage, v
O
, and the corresponding maximum power
that can be delivered to the load?
iii. For the case of v
O
=-4 sin t V, determine i
L
, i
Cn
, i
Cp
,
and v
I
.
bI
i.
mW m P
V v
i v P P
mA e x i
e I i i
Q
CE
C CE Qp Qn
Cn
V
V
S Cp Cn
T
BB
52 . 50 ) 210 . 4 )( 12 (
12
210 . 4 ) )( 10 4 (
) 026 . 0 )( 2 (
2 . 1
13
2
= =
=
= =
= =
= =
(
bZ
ii.
W
R
V
P
V v
L
p
L
O
72 . 0
100
12
) 5 . 0 (
2
1
12
2
2
(max)
(max)
=
|
|
.
|
\
|
= =
=
b3
iii.
At v
O
= -4 V peak, the load current flows into Q
p
,
thus i
Cp
i
L
= mA
i
Cn
= 0
v
I
= -4.0585 sin t V
t
t
R
v
L
O
sin 40
100
sin 4
=
=
2
BB
EBp O I
V
v v v + =
0585 . 4
2
2 . 1
6585 . 0 4
6585 . 0
10 4
40
ln ) 026 . 0 ( ln
13
= + =
=
(
=
(
I
Cp
T EBp
v
V
x
m
Is
i
V v
b4
9.4.5) Comparison between class-AB and class-B
In class-AB, quiescent collector current I
CQ
exists
even for a zero input signal. Hence:
The average power supplied by each source
and the average power dissipated in each
transistor are larger than class-B
The will be less than an idealized class-B
The required power handling capability of Qs
in class-AB will be slightly larger than class-B.
Since I
CQ
is usually small compared to I
p
, the
increase in power dissipation is not great.
bb
9.4.5) Comparison between class-AB and class-B (Cont)
However, the advantage of eliminating
crossover distortion greatly overweighs the
disadvantage of reduced and increased
power dissipation.
bo
9.4.6) Biasing of Class-AB
9.4.6.1) With Diode Biasing
Figure 8.31 shows the V
BB
voltage established by
voltage drops across diodes D
1
and D
2
.
A constant current I
Bias
establishes the required
voltage across D
1
and D
2
(pair of diodes or diode-
connected transistors)
Since D
1
and D
2
may not be
matched to Q
n
and Q
p
, hence
I
CQ
may not be equal to I
Bias
Figure 8.31: Quiescent
bias established by diodes
b7
9.4.6) Biasing of Class-AB (Cont)
9.4.6.1) With Diode Biasing (Cont)
Problem: V
BB
is not constant
As v
I
, v
O
so i
Cn
, hence i
Bn
i
Bn
is supplied by I
Bias
, the current
through D
1
and D
2
, hence V
BB
slightly
Since V
BB
does not remain constant in
this circuit, previous relationship for
collector currents i
Cn
i
Cp
= (I
CQ
)
2
is not
precisely valid for this situation
b8
Design Example 8.9
Objective: Design the class-AB output stage in
Figure 8.31 to meet specific design criteria.
Assume I
SD
= 3 x 10
-14
A for D
1
and D
2
, I
SQ
=
10
-13
for Q
n
and Q
p
, and
n
=
p
= 75. Let R
L
= 8 .
The average power delivered to the load is to be 5
W. The peak output voltage is to be no more than
80 percent of V
CC
, and the minimum value of diode
current I
D
is to be no less than 5 mA.
b9
Design Example 8.9 (Cont)
P
L
* = (1/2)(V
2
P
/R
L
)
V
P
= sqrt[2 R
L
P
L
*] = sqrt[2(8)(5)] = 8.94 V
The supply voltage must then be
V
CC
= V
P
/ 0.8 = 8.94/0.8 = 11.2 V
At this peak output voltage, the emitter current of
Q
n
is approximately equal to the load current, or
i
En
i
L
(max) = V
P
(max)/ R
L
= 8.94/8 = 1.12 A
and the base current is
i
Bn
= i
En
/ (1+
n
) = 1.12/76 = 14.7 mA
o0
For a minimum I
D
= 5 mA, we can choose I
Bias
= 20
mA. For a zero input signal, neglecting base
currents, we find that
V
BB
= 2V
T
ln(I
D
/ I
SD
)
= 2(0.026) ln(20x10
-3
/3x10
-14
) = 1.416V
The quiescent collector currents are then
I
CQ
= I
SQ
exp(V
BB
/ 2 V
T
)
= 10
-13
exp(1.416/2(0.026)) = 67.0 mA
oI
For v
O
= 8.94 V and I
L
= 1.12 A, the base current is
i
Bn
= 14.7 mA, and
i
D
= i
Bias
- i
Bn
= 5.3 mA
The new value of V
BB
is then
V
BB
= 2V
T
ln(I
D
/ I
SD
)
= 2(0.026)ln(5.3x10
-3
/3x10
-14
)
= 1.347V
oZ
The B-E voltage of Q
n
is
v
BEn
= V
T
ln(i
Cn
/ I
SQ
)
= (0.026) ln(1.12/10
-13
) = 0.781V
The E-B voltage of Q
p
is then
v
EBp
= V
BB
- v
BEn
= 1.347-0.781 = 0.566V
and
i
Cp
= I
SQ
exp(v
EBp
/ V
T
)
= 10
-13
exp(0.566/0.026) = 0.285 mA
o3
9.4.6.2) Using the V
BE
Multiplier
Figure 8.32 shows voltage V
BB
established by Q
1
,
R
1
and R
2
, biased by constant-current source I
Bias
Neglecting the base current
in Q
1
, then
I
R
= V
BE1
/ R
2
(8.48)
and voltage V
BB
is
V
BB
= I
R
( R
1
+ R
2
)
= V
BE1
(1 + R
1
/ R
2
)
V
BB
is a multiplication of
V
BE1
, circuit is V
BE
Multiplier
Figure 8.32: Class-AB with V
BE
Multiplier bias circuit
o4
BE
Multiplier (Cont)
A fraction of I
Bias
flows through Q
1
, so that
V
BE1
= V
T
ln (I
C1
/ I
S
) (8.50)
Also, can neglect i
Bn
and i
Bp
because i
Cn
and
i
Cp
are normally small. Current I
Bias
divides
between I
R
and I
C1
, satisfying both Equations
(8.48) and (8.50).
I
C1
= I
Bias
- I
R
ob
BE
Multiplier (Cont)
Advantage of V
BE
Multiplier:
Design flexibility as the multiplication factor
is controlled by adjusting R
1
and R
2
V
BB
is more constant
As v
I
, v
O
so i
Cn
, hence i
Bn

Now I
C1
, however the logarithmic
dependence of V
BE1
on I
C1
means V
BE1
and
V
BB
remains constant
oo
Larger circuits
o7
9.2) Class-A Operation (Ref: Sedra pp. 1231-1235)
Circuit diagram Transfer Characteristics
Figure S1
o8
9.2.3) Signal Waveforms
Assume a sine-wave input is applied to the Class A emitter follower circuit.
Maximum signal waveforms in class A output stage
of Figure S1 under the condition I = V
CC
/ R
L
o9
Example (Cont)
70
9.3) Class-B Operation
9.3.1) Idealized Class-B Output Stage
Figure 8.18: Idealized complementary
pair of electronic devices
Fig (a): v
I
= 0, both devices
off, v
O
= 0
Fig (b): v
I
>0, device A turns
on, supply current to load
Fig (c): v
I
<0, device B turns
on, sink current from load
Fig (d): Voltage transfer
characteristics Unity
voltage gain
7I
Figure 8.20: Voltage transfer
characteristics
Figure 8.19: Basic Class-B circuit
7Z
9.4) Class-AB Operation
Figure 8.24:
Bipolar class-AB
output stage
Figure 8.25: (a) Voltage transfer curve
(b) Sinusoidal input signal (c) Collector
currents (d) Output current
73
9.4.6) Biasing of Class-AB
Figure 8.31: Quiescent
bias established by diodes
Figure 8.32: Class-AB with
V
BE
Multiplier bias circuit

EEEB273 N09 - Output Stages x6

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EEEB273 N09 - Output Stages x6

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EEEB273 Electronics Analysis & Design II

Lecturer: Dr Jamaludin Bin Omar 9-1

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