PROBLEM STATEMENT: Write VHDL code and test bench, synthesis, simulate

and down load in to PLD to sense physical parameter such as

temperature/pressure/flow etc., convert in to digital using ADC, and interface
to PLD and display.

OBJECTIVE:
1. To understand the concept of ADC interfacing
2. To understand the concept of converting physical parameters into digital
and display it.

THEORY:
BLOCK DIAGRAM:





Fig: 1.1 Block diagram of temperature/pressure/flow converter into digital

This block diagram is used to convert any physical quantity like temperature,
pressure or flow into digital. The input to the system is physical quantity such as
temperature, pressure or flow such quantity is called as input measurand. With
the help of transducer converts the mesurand into a electrical signal such as
voltage or current. Signal conditioner processes the transducer output signal and
makes compatible for control, record or display with the help of analog to digital
converter.

ADC INTERFACING:
ADC 0808 is an 8 bit successive approximation ADC. This chip has 8channel
along with multiplexer. The channel select has address lines A, B, C. We can use
channel 0 as input thus. Address lines A, B, C are connected to PB0, PB1 &PB2
for selecting channel 0. The ALE pin is connected to thePC6. At the time of power
on the valid channel address is latched at the rising edge of the ALE signal. ADC
0809 has an START on Conversion pin. A positive going pulse of short duration,
is applied to this pin this pin starts the A/D conversion process. When
conversion process is complete then ADC send EOC signal which is connected to
the PC1 pin which indicates the end of conversion. The OE should always be
high, when data is to be read. The port C upper and port B are defined in the
output mode, where as port C lower of 8255 is configured in input mode. The
ASSIGNMENT NO.1
TITLE: Synthesis, simulate and down temperature/pressure/flow
etc., convert in to digital using ADC, interface to PLD and display.


Sensor Signal
conditioner
ADC Linearizer Digital
Display
Page 2

data is read through port B of 8255. Below fig. shows the interfacing diagram of
ADC 0808 with 8086. & timing diagram of ADC


Fig:1.2 ADC interfacing Diagram


ALGORITHM:

SCHEMATIC DIAGRAM:

I/O PORTS DETAILS:

SYNTHESIS REPORT:

TEST BENCH WAVEFORMS:


FAQs:
1. Explain dual slope and successive approximation method of ADC in details
2. Define VHDL syntax for
Page 3

A) Entity
B) Architecture
C) Component
D) Process



CONCLUSION:






























Page 4






PROBLEM STATEMENT: Write VHDL code and test bench, synthesis, simulate
and down load in to PLD to generate ramp/square waveform using DAC

OBJECTIVE:
1. To understand the concept of square wave using DAC 0808/0809 and
observe wave on CRO.
2. To understand the concept of Ramp wave using DAC 0808/0809 and
observe wave on CRO.

THEORY:
BLOCK DIAGRAM:

Clock

Reset



Fig.2.1: Block diagram of DAC converter

This system generates square wave and Ramp wave using Digital to Analog
Converter (DAC).This DAC accepts 8 bits of input data and generates the square
wave and Ramp wave. The logic of the wave generator is written in VHDL that
produces the 8 bit digital outputs which is then applied to the input to DAC
module by interfacing ADC-DAC add on card. The DAC output is then applied
to the CRO to check square wave and Ramp wave.

1. Square Wave Variable Duty Cycle and Frequency:

To generate square wave we will output FFH and then 00H on port A of 8255.
The output of 8255 (port A) is compulsory connected to the DAC 0808. To vary
the duty cycle it is necessary to vary Ton and Toff time. Variation in Duty cycle
will automatically change the frequency as,
Duty cycle = Ton/(Ton+Toff) = Ton/T frequency
ASSIGNMENT NO.2
TITLE: Synthesis, simulate and down load in to PLD to generate
ramp/square waveform using DAC


Frequency
generator
ADC-DAC
Add- On card

CRO
Page 5

To change time period the Delay between the two outputs (FFH for high output
and 00H for low output) should be change. Below fig shows the interfacing
diagram of DAC 0808 with 8086 & pin configuration of IC 0808
Fig. 2.2: 8bit DAC0808 D/A converter
3. Ramp Wave:

To generate ramp wave output 00H to FFH with some delay after every step
and then immediately output 00H. To obtain ramp wave with reverse direction
then, output above sequence in reverse manner. To obtain ramp wave in
forward direction, initialize, AL = 00H, otherwise AL = FFH for reverse
direction.

ALGORITHM:

SCHEMATIC DIAGRAM:

I/O PORTS DETAILS:

SYNTHESIS REPORT:

TEST BENCH WAVEFORMS:

FAQ:
1. What is digital to analog converter explain with different methods and IC
number.
2. Write a short notes on layout rules.


CONCLUSION:


Page 6






PROBLEM STATEMENT: Write VHDL code and test bench, synthesis,
simulate and down load in to PLD to design lift/traffic light controller.

OBJECTIVE:
1. To understand the concept of finite state machine for 2 lane or 4 lane
traffic light controller.
2. To understand the implementation of state model with the help of
FPGA module.

THEORY:

SYSTEM DESCRIPTION AND BLOCK DIAGRAM:

The traffic light controller is for an intersection between a main street and a side
street for four ways of signal. And for all side contains red, yellow and green
signal light. The operating sequence of this intersection begins with the main
street having a green light turn on to run traffic, next light turns yellow for ready
to stop and then turned red for stop the traffic while simultaneously turning on
the side street green light. The side street is green for running the traffic under
normal circumstances. This cycle repeats continuously.

clock

Reset




R1 G1Y1 R2G2Y2 R3G3 Y3 R4 G4 Y4

Fig. 3.1: Block diagram of traffic light controller
ALGORITHM:

FINITE STATE MACHINE:

STATE DIAGRAM:
ASSIGNMENT NO.3
TITLE: Synthesis, simulate and down load in to PLD to design
lift/traffic light controller.

Traffic light controller
Page 7

SCHEMATIC DIAGRAM:

I/O PORTS DETAILS:

SYNTHESIS REPORT:

TEST BENCH WAVEFORMS:

FAQ:
1. What is function and procedure? Describe it with VHDL example.
2. Explain VLSI design flow.


CONCLUSION: