Serial and UART Tutorial

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Serial and UART Tutorial
1. The UART: What it is and how it works
Copyright 1996 Frank Durda IV <uhclem@FreeBSD.org>, All Rights Reserved. 1 !anuary
1996.
The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of the
serial communications subsystem of a computer. The UART takes bytes of data and transmits the
individual bits in a seuential fashion. At the destination! a second UART re"assembles the bits into
complete bytes.
#erial transmission is commonly used $ith modems and for non"net$orked communication
bet$een computers! terminals and other devices.
There are t$o primary forms of serial transmission% #ynchronous and Asynchronous. &ependin' on
the modes that are supported by the hard$are! the name of the communication sub"system $ill
usually include a A if it supports Asynchronous communications! and a S if it supports #ynchronous
communications. (oth forms are described belo$.
#ome common acronyms are%
UART Universal Asynchronous Receiver/Transmitter
U#ART Universal #ynchronous"Asynchronous Receiver/Transmitter
1.1. Synchronous Serial Transmission
#ynchronous serial transmission reuires that the sender and receiver share a clock $ith one
another! or that the sender provide a strobe or other timin' si'nal so that the receiver kno$s $hen to
)read* the next bit of the data. +n most forms of serial #ynchronous communication! if there is no
data available at a 'iven instant to transmit! a fill character must be sent instead so that data is
al$ays bein' transmitted. #ynchronous communication is usually more efficient because only data
bits are transmitted bet$een sender and receiver! and synchronous communication can be more
costly if extra $irin' and circuits are reuired to share a clock si'nal bet$een the sender and
receiver.
A form of #ynchronous transmission is used $ith printers and fixed disk devices in that the data is
sent on one set of $ires $hile a clock or strobe is sent on a different $ire. ,rinters and fixed disk
devices are not normally serial devices because most fixed disk interface standards send an entire
$ord of data for each clock or strobe si'nal by usin' a separate $ire for each bit of the $ord. +n the
,- industry! these are kno$n as ,arallel devices.
The standard serial communications hard$are in the ,- does not support #ynchronous operations.
This mode is described here for comparison purposes only.
1.2. Asynchronous Serial Transmission
Asynchronous transmission allo$s data to be transmitted $ithout the sender havin' to send a clock
si'nal to the receiver. +nstead! the sender and receiver must a'ree on timin' parameters in advance
and special bits are added to each $ord $hich are used to synchroni.e the sendin' and receivin'
units.
/hen a $ord is 'iven to the UART for Asynchronous transmissions! a bit called the 0#tart (it0 is
added to the be'innin' of each $ord that is to be transmitted. The #tart (it is used to alert the
receiver that a $ord of data is about to be sent! and to force the clock in the receiver into
synchroni.ation $ith the clock in the transmitter. These t$o clocks must be accurate enou'h to not
have the freuency drift by more than 123 durin' the transmission of the remainin' bits in the
$ord. (This reuirement $as set in the days of mechanical teleprinters and is easily met by modern
electronic euipment.)
After the #tart (it! the individual bits of the $ord of data are sent! $ith the 4east #i'nificant (it
(4#() bein' sent first. 5ach bit in the transmission is transmitted for exactly the same amount of
time as all of the other bits! and the receiver )looks* at the $ire at approximately half$ay throu'h
the period assi'ned to each bit to determine if the bit is a 1 or a 0. 6or example! if it takes t$o
seconds to send each bit! the receiver $ill examine the si'nal to determine if it is a 1 or a 0 after
one second has passed! then it $ill $ait t$o seconds and then examine the value of the next bit! and
so on.
The sender does not kno$ $hen the receiver has )looked* at the value of the bit. The sender only
kno$s $hen the clock says to be'in transmittin' the next bit of the $ord.
/hen the entire data $ord has been sent! the transmitter may add a ,arity (it that the transmitter
'enerates. The ,arity (it may be used by the receiver to perform simple error checkin'. Then at
least one #top (it is sent by the transmitter.
/hen the receiver has received all of the bits in the data $ord! it may check for the ,arity (its (both
sender and receiver must a'ree on $hether a ,arity (it is to be used)! and then the receiver looks for
a #top (it. +f the #top (it does not appear $hen it is supposed to! the UART considers the entire
$ord to be 'arbled and $ill report a 6ramin' 5rror to the host processor $hen the data $ord is read.
The usual cause of a 6ramin' 5rror is that the sender and receiver clocks $ere not runnin' at the
same speed! or that the si'nal $as interrupted.
Re'ardless of $hether the data $as received correctly or not! the UART automatically discards the
#tart! ,arity and #top bits. +f the sender and receiver are confi'ured identically! these bits are not
passed to the host.
+f another $ord is ready for transmission! the #tart (it for the ne$ $ord can be sent as soon as the
#top (it for the previous $ord has been sent.
(ecause asynchronous data is )self synchroni.in'*! if there is no data to transmit! the transmission
line can be idle.
1.3. Other UART Functions
+n addition to the basic 7ob of convertin' data from parallel to serial for transmission and from serial
to parallel on reception! a UART $ill usually provide additional circuits for si'nals that can be used
to indicate the state of the transmission media! and to re'ulate the flo$ of data in the event that the
remote device is not prepared to accept more data. 6or example! $hen the device connected to the
UART is a modem! the modem may report the presence of a carrier on the phone line $hile the
computer may be able to instruct the modem to reset itself or to not take calls by raisin' or lo$erin'
one more of these extra si'nals. The function of each of these additional si'nals is defined in the
5+A R#898"- standard.
1.. The RS232!" and #.2 Standards
+n most computer systems! the UART is connected to circuitry that 'enerates si'nals that comply
$ith the 5+A R#898"- specification. There is also a --+TT standard named :.8; that mirrors the
specifications included in R#898"-.
1..1. RS232!" $it Assi%nments &'arks and S(aces)
+n R#898"-! a value of 1 is called a Mark and a value of 0 is called a Space. /hen a
communication line is idle! the line is said to be )<arkin'*! or transmittin' continuous 1 values.
The #tart bit al$ays has a value of 0 (a #pace). The #top (it al$ays has a value of 1 (a <ark). This
means that there $ill al$ays be a <ark (1) to #pace (2) transition on the line at the start of every
$ord! even $hen multiple $ord are transmitted back to back. This 'uarantees that sender and
receiver can resynchroni.e their clocks re'ardless of the content of the data bits that are bein'
transmitted.
The idle time bet$een #top and #tart bits does not have to be an exact multiple (includin' .ero) of
the bit rate of the communication link! but most UARTs are desi'ned this $ay for simplicity.
+n R#898"-! the 0<arkin'0 si'nal (a 1) is represented by a volta'e bet$een "8 :&- and "18 :&-!
and a 0#pacin'0 si'nal (a 0) is represented by a volta'e bet$een 2 and =18 :&-. The transmitter is
supposed to send =18 :&- or "18 :&-! and the receiver is supposed to allo$ for some volta'e loss
in lon' cables. #ome transmitters in lo$ po$er devices (like portable computers) sometimes use
only => :&- and "> :&-! but these values are still acceptable to a R#898"- receiver! provided that
the cable len'ths are short.
1..2. RS232!" $reak Si%nal
R#898"- also specifies a si'nal called a Break! $hich is caused by sendin' continuous #pacin'
values (no #tart or #top bits). /hen there is no electricity present on the data circuit! the line is
considered to be sendin' Break.
The Break si'nal must be of a duration lon'er than the time it takes to send a complete byte plus
#tart! #top and ,arity bits. <ost UARTs can distin'uish bet$een a 6ramin' 5rror and a (reak! but
if the UART cannot do this! the 6ramin' 5rror detection can be used to identify (reaks.
+n the days of teleprinters! $hen numerous printers around the country $ere $ired in series (such as
ne$s services)! any unit could cause a Break by temporarily openin' the entire circuit so that no
current flo$ed. This $as used to allo$ a location $ith ur'ent ne$s to interrupt some other location
that $as currently sendin' information.
+n modern systems there are t$o types of (reak si'nals. +f the (reak is lon'er than 1.? seconds! it is
considered a 0<odem (reak0! and some modems can be pro'rammed to terminate the conversation
and 'o on"hook or enter the modems@ command mode $hen the modem detects this si'nal. +f the
(reak is smaller than 1.? seconds! it si'nifies a &ata (reak and it is up to the remote computer to
respond to this si'nal. #ometimes this form of (reak is used as an Attention or +nterrupt si'nal and
sometimes is accepted as a substitute for the A#-++ -ANTRA4"- character.
<arks and #paces are also euivalent to )Boles* and )No Boles* in paper tape systems.
*ote:
(reaks cannot be 'enerated from paper tape or from any other byte value! since bytes are al$ays
sent $ith #tart and #top bit. The UART is usually capable of 'eneratin' the continuous #pacin'
si'nal in response to a special command from the host processor.
1..3. RS232!" +T, and +", +e-ices
The R#898"- specification defines t$o types of euipment% the &ata Terminal 5uipment (&T5)
and the &ata -arrier 5uipment (&-5). Usually! the &T5 device is the terminal (or computer)! and
the &-5 is a modem. Across the phone line at the other end of a conversation! the receivin' modem
is also a &-5 device and the computer that is connected to that modem is a &T5 device. The &-5
device receives si'nals on the pins that the &T5 device transmits on! and vice versa.
/hen t$o devices that are both &T5 or both &-5 must be connected to'ether $ithout a modem or
a similar media translator bet$een them! a NU44 modem must be used. The NU44 modem
electrically re"arran'es the cablin' so that the transmitter output is connected to the receiver input
on the other device! and vice versa. #imilar translations are performed on all of the control si'nals
so that each device $ill see $hat it thinks are &-5 (or &T5) si'nals from the other device.
The number of si'nals 'enerated by the &T5 and &-5 devices are not symmetrical. The &T5
device 'enerates fe$er si'nals for the &-5 device than the &T5 device receives from the &-5.
1... RS232!" .in Assi%nments
The 5+A R#898"- specification (and the +TU euivalent! :.8;) calls for a t$enty"five pin connector
(usually a &(8>) and defines the purpose of most of the pins in that connector.
+n the +(< ,ersonal -omputer and similar systems! a subset of R#898"- si'nals are provided via
nine pin connectors (&(C). The si'nals that are not included on the ,- connector deal mainly $ith
synchronous operation! and this transmission mode is not supported by the UART that +(< selected
for use in the +(< ,-.
&ependin' on the computer manufacturer! a &(8>! a &(C! or both types of connector may be used
for R#898"- communications. (The +(< ,- also uses a &(8> connector for the parallel printer
interface $hich causes some confusion.)
(elo$ is a table of the R#898"- si'nal assi'nments in the &(8> and &(C connectors.
+$2/
RS232!"
.in
+$0 1$'
." .in
,1A "ircuit
Sym2ol
""1TT
"ircuit
Sym2ol
"ommon
*ame
Si%nal
Source
+escri(tion
1 " AA 121 ,D/6D "
6rame/,rotective
Dround
8 9 (A 129 T& &T5 Transmit &ata
9 8 (( 12; R& &-5 Receive &ata
; E -A 12> RT# &T5 Reuest to #end
> F -( 12? -T# &-5 -lear to #end
? ? -- 12E &#R &-5 &ata #et Ready
E > A: 128 #D/DN& " #i'nal Dround
F 1 -6 12C &-&/-& &-5 &ata -arrier &etect
C " " " " " Reserved for Test
12 " " " " " Reserved for Test
11 " " " " " Reserved for Test
18 " -+ 188 #R4#& &-5
#ec. Recv. 4ine
#i'nal &etector
19 " #-( 181 #-T# &-5
#econdary -lear to
#end
1; " #(A 11F #T& &T5 #econdary Transmit
+$2/
RS232!"
.in
+$0 1$'
." .in
,1A "ircuit
Sym2ol
""1TT
"ircuit
Sym2ol
"ommon
*ame
Si%nal
Source
+escri(tion
&ata
1> " &( 11; T#5T &-5
Trans. #i'. 5lement
Timin'
1? " #(( 11C #R& &-5
#econdary Received
&ata
1E " && 11> R#5T &-5
Receiver #i'nal
5lement Timin'
1F " " 1;1 4AA, &T5 4ocal 4oopback
1C " #-A 182 #R# &T5
#econdary Reuest
to #end
82 ; -& 12F.8 &TR &T5
&ata Terminal
Ready
81 " " " R&4 &T5
Remote &i'ital
4oopback
88 C -5 18> R+ &-5 Rin' +ndicator
89 " -B 111 &#R# &T5
&ata #i'nal Rate
#elector
8; " &A 119 T#5T &T5
Trans. #i'. 5lement
Timin'
8> " " 1;8 " &-5 Test <ode
1./. $its3 $aud and Sym2ols
(aud is a measurement of transmission speed in asynchronous communication. (ecause of
advances in modem communication technolo'y! this term is freuently misused $hen describin'
the data rates in ne$er devices.
Traditionally! a (aud Rate represents the number of bits that are actually bein' sent over the media!
not the amount of data that is actually moved from one &T5 device to the other. The (aud count
includes the overhead bits #tart! #top and ,arity that are 'enerated by the sendin' UART and
removed by the receivin' UART. This means that seven"bit $ords of data actually take 12 bits to be
completely transmitted. Therefore! a modem capable of movin' 922 bits per second from one place
to another can normally only move 92 E"bit $ords if ,arity is used and one #tart and #top bit are
present.
+f F"bit data $ords are used and ,arity bits are also used! the data rate falls to 8E.8E $ords per
second! because it no$ takes 11 bits to send the ei'ht"bit $ords! and the modem still only sends 922
bits per second.
The formula for convertin' bytes per second into a baud rate and vice versa $as simple until error"
correctin' modems came alon'. These modems receive the serial stream of bits from the UART in
the host computer (even $hen internal modems are used the data is still freuently seriali.ed) and
converts the bits back into bytes. These bytes are then combined into packets and sent over the
phone line usin' a #ynchronous transmission method. This means that the #top! #tart! and ,arity
bits added by the UART in the &T5 (the computer) $ere removed by the modem before
transmission by the sendin' modem. /hen these bytes are received by the remote modem! the
remote modem adds #tart! #top and ,arity bits to the $ords! converts them to a serial format and
then sends them to the receivin' UART in the remote computer! $ho then strips the #tart! #top and
,arity bits.
The reason all these extra conversions are done is so that the t$o modems can perform error
correction! $hich means that the receivin' modem is able to ask the sendin' modem to resend a
block of data that $as not received $ith the correct checksum. This checkin' is handled by the
modems! and the &T5 devices are usually una$are that the process is occurrin'.
(y stripin' the #tart! #top and ,arity bits! the additional bits of data that the t$o modems must
share bet$een themselves to perform error"correction are mostly concealed from the effective
transmission rate seen by the sendin' and receivin' &T5 euipment. 6or example! if a modem
sends ten E"bit $ords to another modem $ithout includin' the #tart! #top and ,arity bits! the
sendin' modem $ill be able to add 92 bits of its o$n information that the receivin' modem can use
to do error"correction $ithout impactin' the transmission speed of the real data.
The use of the term (aud is further confused by modems that perform compression. A sin'le F"bit
$ord passed over the telephone line mi'ht represent a do.en $ords that $ere transmitted to the
sendin' modem. The receivin' modem $ill expand the data back to its ori'inal content and pass
that data to the receivin' &T5.
<odern modems also include buffers that allo$ the rate that bits move across the phone line (&-5
to &-5) to be a different speed than the speed that the bits move bet$een the &T5 and &-5 on
both ends of the conversation. Normally the speed bet$een the &T5 and &-5 is hi'her than the
&-5 to &-5 speed because of the use of compression by the modems.
(ecause the number of bits needed to describe a byte varied durin' the trip bet$een the t$o
machines plus the differin' bits"per"seconds speeds that are used present on the &T5"&-5 and
&-5"&-5 links! the usa'e of the term (aud to describe the overall communication speed causes
problems and can misrepresent the true transmission speed. #o (its ,er #econd (bps) is the correct
term to use to describe the transmission rate seen at the &-5 to &-5 interface and (aud or (its ,er
#econd are acceptable terms to use $hen a connection is made bet$een t$o systems $ith a $ired
connection! or if a modem is in use that is not performin' error"correction or compression.
<odern hi'h speed modems (8;22! C?22! 1;!;22! and 1C!822bps) in reality still operate at or belo$
8;22 baud! or more accurately! 8;22 #ymbols per second. Bi'h speed modem are able to encode
more bits of data into each #ymbol usin' a techniue called -onstellation #tuffin'! $hich is $hy
the effective bits per second rate of the modem is hi'her! but the modem continues to operate $ithin
the limited audio band$idth that the telephone system provides. <odems operatin' at 8F!F22 and
hi'her speeds have variable #ymbol rates! but the techniue is the same.
1.4. The 1$' .ersonal "om(uter UART
#tartin' $ith the ori'inal +(< ,ersonal -omputer! +(< selected the National #emiconductor
+N#F8>2 UART for use in the +(< ,- ,arallel/#erial Adapter. #ubseuent 'enerations of
compatible computers from +(< and other vendors continued to use the +N#F8>2 or improved
versions of the National #emiconductor UART family.
1.4.1. *ational Semiconductor UART Family Tree
There have been several versions and subseuent 'enerations of the +N#F8>2 UART. 5ach ma7or
version is described belo$.
INS8250 -> INS8250B
\
\
\-> INS8250A -> INS82C50A
\
\
\-> NS16450 -> NS16C450
\
\
\-> NS16550 -> NS16550A -> PC16550D
+N#F8>2
This part $as used in the ori'inal +(< ,- and +(< ,-/GT. The ori'inal name for this part
$as the +N#F8>2 A-5 (Asynchronous -ommunications 5lement) and it is made from N<A#
technolo'y.
The F8>2 uses ei'ht +/A ports and has a one"byte send and a one"byte receive buffer. This
ori'inal UART has several race conditions and other fla$s. The ori'inal +(< (+A# includes
code to $ork around these fla$s! but this made the (+A# dependent on the fla$s bein'
present! so subseuent parts like the F8>2A! 1?;>2 or 1?>>2 could not be used in the ori'inal
+(< ,- or +(< ,-/GT.
+N#F8>2"(
This is the slo$er speed of the +N#F8>2 made from N<A# technolo'y. +t contains the same
problems as the ori'inal +N#F8>2.
+N#F8>2A
An improved version of the +N#F8>2 usin' G<A# technolo'y $ith various functional fla$s
corrected. The +N#F8>2A $as used initially in ,- clone computers by vendors $ho used
)clean* (+A# desi'ns. (ecause of the corrections in the chip! this part could not be used $ith
a (+A# compatible $ith the +N#F8>2 or +N#F8>2(.
+N#F8->2A
This is a -<A# version (lo$ po$er consumption) of the +N#F8>2A and has similar
functional characteristics.
N#1?;>2
#ame as N#F8>2A $ith improvements so it can be used $ith faster -,U bus desi'ns. +(<
used this part in the +(< AT and updated the +(< (+A# to no lon'er rely on the bu's in the
+N#F8>2.
N#1?-;>2
This is a -<A# version (lo$ po$er consumption) of the N#1?;>2.
N#1?>>2
#ame as N#1?;>2 $ith a 1?"byte send and receive buffer but the buffer desi'n $as fla$ed
and could not be reliably be used.
N#1?>>2A
#ame as N#1?>>2 $ith the buffer fla$s corrected. The 1?>>2A and its successors have
become the most popular UART desi'n in the ,- industry! mainly due to its ability to reliably
handle hi'her data rates on operatin' systems $ith slu''ish interrupt response times.
N#1?->>8
This component consists of t$o N#1?->>2A -<A# UARTs in a sin'le packa'e.
,-1?>>2&
#ame as N#1?>>2A $ith subtle fla$s corrected. This is revision & of the 1?>>2 family and is
the latest desi'n available from National #emiconductor.
1.4.2. The *S14//5AF and the ."14//5+ are the same thin%
National reor'ani.ed their part numberin' system a fe$ years a'o! and the N#1?>>2A6N no lon'er
exists by that name. (+f you have a N#1?>>2A6N! look at the date code on the part! $hich is a four
di'it number that usually starts $ith a nine. The first t$o di'its of the number are the year! and the
last t$o di'its are the $eek in that year $hen the part $as packa'ed. +f you have a N#1?>>2A6N! it
is probably a fe$ years old.)
The ne$ numbers are like ,-1?>>2&:! $ith minor differences in the suffix letters dependin' on the
packa'e material and its shape. (A description of the numberin' system can be found belo$.)
+t is important to understand that in some stores! you may pay H1>(U#) for a N#1?>>2A6N made in
1CC2 and in the next bin are the ne$ ,-1?>>2&N parts $ith minor fixes that National has made
since the A6N part $as in production! the ,-1?>>2&N $as probably made in the past six months
and it costs half (as lo$ as H>(U#) in volume) as much as the N#1?>>2A6N because they are
readily available.
As the supply of N#1?>>2A6N chips continues to shrink! the price $ill probably continue to
increase until more people discover and accept that the ,-1?>>2&N really has the same function as
the old part number.
1.4.3. *ational Semiconductor .art *um2erin% System
The older N#nnnnnrqp part numbers are no$ of the format ,-nnnnnrgp.
The r is the revision field. The current revision of the 1?>>2 from National #emiconductor is D.
The p is the packa'e"type field. The types are%
060 I6, (uad flat pack) 4 lead type
0N0 &+, (dual inline packa'e) throu'h hole strai'ht lead type
0:0 4,-- (lead plastic chip carrier) J lead type
The g is the product 'rade field. +f an I precedes the packa'e"type letter! it indicates an )industrial*
'rade part! $hich has hi'her specs than a standard part but not as hi'h as <ilitary #pecification
(<ilspec) component. This is an optional field.
#o $hat $e used to call a N#1?>>2A6N (&+, ,acka'e) is no$ called a ,-1?>>2&N or
,-1?>>2&+N.
1.6. Other #endors and Similar UARTs
Aver the years! the F8>2! F8>2A! 1?;>2 and 1?>>2 have been licensed or copied by other chip
vendors. +n the case of the F8>2! F8>2A and 1?;>2! the exact circuit (the )me'acell*) $as licensed
to many vendors! includin' /estern &i'ital and +ntel. Ather vendors reverse"en'ineered the part or
produced emulations that had similar behavior.
+n internal modems! the modem desi'ner $ill freuently emulate the F8>2A/1?;>2 $ith the modem
microprocessor! and the emulated UART $ill freuently have a hidden buffer consistin' of several
hundred bytes. (ecause of the si.e of the buffer! these emulations can be as reliable as a 1?>>2A in
their ability to handle hi'h speed data. Bo$ever! most operatin' systems $ill still report that the
UART is only a F8>2A or 1?;>2! and may not make effective use of the extra bufferin' present in
the emulated UART unless special drivers are used.
#ome modem makers are driven by market forces to abandon a desi'n that has hundreds of bytes of
buffer and instead use a 1?>>2A UART so that the product $ill compare favorably in market
comparisons even thou'h the effective performance may be lo$ered by this action.
A common misconception is that all parts $ith )1?>>2A* $ritten on them are identical in
performance. There are differences! and in some cases! outri'ht fla$s in most of these 1?>>2A
clones.
/hen the N#1?>>2 $as developed! the National #emiconductor obtained several patents on the
desi'n and they also limited licensin'! makin' it harder for other vendors to provide a chip $ith
similar features. (ecause of the patents! reverse"en'ineered desi'ns and emulations had to avoid
infrin'in' the claims covered by the patents. #ubseuently! these copies almost never perform
exactly the same as the N#1?>>2A or ,-1?>>2&! $hich are the parts most computer and modem
makers $ant to buy but are sometimes un$illin' to pay the price reuired to 'et the 'enuine part.
#ome of the differences in the clone 1?>>2A parts are unimportant! $hile others can prevent the
device from bein' used at all $ith a 'iven operatin' system or driver. These differences may sho$
up $hen usin' other drivers! or $hen particular combinations of events occur that $ere not $ell
tested or considered in the /indo$sK driver. This is because most modem vendors and 1?>>2"
clone makers use the <icrosoft drivers from /indo$sK for /ork'roups 9.11 and the <icrosoftK
<#"&A#K utility as the primary tests for compatibility $ith the N#1?>>2A. This over"simplistic
criteria means that if a different operatin' system is used! problems could appear due to subtle
differences bet$een the clones and 'enuine components.
National #emiconductor has made available a pro'ram named -A<T5#T that performs
compatibility tests independent of any A# drivers. +t should be remembered that the purpose of this
type of pro'ram is to demonstrate the fla$s in the products of the competition! so the pro'ram $ill
report ma7or as $ell as extremely subtle differences in behavior in the part bein' tested.
+n a series of tests performed by the author of this document in 1CC;! components made by National
#emiconductor! T+! #tarTech! and -<& as $ell as me'acells and emulations embedded in internal
modems $ere tested $ith -A<T5#T. A difference count for some of these components is listed
belo$. (ecause these tests $ere performed in 1CC;! they may not reflect the current performance of
the 'iven product from a vendor.
+t should be noted that -A<T5#T normally aborts $hen an excessive number or certain types of
problems have been detected. As part of this testin'! -A<T5#T $as modified so that it $ould not
abort no matter ho$ many differences $ere encountered.
#endor .art *um2er
,rrors &aka 7di88erences7
re(orted)
National (,-1?>>2&:) 2
National (N#1?>>2A6N) 2
National (N#1?->>8:) 2
T+ (T41?>>2A6N) 9
-<& (1?->>2,5) 1C
#tarTech (#T1?->>2J) 89
Rock$ell
Reference modem $ith internal 1?>>2 or an emulation
(R-1;;&,i/-9222"8>)
11E
#endor .art *um2er
,rrors &aka 7di88erences7
re(orted)
#ierra <odem $ith an internal 1?>>2 (#-11C>1/#-119>1) C1
*ote:
To date! the author of this document has not found any non"National parts that report .ero
differences usin' the -A<T5#T pro'ram. +t should also be noted that National has had five
versions of the 1?>>2 over the years and the ne$est parts behave a bit differently than the classic
N#1?>>2A6N that is considered the benchmark for functionality. -A<T5#T appears to turn a
blind eye to the differences $ithin the National product line and reports no errors on the National
parts (except for the ori'inal 1?>>2) even $hen there are official erratas that describe bu's in the A!
( and - revisions of the parts! so this bias in -A<T5#T must be taken into account.
+t is important to understand that a simple count of differences from -A<T5#T does not reveal a
lot about $hat differences are important and $hich are not. 6or example! about half of the
differences reported in the t$o modems listed above that have internal UARTs $ere caused by the
clone UARTs not supportin' five" and six"bit character modes. The real 1?>>2! 1?;>2! and F8>2
UARTs all support these modes and -A<T5#T checks the functionality of these modes so over
fifty differences are reported. Bo$ever! almost no modern modem supports five" or six"bit
characters! particularly those $ith error"correction and compression capabilities. This means that
the differences related to five" and six"bit character modes can be discounted.
<any of the differences -A<T5#T reports have to do $ith timin'. +n many of the clone desi'ns!
$hen the host reads from one port! the status bits in some other port may not update in the same
amount of time (some faster! some slo$er) as a real N#1?>>2A6N and -A<T5#T looks for these
differences. This means that the number of differences can be misleadin' in that one device may
only have one or t$o differences but they are extremely serious! and some other device that updates
the status re'isters faster or slo$er than the reference part (that $ould probably never affect the
operation of a properly $ritten driver) could have do.ens of differences reported.
-A<T5#T can be used as a screenin' tool to alert the administrator to the presence of potentially
incompatible components that mi'ht cause problems or have to be handled as a special case.
+f you run -A<T5#T on a 1?>>2 that is in a modem or a modem is attached to the serial port! you
need to first issue a AT52L/ command to the modem so that the modem $ill not echo any of the
test characters. +f you for'et to do this! -A<T5#T $ill report at least this one difference%
Error (6)...!"eo#$ !%$err#p$ &a!'e() II* + c1 ,S* + 61
1.9. 92/5:14/5:14//5 Re%isters
The F8>2/1?;>2/1?>>2 UART occupies ei'ht conti'uous +/A port addresses. +n the +(< ,-! there
are t$o defined locations for these ei'ht ports and they are kno$n collectively as C-M1 and C-M2.
The makers of ,-"clones and add"on cards have created t$o additional areas kno$n as C-M. and
C-M4! but these extra -A< ports conflict $ith other hard$are on some systems. The most common
conflict is $ith video adapters that provide +(< F>1; emulation.
C-M1 is located from 2x9fF to 2x9ff and normally uses +RI ;. C-M2 is located from 2x8fF to 2x8ff
and normally uses +RI 9. C-M. is located from 2x9eF to 2x9ef and has no standardi.ed +RI. C-M4
is located from 2x8eF to 2x8ef and has no standardi.ed +RI.
A description of the +/A ports of the F8>2/1?;>2/1?>>2 UART is provided belo$.
1:O
.ort
Access Allowed +escri(tion
=2x22 $rite (&4A(MM2)
Transmit Boldin' Re'ister
(TBR).
+nformation $ritten to this
port are treated as data $ords
and $ill be transmitted by the
UART.
=2x22 read (&4A(MM2)
Receive (uffer Re'ister
(R(R).
Any data $ords received by
the UART form the serial link
are accessed by the host by
readin' this port.
=2x22 $rite/read (&4A(MM1)
&ivisor 4atch 4#( (&44)
This value $ill be divided
from the master input clock
(in the +(< ,-! the master
clock is 1.F;98<B.) and the
resultin' clock $ill determine
the baud rate of the UART.
This re'ister holds bits 2 thru
E of the divisor.
=2x21 $rite/read (&4A(MM1)
&ivisor 4atch <#( (&4B)
This value $ill be divided
from the master input clock
(in the +(< ,-! the master
clock is 1.F;98<B.) and the
resultin' clock $ill determine
the baud rate of the UART.
This re'ister holds bits F thru
1> of the divisor.
=2x21 $rite/read (&4A(MM2)
+nterrupt 5nable Re'ister (+5R)
The F8>2/1?;>2/1?>>2 UART classifies events into one of
four cate'ories. 5ach cate'ory can be confi'ured to 'enerate
an interrupt $hen any of the events occurs. The
F8>2/1?;>2/1?>>2 UART 'enerates a sin'le external
interrupt si'nal re'ardless of ho$ many events in the
enabled cate'ories have occurred. +t is up to the host
processor to respond to the interrupt and then poll the
enabled interrupt cate'ories (usually all cate'ories have
1:O
.ort
Access Allowed +escri(tion
interrupts enabled) to determine the true cause(s) of the
interrupt.
(it
E
Reserved! al$ays 2.
(it
?
Reserved! al$ays 2.
(it
>
Reserved! al$ays 2.
(it
;
Reserved! al$ays 2.
(it
9
5nable <odem #tatus +nterrupt (5&##+). #ettin' this
bit to 010 allo$s the UART to 'enerate an interrupt
$hen a chan'e occurs on one or more of the status
lines.
(it
8
5nable Receiver 4ine #tatus +nterrupt (54#+) #ettin'
this bit to 010 causes the UART to 'enerate an interrupt
$hen the an error (or a (R5AN si'nal) has been
detected in the incomin' data.
(it
1
5nable Transmitter Boldin' Re'ister 5mpty +nterrupt
(5T(5+) #ettin' this bit to 010 causes the UART to
'enerate an interrupt $hen the UART has room for one
or more additional characters that are to be transmitted.
(it
2
5nable Received &ata Available +nterrupt (5R(6+)
#ettin' this bit to 010 causes the UART to 'enerate an
interrupt $hen the UART has received enou'h
characters to exceed the tri''er level of the 6+6A! or the
6+6A timer has expired (stale data)! or a sin'le
character has been received $hen the 6+6A is disabled.
=2x28 $rite
6+6A -ontrol Re'ister (6-R) (This port does not exist on
the F8>2 and 1?;>2 UART.)
(it E Receiver Tri''er (it O1
(it ?
Receiver Tri''er (it O2
These t$o bits control at $hat point the receiver is to
'enerate an interrupt $hen the 6+6A is active.
E ?
Bo$ many $ords are received before an interrupt
is 'enerated
2 2 1
2 1 ;
1 2 F
1 1 1;
(it > Reserved! al$ays 2.
(it ; Reserved! al$ays 2.
1:O
.ort
Access Allowed +escri(tion
(it 9
&<A <ode #elect. +f (it 2 is set to 010 (6+6As
enabled)! settin' this bit chan'es the operation of the
"RGR&P and "TGR&P si'nals from <ode 2 to <ode
1.
(it 8
Transmit 6+6A Reset. /hen a 010 is $ritten to this bit!
the contents of the 6+6A are discarded. Any $ord
currently bein' transmitted $ill be sent intact. This
function is useful in abortin' transfers.
(it 1
Receiver 6+6A Reset. /hen a 010 is $ritten to this bit!
the contents of the 6+6A are discarded. Any $ord
currently bein' assembled in the shift re'ister $ill be
received intact.
(it 2
1?>>2 6+6A 5nable. /hen set! both the transmit and
receive 6+6As are enabled. Any contents in the
holdin' re'ister! shift re'isters or 6+6As are lost $hen
6+6As are enabled or disabled.
=2x28 read
+nterrupt +dentification Re'ister
(it
E
6+6As enabled. An the F8>2/1?;>2 UART! this bit is
.ero.
(it
?
6+6As enabled. An the F8>2/1?;>2 UART! this bit is
.ero.
(it
>
Reserved! al$ays 2.
(it
;
Reserved! al$ays 2.
(it
9
+nterrupt +& (it O8. An the F8>2/1?;>2 UART! this bit
is .ero.
(it
8
+nterrupt +& (it O1
(it
1
+nterrupt +& (it O2.These three bits combine to report
the cate'ory of event that caused the interrupt that is in
pro'ress. These cate'ories have priorities! so if
multiple cate'ories of events occur at the same time!
the UART $ill report the more important events first
and the host must resolve the events in the order they
are reported. All events that caused the current
interrupt must be resolved before any ne$ interrupts
$ill be 'enerated. (This is a limitation of the ,-
architecture.)
8 1 2 ,riority &escription
2 1 1 6irst Received 5rror (A5! ,5! (+! or 65)
2 1 2 #econd Received &ata Available
1 1 2 #econd
Tri''er level identification (#tale data
in receive buffer)
2 2 1 Third Transmitter has room for more $ords
1:O
.ort
Access Allowed +escri(tion
(TBR5)
2 2 2 6ourth
<odem #tatus -han'e ("-T#! "&#R!
"R+! or "&-&)
(it
2
+nterrupt ,endin' (it. +f this bit is set to 020! then at
least one interrupt is pendin'.
=2x29
$rite/read
4ine -ontrol Re'ister (4-R)
(it E
&ivisor 4atch Access (it (&4A(). /hen set!
access to the data transmit/receive re'ister
(TBR/R(R) and the +nterrupt 5nable Re'ister
(+5R) is disabled. Any access to these ports is
no$ redirected to the &ivisor 4atch Re'isters.
#ettin' this bit! loadin' the &ivisor Re'isters!
and clearin' &4A( should be done $ith
interrupts disabled.
(it ?
#et (reak. /hen set to 010! the transmitter
be'ins to transmit continuous #pacin' until
this bit is set to 020. This overrides any bits of
characters that are bein' transmitted.
(it >
#tick ,arity. /hen parity is enabled! settin'
this bit causes parity to al$ays be 010 or 020!
based on the value of (it ;.
(it ;
5ven ,arity #elect (5,#). /hen parity is
enabled and (it > is 020! settin' this bit causes
even parity to be transmitted and expected.
Ather$ise! odd parity is used.
(it 9
,arity 5nable (,5N). /hen set to 010! a parity
bit is inserted bet$een the last bit of the data
and the #top (it. The UART $ill also expect
parity to be present in the received data.
(it 8
Number of #top (its (#T(). +f set to 010 and
usin' >"bit data $ords! 1.> #top (its are
transmitted and expected in each data $ord.
6or ?! E and F"bit data $ords! 8 #top (its are
transmitted and expected. /hen this bit is set
to 020! one #top (it is used on each data $ord.
(it 1 /ord 4en'th #elect (it O1 (/4#(1)
(it 2 /ord 4en'th #elect (it O2 (/4#(2)

To'ether these bits specify the number of bits
in each data $ord.
1 2 /ord 4en'th
2 2 > &ata (its
2 1 ? &ata (its
1 2 E &ata (its
1 1 F &ata (its
=2x2; $rite/read
1:O
.ort
Access Allowed +escri(tion
<odem -ontrol Re'ister (<-R)
(it
E
Reserved! al$ays 2.
(it
?
Reserved! al$ays 2.
(it
>
Reserved! al$ays 2.
(it
;
4oop"(ack 5nable. /hen set to 010! the UART
transmitter and receiver are internally connected
to'ether to allo$ dia'nostic operations. +n addition! the
UART modem control outputs are connected to the
UART modem control inputs. -T# is connected to
RT#! &TR is connected to &#R! AUT1 is connected to
R+! and AUT 8 is connected to &-&.
(it
9
AUT 8. An auxiliary output that the host processor may
set hi'h or lo$. +n the +(< ,- serial adapter (and most
clones)! AUT 8 is used to tri"state (disable) the interrupt
si'nal from the F8>2/1?;>2/1?>>2 UART.
(it
8
AUT 1. An auxiliary output that the host processor may
set hi'h or lo$. This output is not used on the +(< ,-
serial adapter.
(it
1
Reuest to #end (RT#). /hen set to 010! the output of
the UART "RT# line is 4o$ (Active).
(it
2
&ata Terminal Ready (&TR). /hen set to 010! the
output of the UART "&TR line is 4o$ (Active).
=2x2> $rite/read
4ine #tatus Re'ister (4#R)
(it
E
5rror in Receiver 6+6A. An the F8>2/1?;>2 UART! this
bit is .ero. This bit is set to 010 $hen any of the bytes in
the 6+6A have one or more of the follo$in' error
conditions% ,5! 65! or (+.
(it
?
Transmitter 5mpty (T5<T). /hen set to 010! there are
no $ords remainin' in the transmit 6+6A or the
transmit shift re'ister. The transmitter is completely
idle.
(it
>
Transmitter Boldin' Re'ister 5mpty (TBR5). /hen set
to 010! the 6+6A (or holdin' re'ister) no$ has room for
at least one additional $ord to transmit. The transmitter
may still be transmittin' $hen this bit is set to 010.
(it
;
(reak +nterrupt ((+). The receiver has detected a (reak
si'nal.
(it
9
6ramin' 5rror (65). A #tart (it $as detected but the
#top (it did not appear at the expected time. The
received $ord is probably 'arbled.
(it
8
,arity 5rror (,5). The parity bit $as incorrect for the
$ord received.
1:O
.ort
Access Allowed +escri(tion
(it
1
Averrun 5rror (A5). A ne$ $ord $as received and
there $as no room in the receive buffer. The ne$ly"
arrived $ord in the shift re'ister is discarded. An
F8>2/1?;>2 UARTs! the $ord in the holdin' re'ister is
discarded and the ne$ly" arrived $ord is put in the
holdin' re'ister.
(it
2
&ata Ready (&R) Ane or more $ords are in the receive
6+6A that the host may read. A $ord must be
completely received and moved from the shift re'ister
into the 6+6A (or holdin' re'ister for F8>2/1?;>2
desi'ns) before this bit is set.
=2x2?
$rite/read
<odem #tatus Re'ister (<#R)
(it
E
&ata -arrier &etect (&-&). Reflects the state of the
&-& line on the UART.
(it
?
Rin' +ndicator (R+). Reflects the state of the R+ line on
the UART.
(it
>
&ata #et Ready (&#R). Reflects the state of the &#R
line on the UART.
(it
;
-lear To #end (-T#). Reflects the state of the -T# line
on the UART.
(it
9
&elta &ata -arrier &etect (&&-&). #et to 010 if the
"&-& line has chan'ed state one more time since the
last time the <#R $as read by the host.
(it
8
Trailin' 5d'e Rin' +ndicator (T5R+). #et to 010 if the
"R+ line has had a lo$ to hi'h transition since the last
time the <#R $as read by the host.
(it
1
&elta &ata #et Ready (&&#R). #et to 010 if the "&#R
line has chan'ed state one more time since the last time
the <#R $as read by the host.
(it
2
&elta -lear To #end (&-T#). #et to 010 if the "-T#
line has chan'ed state one more time since the last time
the <#R $as read by the host.
=2x2E $rite/read
#cratch Re'ister (#-R). This
re'ister performs no function
in the UART. Any value can
be $ritten by the host to this
location and read by the host
later on.
1.0. $eyond the 14//5A UART
Althou'h National #emiconductor has not offered any components compatible $ith the 1?>>2 that
provide additional features! various other vendors have. #ome of these components are described
belo$. +t should be understood that to effectively utili.e these improvements! drivers may have to
be provided by the chip vendor since most of the popular operatin' systems do not support features
beyond those provided by the 1?>>2.
#T1??>2
(y default this part is similar to the N#1?>>2A! but an extended 98"byte send and receive
buffer can be optionally enabled. <ade by #tarTech.
T+41???2
(y default this part behaves similar to the N#1?>>2A! but an extended ?;"byte send and
receive buffer can be optionally enabled. <ade by Texas +nstruments.
Bayes 5#,
This proprietary plu'"in card contains a 82;F"byte send and receive buffer! and supports data
rates to 892.;Nbit/sec. <ade by Bayes.
+n addition to these )dumb* UARTs! many vendors produce intelli'ent serial communication
boards. This type of desi'n usually provides a microprocessor that interfaces $ith several UARTs!
processes and buffers the data! and then alerts the main ,- processor $hen necessary. (ecause the
UARTs are not directly accessed by the ,- processor in this type of communication system! it is not
necessary for the vendor to use UARTs that are compatible $ith the F8>2! 1?;>2! or the 1?>>2
UART. This leaves the desi'ner free to components that may have better performance
characteristics.
Next
8. -onfi'urin' the /!o driver
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