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  • Digital System Design Using Verilog December 2011

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    Vinayaka Hm
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    1. The document appears to be exam questions for a Digital System Design using Verilog course. It covers topics such as Verilog modules, design methodology, Boolean logic implementation, parity trees, comparators, memory design, programmable logic devices, and serial interface standards. 2. The questions test knowledge of Verilog modeling, circuit design and implementation, sequential and combinational logic, memory architectures, and field programmable gate array applications and design. 3. Answers would require explaining concepts, providing examples, drawing diagrams, and developing Verilog models to demonstrate understanding of digital system design and Verilog.

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    Digital System Design Using Verilog December 2011

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    1. The document appears to be exam questions for a Digital System Design using Verilog course. It covers topics such as Verilog modules, design methodology, Boolean logic implementation, parity trees, comparators, memory design, programmable logic devices, and serial interface standards. 2. The questions test knowledge of Verilog modeling, circuit design and implementation, sequential and combinational logic, memory architectures, and field programmable gate array applications and design. 3. Answers would require explaining concepts, providing examples, drawing diagrams, and developing Verilog models to demonstrate understanding of digital system design and Verilog.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    1K views1 page

    Digital System Design Using Verilog December 2011

    Uploaded by

    Vinayaka Hm
    1. The document appears to be exam questions for a Digital System Design using Verilog course. It covers topics such as Verilog modules, design methodology, Boolean logic implementation, parity trees, comparators, memory design, programmable logic devices, and serial interface standards. 2. The questions test knowledge of Verilog modeling, circuit design and implementation, sequential and combinational logic, memory architectures, and field programmable gate array applications and design. 3. Answers would require explaining concepts, providing examples, drawing diagrams, and developing Verilog models to demonstrate understanding of digital system design and Verilog.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
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    USN
    10EC121
    M.Tech. DegreeExamination, December 2011
    Digital System Design using Verilog
    Time: 3 hrs. Max. Marks:l00
    Note: Answer any FIVE full questions.
    1 a. What does a verilog module define. Explain in brief the three principal design tasks that
    benefit theuseof verilog. (08 Marks)
    b. What is meant by design methodology? Explain the basic steps of design methodology, in
    brief. (12 Marks)
    '2 a. Using AND-OR-INVERTER (AOI) logic implement the given Boolean function
    F =(x+y.z).(y.z). Show how the Boolean equation for F can be transformed into SOP
    form. Usethelaws of Boolean algebra for reduction and implement theSOP formtheresult.
    (08 Marks)
    b. Write averilog model to devise aone-hot code to represent the days of the week (Monday
    through Sunday). (06 Marks)
    c. Draw thecircuit diagrams of parity trees for generating and checking odd parity for an8-bit
    code. (06 Marks)
    3 a. With aneat figure, explain theequality comparator and inequality comparator. (08 Marks)
    b. Develop averilog model of aconverter that converts a4-bit binary codeinput to a4-bit gray
    coded output. (08 Marks)
    c. What number is represented by the signal fixed-point binary number 111101, assuming the
    binary point is four places fromtheright? (04 Marks)
    4 a. Design acontrol sequence for thecontrol signals ofthe sequential complex multiplier.
    (10 Marks)
    b. What is the main difference between atestbench for acombinational circuit and atestbench
    for asequential circuit? Explain with anexample. (06 Marks)
    c. What is GALS? Explain. (04 Marks)
    5 a. Design aI Gx8-bit memory using four 256Mx4-bit memory components. (08 Marks)
    b. Develop averilog model of adual-port 4k x 16-bit flow through SSRAM. Oneport allows
    datatobewritten and read, whiletheother port only allows datatoberead. (08 Marks)
    c. Determine whether there is anerror inthe ECC word 000111000100 and if socorrect it.
    (04 Marks)
    6 a. What is thebenefit of allowing PLD inasystemtobereprogrammed? Explain.
    b. What distinguishes aplatform FPGA fromasimple FPGA? Explain inbrief.
    c. Write aGurnnut assembly language program tofind thegreater of two values.
    (06 Marks)
    (04 Marks)
    (10 Marks)
    7 a. Briefly explain the serial interface standards for I/O devices.
    b. With aneat diagram, explain thearchitecture for Sobel accelerator datapath.
    (10 Marks)
    (10 Marks)
    8 a. Briefly describe thepurpose of floor planning placement and routing. (10 Marks)
    b. With aneat circuit diagram, explain 4-bit LFSRs and 4-bit GFSR and their purposes.
    (10 Marks)
    * * * * *

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