MIMO Signal Processing Considerations

David Hawke, Director Wireless Product Marketing, Xilinx looks at the

signal processing requirements and considerations behind MIMO and how
they can be optimised.
In a bid to meet demand for greater bandwidth, operators are tackling network expansion through
the use of Multiple-In-Multiple-Out, MIMO antennas, an increasing number of mobile stations and
wider range of frequencies.
But this demand cannot be met without adhering to commercial pressures; in the face of
mounting operating costs, operators are also desperate for equipment that offers greater
efficiency and higher integration.
This burden falls to the equipment manufacturers, who must now deliver these gains within
smaller budgets and market windows. These design considerations for MIMO signal processing
are of great importance in the design of any system and should be determined at the earliest
stages oft he design process.
Cellular applications
The LTE rollout (both TDD and FDD) across the globe has come with its own unique
requirements in terms of equipment features and performance, particularly when compared to
previous air-interface roll-outs.
The most common configuration used for the CDMA2000 and WCDMA 3G rollout was a 20MHz
2x2 radio, a configuration that has now evolved to deliver wider bandwidth and support more
frequency bands. Manufacturers are now commonly developing MIMO radios capable of
delivering as much as 100MHz of usable bandwidth. These new configurations typically employ
4x4 and 8x8 MIMO antenna arrays.
Development of these ultra-wide-band radios will allow network operators to deploy a single radio
that supports multiple frequency bands of interest - for example 1800MHz, 1900MHz, and even
2100MHz in the futureresulting in fewer remote radios mounted on the tower top, which in turn
reduces costs. This evolution not only saves significant capital equipment costs through the use
of fewer radios, but also significantly reduces operating costs and site-rental costs through wind-
loading reduction and reduced total weight loading on the tower.
MIMO processing requirements
A 100MHz 8x8 radio requires 20x more signal processing than a 20MHz 2x2 radio. When
considering the digital and analogue processing requirements for such radio equipment, it is hard
to see how the products could ever be realised while meeting mechanical, thermal, and cost
constraints imposed by passively cooled remote radios. Clearly, continued evolution of new
generations of digital and analogue ICs is required.
Consider the system-level requirements for implementing a 100MHz 8x8 radio as an example.
In an 8x8 mobile radio, the dimensions that define the required FPGA devices needed include
the number of antennas, the air interface, the number of carriers, and the instantaneous
bandwidth. The number of antennas defines the required number of DAC and ADC connections.
The radios instantaneous bandwidth defines the sample rate and therefore defines the speed
and number of SerDes ports required to connect the digital signal processing in the FPGA with
the DACs and ADCs.
Data converters have advanced significantly over the last few years with many manufacturers
now offering multiple DACs and ADCs within a single package, connected to the digital radio
processing circuitry via JESD204B. The JESD204B interface standard replaces the older,
previously used LVDS parallel interfaces with high speed SerDes ports capable of running at
12.5Gbps. JESD204B interfaces significantly reduce the number of required connections
between the DACs and ADCs and the digital front end processing circuitry. The result is fewer
PCB layers and reduced interface power. Furthermore, these JESD204B converters are now
becoming even more integrated; they are absorbing entire uplink and downlink RF-processing
subsystems, resulting in high-performance RF ICs that include the DACs, ADCs, filtering, and
modulators needed to create highly integrated and high-performance analogue front ends, AFEs.
More variables
In addition to determining the number of required SerDes transceivers, a mobile radios
bandwidth and antenna count also dictate the amount of logic and DSP required for processing
algorithms, including Digital Up Conversion, DUC and Digital Down Conversion, DDC. DUC and
DDC algorithms are very well suited to FPGA implementations because they allow network
customers to tweak the algorithms as needed without hardware changes. Two additional and
commonly used algorithms are Crest Factor Reduction, CFR, and Digital Pre-Distortion, DPD,
which improve a radio output power amplifiers efficiency.
Based on the DSP resources required for implementing wideband radios and the number of
SERDES required to communicate with eight antennas, a cost-effective method of implementing
a mobile radio using current-generation Xilinx FPGAs would be to split the algorithmic processing
between two devices, as shown in Figure 1. This system partitioning effectively creates two 4x4
100MHz radios. A by-product of this partitioning is that it spreads the operating power evenly
across two digital devices, easing the thermal constraints and simplifying the designs
mechanics.

Figure 1: 100MHz 8x8 Radio implementation example using two Kintex-7 FPGAs
However, this system-level partition is no longer needed using Xilinx Kintex UltraScale devices,
which have significantly more DSP capability, a larger number of SERDES ports, and consume
significantly less power.
UltraScale architecture for MIMO
In fact, the UltraScale architecture has been highly tuned to the needs of this type of radio
design. The UltraScale architectures highly efficient block RAM and LUT (Look Up Table) RAM
and its optimised DSP48E2 DSP blocks efficiently combine to create the many types of filters
needed for DUC, DDC, CFR, and DPD signal processing. The UltraScale architectures
programmable-logic fabric and on-chip memory can implement high-performance, soft
microprocessors, which can be used with hardware acceleration to implement highly scalable,
low-footprint coefficient engines for DPD processing.
UltraScale FPGAs can achieve clock rates in excess of 491MHz, which permits the exploitation
of time-division multiplexing to further reduce the amount of on-chip area devoted to signal
processing while retaining the low power consumption of an FPGA-based radio design.
Consequently, a 100MHz 8x8 radio can be implemented with just one Kintex UltraScale FPGA,
as shown in Figure 2.

Figure 2: Comparable 100MHz 8x8 Radio implemented with one Kintex UltraScale FPGA
To implement such a complex radio in a single device, the overall operating power must drop
considerably to reduce the generated heat. FPGAs based on the Xilinx UltraScale architecture
have been tailored for low-power operation in several ways. First, the static power of two 28nm
FPGAs is replaced by just one 20nm FPGA. The one FPGA device shown in Figure 2 consumes
less power than the two FPGAs shown in Figure 1 while implementing the same number of
channels.
Design considerations for low power
Furthermore, careful design has significantly reduced the dynamic power of the devices
programmable-logic fabric and SERDES transceivers. Fewer of DSP blocks are needed for
digital filter implementations based on complex MAC (multiply/accumulate) operations. Reducing
the required number of DSP blocks reduces the dynamic power and area needed to implement
DUC, DDC, CFR, and DPD algorithms.
The system-level result is an 8% reduction in cost per transmit/receive pair and a power
reduction of more than 31% relative to an implementation based on a previous-generation
device. Additional system-level cost savings can be realised through the reduced number of
required PCB layers and reduced power supply complexity. A smaller power supply and smaller,
less complex cooling hardware further reduce the remote radio systems weight and the required
enclosure size, which further reduces BOM and operating costs.
The demand for radio infrastructure equipment that matches lower purchase and operating costs
with higher reliability is rising; the key to meeting that demand is integration. As shown here,
ultra-wideband MIMO radios offer the solution but, until recently, could only be implemented
using multiple discrete components which threatened to add cost and power. Through the higher
integration offered in modern FPGAs, the MIMO landscape is changing.
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