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D, JG, OR P PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
D
VDD
2OUT
2IN
2IN +
FK PACKAGE
(TOP VIEW)
NC
1IN
NC
1IN +
NC
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
NC
2OUT
NC
2IN
NC
NC No internal connection
DISTRIBUTION OF TLC27L7
INPUT OFFSET VOLTAGE
description
30
PACKAGE
VIOmax
AT 25C
SMALL
OUTLINE
(D)
0C
to
70C
500 V
2 mV
5 mV
10 mV
TLC27L7CD
TLC27L2BCD
TLC27L2ACD
TLC27L2CD
40C
to
85C
500 V
2 mV
5 mV
10 mV
TLC27L7ID
TLC27L2BID
TLC27L2AID
TLC27L2ID
55C
to
125C
500 V
10 mV
TLC27L7MD
TLC27L2MD
TLC27L2MDRG4
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
TLC27L7CP
TLC27L2BCP
TLC27L2ACP
TLC27L2CP
TLC27L7IP
TLC27L2BIP
TLC27L2AIP
TLC27L2IP
TLC27L7MFK
TLC27L2MFK
TLC27L7MJG
TLC27L2MJG
TLC27L7MP
TLC27L2MP
Percentage of Units %
25
AVAILABLE OPTIONS
TA
NC
1OUT
NC
VDD
NC
1OUT
1IN
1IN +
GND
NC
GND
NC
2IN +
NC
20
15
10
5
0
800
400
0
400
800
VIO Input Offset Voltage V
The D package is available taped and reeled. Add R suffix to the device type
(e.g., TLC27L7CDR).
description (continued)
These devices use Texas Instruments silicon-gate LinCMOS technology, which provides offset voltage
stability far exceeding the stability available with conventional metal-gate processes.
The extremely high input impedance, low bias currents, and low power consumption make these cost-effective
devices ideal for high gain, low frequency, low power applications. Four offset voltage grades are available
(C-suffix and I-suffix types), ranging from the low-cost TLC27L2 (10 mV) to the high-precision TLC27L7
(500 V). These advantages, in combination with good common-mode rejection and supply voltage rejection,
make these devices a good choice for new state-of-the-art designs as well as for upgrading existing designs.
In general, many features associated with bipolar technology are available in LinCMOS operational amplifiers,
without the power penalties of bipolar technology. General applications such as transducer interfacing, analog
calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC27L2 and
TLC27L7. The devices also exhibit low voltage single-supply operation and ultra-low power consumption,
making them ideally suited for remote and inaccessible battery-powered applications. The common-mode input
voltage range includes the negative rail.
A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density
system applications.
The device inputs and outputs are designed to withstand 100-mA surge currents without sustaining latch-up.
The TLC27L2 and TLC27L7 incorporate internal ESD-protection circuits that prevent functional failures at
voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in
handling these devices as exposure to ESD may result in the degradation of the device parametric performance.
The C-Suffix devices are characterized for operation from 0C to 70C. The I-suffix devices are characterized
for operation from 40C to 85C. The M-suffix devices are characterized for operation over the full military
temperature range of 55C to 125C.
P4
R6
R1
N5
R2
IN
P5
P1
P6
P2
IN +
R5
C1
OUT
N3
N1
R3
N2
D1
N4
R4
D2
GND
N6
R7
N7
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Differential input voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VDD
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Total current into VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Duration of short-circuit current at (or below) 25C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C to 85C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 125C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN .
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
DISSIPATION RATING TABLE
PACKAGE
TA 25C
25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25C
TA = 70
70C
C
POWER RATING
TA = 85
85C
C
POWER RATING
TA = 125
125C
C
POWER RATING
5.8 mW/C
464 mW
377 mW
725 mW
FK
1375 mW
11 mW/C
880 mW
715 mW
275 mW
JG
1050 mW
8.4 mW/C
672 mW
546 mW
210 mW
1000 mW
8 mW/C
640 mW
520 mW
VDD = 5 V
VDD = 10 V
C SUFFIX
I SUFFIX
M SUFFIX
MIN
MAX
MIN
MAX
MIN
MAX
16
16
16
0.2
3.5
0.2
3.5
3.5
0.2
8.5
0.2
8.5
8.5
70
40
85
55
125
UNIT
V
V
C
PARAMETER
TEST CONDITIONS
TA
TLC27L2C
TLC27L2AC
TLC27L2BC
TLC27L7C
MIN
TLC27L2C
VIO
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 1 M
VIC = 0,
RL = 1 M
Full range
TLC27L2BC
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 1 M
Full range
TLC27L7C
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 1 M
VIO
IIO
VO = 2.5 V,
VIC = 2.5 V
IIB
VO = 2.5 V,
VIC = 2.5 V
VOH
VOL
AVD
CMRR
kSVR
IDD
RL = 1 M
VO = 0.25 V to 2 V,
IOL = 0
RL = 1 M
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 2.5 V,
No load
VO = 1.4 V
VIC = 2.5 V,
10
0.9
204
mV
2000
3000
25C
170
Full range
500
V
V
1500
25 C to
25C
70C
1.1
25C
0.1
60
70C
300
25C
0.6
60
70C
50
600
25C
25
C
0.2
to
4
Full range
0.2
to
3.5
25C
3.2
4.1
0C
4.1
70C
4.2
V/C
V/C
0.3
to
4.2
pA
pA
25C
50
0C
50
70C
50
25C
50
700
0C
50
700
70C
50
380
25C
65
94
0C
60
95
70C
60
95
25C
70
97
0C
60
97
70C
60
98
mV
V/mV
dB
dB
25C
20
34
0C
24
42
70C
16
28
5
6.5
25C
MAX
1.1
12
25C
VO = 1.4 V,
RS = 50 ,
TYP
Full range
TLC27L2AC
VICR
25C
UNIT
PARAMETER
TEST CONDITIONS
TA
TLC27L2C
TLC27L2AC
TLC27L2BC
TLC27L7C
MIN
VO = 1.4 V,
RS = 50 ,
TLC27L2C
VIO
VIC = 0,
RL = 1 M
25C
MAX
1.1
10
12
25C
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 1 M
Full range
TLC27L2BC
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 1 M
Full range
TLC27L7C
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 1 M
Full range
TYP
Full range
TLC27L2AC
UNIT
0.9
5
6.5
25C
235
2000
3000
25C
190
800
25C
0.1
60
IIO
VO = 5 V,
VIC = 5 V
70C
300
25C
0.7
60
IIB
VO = 5 V,
VIC = 5 V
70C
50
600
VICR
VOH
VOL
AVD
CMRR
kSVR
IDD
25C to
70C
RL = 1 M
IOL = 0
VO = 1 V to 6 V,
RL = 1 M
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 5 V,
No load
VO = 1.4 V
VIC = 5 V,
1900
VIO
V/C
25C
25
C
0.2
to
9
Full range
0.2
to
8.5
mV
0.3
to
9.2
pA
pA
25C
8.9
0C
7.8
8.9
70C
7.8
8.9
25C
50
0C
50
70C
50
25C
50
860
0C
50
1025
70C
50
660
25C
65
97
0C
60
97
70C
60
97
25C
70
97
0C
60
97
70C
60
98
mV
V/mV
dB
dB
25C
29
46
0C
36
66
70C
22
40
PARAMETER
TEST CONDITIONS
TA
TLC27L2I
TLC27L2AI
TLC27L2BI
TLC27L7I
MIN
VO = 1.4 V,
RS = 50 ,
TLC27L2I
VIO
VIC = 0,
RL = 1 M
VIC = 0,
RL = 1 M
Full range
TLC27L2BI
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 1 M
Full range
TLC27L7I
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 1 M
VIO
IIO
VO = 2.5 V,
VIC = 2.5 V
IIB
VO = 2.5 V,
VIC = 2.5 V
VOH
VOL
AVD
CMRR
kSVR
IDD
Large-signal differential
voltage amplification
RL = 1 M
IOL = 0
VO = 0.25 V to 2 V,
RL = 1 M
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 2.5 V,
No load
VO = 1.4 V
VIC = 2.5 V,
10
0.9
240
mV
2000
3500
25C
170
Full range
500
V
V
2000
25 C to
25C
85C
1.1
25C
0.1
60
85C
24
1000
25C
0.6
60
85C
200
2000
25C
25
C
0.2
to
4
Full range
0.2
to
3.5
25C
3.2
4.1
40C
4.1
85C
4.2
V/C
V/C
0.3
to
4.2
pA
pA
25C
50
40C
50
85C
50
25C
50
480
40C
50
900
85C
50
330
25C
65
94
40C
60
95
85C
60
95
25C
70
97
40C
60
97
85C
60
98
mV
V/mV
dB
dB
25C
20
34
40C
31
54
85C
15
26
5
7
25C
MAX
1.1
13
25C
VO = 1.4 V,
RS = 50 ,
TYP
Full range
TLC27L2AI
VICR
25C
UNIT
PARAMETER
TEST CONDITIONS
TA
TLC27L2I
TLC27L2AI
TLC27L2BI
TLC27L7I
MIN
TLC27L2I
VIO
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 1 M
VIC = 0,
RL = 1 M
Full range
TLC27L2BI
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 1 M
Full range
TLC27L7I
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 1 M
VIO
IIO
VO = 5 V,
VIC = 5 V
IIB
VO = 5 V,
VIC = 5 V
VOH
VOL
AVD
CMRR
kSVR
IDD
RL = 1 M
VO = 1 V to 6 V,
IOL = 0
RL = 1 M
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 5 V,
No load
VO = 1.4 V
VIC = 5 V,
mV
7
235
2000
3500
25C
190
Full range
800
V
V
2900
25 C to
25C
85C
10
0.9
25C
V/C
V/C
25C
0.1
60
85C
26
1000
25C
0.7
60
85C
220
2000
25C
25
C
0.2
to
9
Full range
0.2
to
8.5
MAX
1.1
13
25C
VO = 1.4 V,
RS = 50 ,
TYP
Full range
TLC27L2AI
VICR
25C
UNIT
0.3
to
9.2
pA
pA
25C
8.9
40C
7.8
8.9
85C
7.8
8.9
25C
50
40C
50
85C
50
25C
50
860
40C
50
1550
85C
50
585
25C
65
97
40C
60
97
85C
60
98
25C
70
97
40C
60
97
85C
60
98
mV
V/mV
dB
dB
25C
29
46
40C
49
86
85C
20
36
TEST CONDITIONS
TA
TLC27L2M
TLC27L7M
MIN
VIO
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 1 M
Full range
TLC27L7M
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 1 M
Full range
VIO
IIO
IIB
25C
TLC27L2M
VO = 2.5 V,
VO = 2.5 V,
VIC = 2.5 V
VIC = 2.5 V
VOL
AVD
CMRR
kSVR
IDD
VO = 0.25 V to 2 V,
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 2.5 V,
No load
RL = 1 M
IOL = 0
RL = 1 M
VO = 1.4 V
VIC = 2.5 V,
10
170
mV
V
V/C
25C
0.1
60
pA
125C
1.4
15
nA
25C
0.6
60
pA
125C
35
nA
0.3
to
4.2
25C
0
to
4
0
to
3.5
3.2
55C
4.1
125C
4.2
V
4.1
V
25C
50
55C
50
125C
50
25C
50
500
55C
25
1000
125C
25
200
25C
65
94
55C
60
95
125C
60
85
25C
70
97
55C
60
97
125C
60
98
mV
V/mV
dB
dB
25C
20
34
55C
35
60
125C
14
24
500
3750
1.4
1.1
25 C to
25C
125C
Full range
VOH
MAX
12
25C
25C
25
C
VICR
UNIT
TYP
TEST CONDITIONS
TA
TLC27L2M
TLC27L7M
MIN
VIO
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 1 M
Full range
TLC27L7M
VO = 1.4 V,
RS = 50 ,
VIC = 0,
RL = 1 M
Full range
VIO
IIO
IIB
VICR
25C
TLC27L2M
VO = 5 V,
VIC = 5 V
VO = 5 V,
VIC = 5 V
VOL
AVD
CMRR
kSVR
IDD
RL = 1 M
IOL = 0
VO = 1 V to 6 V,
RL = 1 M
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 5 V,
No load
VO = 1.4 V
VIC = 5 V,
1.1
10
190
800
4300
25 C to
25C
125C
25C
mV
V
V/C
1.4
0.1
60
pA
125C
1.8
15
nA
25C
0.7
60
pA
125C
10
35
nA
25C
25
C
0
to
9
Full range
0
to
8.5
MAX
12
25C
25C
VOH
UNIT
TYP
0.3
to
9.2
8.9
55C
7.8
8.8
125C
7.8
25C
50
55C
50
125C
50
25C
50
860
55C
25
1750
125C
25
380
25C
65
97
55C
60
97
125C
60
91
25C
70
97
55C
60
97
125C
60
98
mV
V/mV
dB
dB
25C
29
46
55C
56
96
125C
18
30
PARAMETER
TEST CONDITIONS
TA
TLC27L2C
TLC27L2AC
TLC27L2BC
TLC27L7C
MIN
VI(PP) = 1 V
SR
RL = 1 M,
M ,
CL = 20 pF,
See Figure 1
VI(PP) = 2.5 V
Vn
f = 1 kHz,
See Figure 2
RS = 20 ,
BOM
VO = VOH,
RL = 1 M,
CL = 20 pF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 pF,
B1
Unity-gain bandwidth
VI = 10 mV,
CL = 20 pF,
Phase margin
f = B1,
See Figure 3
TYP
25C
0.03
0C
0.04
70C
0.03
25C
0.03
0C
0.03
70C
0.02
25C
68
25C
0C
70C
4.5
25C
85
0C
100
70C
65
25C
34
0C
36
70C
30
UNIT
MAX
V/ s
V/s
nV/Hz
kHz
kHz
PARAMETER
TEST CONDITIONS
TA
TLC27L2C
TLC27L2AC
TLC27L2BC
TLC27L7C
MIN
VI(PP) = 1 V
SR
RL = 1 M,
M ,
CL = 20 pF,
See Figure 1
VI(PP) = 5.5 V
Vn
BOM
B1
10
f = 1 kHz,
See Figure 2
RS = 20 ,
VO = VOH,
RL = 1 M,
CL = 20 pF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 pF,
Unity-gain bandwidth
Phase margin
VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 3
TYP
25C
0.05
0C
0.05
70C
0.04
25C
0.04
0C
0.05
70C
0.04
25C
68
25C
0C
1.3
70C
0.9
25C
110
0C
125
70C
90
25C
38
0C
40
70C
34
UNIT
MAX
V/
V/ss
nV/Hz
kHz
kHz
PARAMETER
TEST CONDITIONS
TA
TLC27L2I
TLC27L2AI
TLC27L2BI
TLC27L7I
MIN
VI(PP) = 1 V
SR
RL = 1 M,
M ,
CL = 20 pF,
See Figure 1
VI(PP) = 2.5 V
Vn
f = 1 kHz,
See Figure 2
RS = 20 ,
BOM
VO = VOH,
RL = 1 M,
CL = 20 pF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 pF,
B1
Unity-gain bandwidth
VI = 10 mV,
CL = 20 pF,
Phase margin
f = B1,
See Figure 3
TYP
25C
0.03
40C
0.04
85C
0.03
25C
0.03
40C
0.04
85C
0.02
25C
68
25C
40C
85C
25C
85
40C
130
85C
55
25C
34
40C
38
85C
29
UNIT
MAX
V/ s
V/s
nV/Hz
kHz
kHz
PARAMETER
TEST CONDITIONS
TA
TLC27L2I
TLC27L2AI
TLC27L2BI
TLC27L7I
MIN
VI(PP) = 1 V
SR
RL = 1 M,
M ,
CL = 20 pF,
See Figure 1
VI(PP) = 5.5 V
Vn
BOM
B1
f = 1 kHz,
See Figure 2
RS = 20 ,
VO = VOH,
RL = 1 M,
CL = 20 pF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 pF,
Unity-gain bandwidth
Phase margin
VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 3
TYP
25C
0.05
40C
0.06
85C
0.03
25C
0.04
40C
0.05
85C
0.03
25C
68
25C
40C
1.4
85C
0.8
25C
110
40C
155
85C
80
25C
38
40C
42
85C
32
UNIT
MAX
V/
V/ss
nV/Hz
kHz
kHz
11
TEST CONDITIONS
TA
TLC27L2M
TLC27L7M
MIN
VI(PP) = 1 V
SR
RL = 1 M,
M ,
CL = 20 pF,
See Figure 1
VI(PP) = 2.5 V
Vn
BOM
B1
f = 1 kHz,
See Figure 2
RS = 20 ,
VO = VOH,
RL = 1 M,
CL = 20 pF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 pF,
Unity-gain bandwidth
VI = 10 mV,
CL = 20 pF,
Phase margin
f = B1,
See Figure 3
TYP
25C
0.03
55C
0.04
125C
0.02
25C
0.03
55C
0.04
125C
0.02
25C
68
25C
55C
125C
25C
85
55C
140
125C
45
25C
34
55C
39
125C
25
UNIT
MAX
V/ s
V/s
nV/Hz
kHz
kHz
TEST CONDITIONS
TA
TLC27L2M
TLC27L7M
MIN
VI(PP) = 1 V
SR
M ,
RL = 1 M,
CL = 20 pF,
See Figure 1
VI(PP) = 5.5 V
Vn
f = 1 kHz,
See Figure 2
RS = 20 ,
BOM
VO = VOH,
RL = 1 M,
CL = 20 pF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 pF,
B1
12
Unity-gain bandwidth
Phase margin
VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 3
TYP
25C
0.05
55C
0.06
125C
0.03
25C
0.04
55C
0.06
125C
0.03
25C
68
25C
55C
1.5
125C
0.7
25C
110
55C
165
125C
70
25C
38
55C
43
125C
29
UNIT
MAX
V/ s
V/s
nV/Hz
kHz
kHz
VDD
VO
VO
VI
+
CL
RL
VI
CL
RL
VDD
(a) SINGLE SUPPLY
2 k
VDD +
VDD
20
VO
VO
1/2 VDD
+
20
20
20
VDD
VDD +
100
100
VI
VI
10 k
VO
VO
1/2 VDD
CL
CL
VDD
(a) SINGLE SUPPLY
13
Isolate the device from other potential leakage sources.Use a grounded shield around and between the
device inputs (see Figure 4). Leakages that would otherwise flow to the inputs are shunted away.
2. Compensate for the leakage of the test socket by actually performing an input bias current test (using
a picoammeter) with no device in the test socket. The actual input bias current can then be calculated
by subtracting the open-socket leakage readings from the readings obtained with a device in the test
socket.
One word of caution: many automatic testers as well as some bench-top operational amplifier testers use the
servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage
drop across the series resistor is measured and the bias current is calculated). This method requires that a
device be inserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not
feasible using this method.
8
V = VIC
14
(c) f = BOM
test time
Inadequate test time is a frequent problem, especially when testing CMOS high-volume, short-test-time
environment. Internal capacitances are inherently higher in CMOS devices and require longer test times than
their bipolar and BiFET counterparts. The problem becomes more pronounced with reduced supply levels and
lower temperatures.
15
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
16
VIO
VIO
Distribution
6, 7
Distribution
8, 9
VOH
10, 11
12
13
VOL
14,16
15,17
18, 19
AVD
vs Supply voltage
vs Free-air temperature
vs Frequency
20
21
32, 33
IIB
IIO
vs Free-air temperature
22
vs Free-air temperature
22
VIC
vs Supply voltage
23
IDD
Supply current
vs Supply voltage
vs Free-air temperature
24
25
SR
Slew rate
vs Supply voltage
vs Free-air temperature
26
27
vs Free-air temperature
28
VO(PP)
vs Frequency
29
B1
Unity-gain bandwidth
vs Free-air temperature
vs Supply voltage
30
31
Phase margin
vs Supply voltage
vs Free-air temperature
vs Capacitive Load
34
35
36
Vn
vs Frequency
37
Phase shift
vs Frequency
32, 33
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLC27L2
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC27L2
INPUT OFFSET VOLTAGE
70
70
905 Amplifiers Tested From 6 Wafer Lots
VDD = 5 V
TA = 25C
P Package
60
Percentage of Units %
Percentage of Units %
60
50
40
30
20
50
40
30
20
10
10
0
5
3 2 1 0
1
2
3
VIO Input Offset Voltage mV
Figure 6
70
356 Amplifiers Tested From 8 Wafer Lots
VDD = 5 V
TA = 25C to 125C
P Package
Outliers:
(1) 19.2 V/C
(1) 12.1 V/C
60
Percentage of Units %
Percentage of Units %
70
50
Figure 7
60
3 2 1 0
1
2
3
VIO Input Offset Voltage mV
40
30
20
50
40
30
20
10
10
0
2
4
6
8
10 8 6 4 2 0
VIO Temperature Coefficient V/C
10
0
10 8 6 4 2 0
2
4
6
8
VIO Temperature Coefficient V/C
10
Figure 9
Figure 8
17
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
16
VOH
VOH High-Level Output Voltage V
VOH
VOH High-Level Output Voltage V
VID = 100 mV
TA = 25C
4
VDD = 5 V
3
VDD = 4 V
VDD = 3 V
0
0
VDD = 16 V
12
2
4
6
8
IOH High-Level Output Current mA
8
VDD = 10 V
6
4
2
0
10
5 10 15 20 25 30 35 40
IOH High-Level Output Current mA
Figure 11
Figure 10
VID = 100 mV
RL = 10 k
TA = 25C
14
12
10
6
4
2
0
0
VDD 1.6
VOH
VOH High-Level Output Voltage V
VOH
VOH High-Level Output Voltage V
16
VID = 100 mV
TA = 25C
10
14
4
6
8
10
12
VDD Supply Voltage V
14
16
1.7
VDD = 5 V
1.8
IOH = 5 mA
VID = 100 mA
1.9
2
VDD = 10 V
2.1
2.2
2.3
2.4
75
50
25
0
20
50
75
100
TA Free-Air Temperature C
Figure 13
Figure 12
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
18
125
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
700
500
VOL
VOL Low-Level Output Voltage mV
VOL
VOL Low-Level Output Voltage mV
VDD = 5 V
IOL = 5 mA
TA = 25C
600
VID = 100 mV
500
400
VID = 1 V
300
0
0.5
1
1.5
2
2.5
3
3.3
VIC Common-Mode Input Voltage V
VDD = 10 V
IOL = 5 mA
TA = 25C
450
400
VID = 100 mV
VID = 1 V
350
VID = 2.5 V
300
250
2
4
6
8
1
3
5
7
9
VIC Common-Mode Input Voltage V
Figure 15
Figure 14
VOL
VOL Low-Level Output Voltage mV
VOL
VOL Low-Level Output Voltage mV
800
700
600
500
VDD = 5 V
400
300
VDD = 10 V
200
100
800
700
600
IOL = 5 mA
VID = 1 V
VIC = 0.5 V
500
2 3 4 5 6 7 8 9 10
VID Differential Input Voltage V
VDD = 5 V
400
VDD = 10 V
300
0
0
10
200
100
0
75
50
25
0
25
50
75
100
TA Free-Air Temperature C
125
Figure 17
Figure 16
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
19
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL
VOL Low-Level Output Voltage V
0.9
0.8
VDD = 5 V
0.7
VDD = 4 V
0.6
VDD = 3 V
0.5
0.4
0.2
0.1
0
1
2
3
4
5
6
7
IOL Low-Level Output Current mA
VID = 1 V
VIC = 0.5 V
TA = 25C
2.5
1.5
0.5
5
10
15
20
25
IOL Low-Level Output Current mA
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
2000
2000
AVD
AVD Large-Signal Differential
Voltage Amplification V/mV
TA = 55C
1600
1400
TA = 0C
1600
1400
1200
25C
1000
70C
800
85C
600
400
125C
200
0
0
4
6
8
10
12
VDD Supply Voltage V
14
16
RL = 1 M
1800
40C
AVD
AVD Large-Signal Differential
Voltage Amplification V/mV
RL = 1 M
1800
VDD = 10 V
1200
1000
800
600
VDD = 5 V
400
200
0
75
50
Figure 20
25
0
25
50
75
100
TA Free-Air Temperature C
Figure 21
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
20
30
Figure 19
Figure 18
VDD = 16 V
VDD = 10 V
0.3
VID = 1 V
VIC = 0.5 V
TA = 25C
VOL
VOL Low-Level Output Voltage V
125
TYPICAL CHARACTERISTICS
COMMON-MODE
INPUT VOLTAGE POSITIVE LIMIT
vs
SUPPLY VOLTAGE
10000
16
VDD = 10 V
VIC = 5 V
See Note A
1000
100
IIIB
I IO Input Bias and Offset Currents pA
IB and IIO
IIB
IIO
10
0.1
25
45
65
85
105
TA Free-Air Temperature C
125
TA = 25C
14
12
10
8
6
4
2
0
0
NOTE A: The typical values of input bias current and input offset
current below 5 pA were determined mathematically.
4
6
8
10
12
VDD Supply Voltage V
14
16
Figure 23
Figure 22
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
90
60
TA = 55C
VO = VDD/2
No Load
80
VO = VDD/2
No Load
40C
60
50
0C
40
25C
30
70C
20
125C
0
2
4
6
8
10
12
VDD Supply Voltage V
14
40
VDD = 10 V
30
20
VDD = 5 V
10
10
IDD
mA
I DD Supply Current
A
IDD
mA
I DD Supply Current
A
50
70
16
0
75
50
25
0
25
50
75
100
TA Free-Air Temperature C
125
Figure 25
Figure 24
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
21
TYPICAL CHARACTERISTICS
SLEW RATE
vs
SUPPLY VOLTAGE
SLEW RATE
vs
FREE-AIR TEMPERATURE
0.07
0.07
AV = 1
VI(PP) = 1 V
RL =1 M
CL = 20 pF
TA = 25C
See Figure 1
0.05
0.06
SR Slew Rate V/s s
0.06
0.04
0.03
0.03
0.01
0.01
4
6
8
10
12
VDD Supply Voltage V
14
0.00
75
16
VDD = 10 V
VI(PP) = 1 V
0.04
0.02
0.00
VDD = 5 V
VI(PP) = 1 V
VDD = 5 V
VI(PP) = 2.5 V
50
1.2
1.1
1
AV = 1
VIPP = 1 V
RL =1 M
CL = 20 pF
VDD = 5 V
0.9
0.8
0.7
0.6
0.5
75
50
25
0
25
50
75
100
TA Free-Air Temperature C
125
10
9
VDD = 10 V
7
6
5
TA = 125C
TA = 25C
TA = 55C
VDD = 5 V
4
3
RL = 1 M
See Figure 1
2
1
0
0.1
Figure 28
1
10
f Frequency kHz
Figure 29
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
22
125
1.4
VDD = 10 V
25
0
25
50
75
100
TA Free-Air Temperature C
Figure 27
Figure 26
1.3
RL =1 M
CL = 20 pF
AV = 1
See Figure 1
0.05
0.02
VDD = 10 V
VI(PP) = 5.5 V
100
TYPICAL CHARACTERISTICS
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
150
140
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 3
B1
B1 Unity-Gain Bandwidth kHz
B1
B1 Unity-Gain Bandwidth kHz
130
VI = 10 mV
CL = 20 pF
TA = 25C
See Figure 3
130
110
90
70
50
120
110
100
90
80
70
60
30
75
50
50
25
0
25
50
75
100
TA Free-Air Temperature C
125
6
8
10
12
VDD Supply Voltage V
14
16
Figure 31
Figure 30
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
10 7
VDD = 10 V
RL = 1 M
TA = 25C
10 5
10 4
30
AVD
10 3
10 2
60
Phase Shift
AVD
AVD Large-Signal Differential
Voltage Amplification
10 6
90
Phase Shift
10 1
120
1
0.1
1
150
10
100
1k
10 k
f Frequency Hz
100 k
180
1M
Figure 32
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
23
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
10 7
VDD = 10 V
RL = 1 M
TA = 25C
10 5
10 4
30
AVD
10 3
60
10 2
90
Phase Shift
AVD
AVD Large-Signal Differential
Voltage Amplification
10 6
Phase Shift
10 1
120
150
0.1
1
10
100
1k
10 k
f Frequency Hz
100 k
180
1M
Figure 33
PHASE MARGIN
vs
SUPPLY VOLTAGE
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
42
40
VI = 10 mV
CL = 20 pF
TA = 25C
See Figure 3
36
38
m
m Phase Margin
m
m Phase Margin
40
VDD = 5 mV
VI = 10 mV
CL = 20 pF
See Figure 3
32
36
34
28
24
32
30
0
4
6
8
10
12
VDD Supply Voltage V
14
16
20
75
50
25
25
50
75
100
TA Free-Air Temperature C
Figure 34
Figure 35
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
24
125
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
CAPACITIVE LOAD
37
33
31
29
27
25
0
10
20
30 40 50 60 70 80
CL Capacitive Load pF
90 100
VN
nV/HzHz
V n Equivalent Input Noise Voltage nV/
200
VDD = 5 mV
VI = 10 mV
TA = 25C
See Figure 3
35
m
m Phase Margin
175
150
125
100
75
50
25
0
Figure 36
10
100
f Frequency Hz
1000
Figure 37
25
APPLICATION INFORMATION
single-supply operation
While the TLC27L2 and TLC27L7 perform well using dual power supplies (also called balanced or split
supplies), the design is optimized for single-supply operation. This design includes an input common-mode
voltage range that encompasses ground as well as an output voltage range that pulls down to ground. The
supply voltage range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly
available for TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is
recommended.
Many single-supply applications require that a voltage be applied to one input to establish a reference level that
is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38).
The low input bias current of the TLC27L2 and TLC27L7 permits the use of very large resistive values to
implement the voltage divider, thus minimizing power consumption.
The TLC27L2 and TLC27L7 work well in conjunction with digital logic; however, when powering both linear
devices and digital logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, high-frequency applications may require RC decoupling.
VDD
R4
R1
R2
VI
VO
+
VREF
R3
REF
C
0.01 F
+ V
+
R3
DD R1 ) R3
VREF VI R4
R2
) V
VO
Logic
Logic
Logic
Power
Supply
VO
Logic
Logic
Logic
Power
Supply
26
REF
APPLICATION INFORMATION
input characteristics
The TLC27L2 and TLC27L7 are specified with a minimum and a maximum input voltage that, if exceeded at
either input, could cause the device to malfunction. Exceeding this specified range is a common problem,
especially in single-supply operation. Note that the lower range limit includes the negative rail, while the upper
range limit is specified at VDD 1 V at TA = 25C and at VDD 1.5 V at all other temperatures.
The use of the polysilicon-gate process and the careful input circuit design gives the TLC27L2 and TLC27L7
very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage
drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus
dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate)
alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude.
The offset voltage drift with time has been calculated to be typically 0.1 V/month, including the first month of
operation.
Because of the extremely high input impedance and resulting low bias current requirements, the TLC27L2 and
TLC27L7 are well suited for low-level signal processing; however, leakage currents on printed circuit boards
and sockets can easily exceed bias current requirements and cause a degradation in device performance. It
is good practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement
Information section). These guards should be driven from a low-impedance source at the same voltage level
as the common-mode input (see Figure 40).
Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation.
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias current requirements of the TLC27L2 and TLC27L7 result in a low noise
current, which is insignificant in most applications. This feature makes the devices especially favorable over
bipolar devices when using values of circuit impedance greater than 50 k, since bipolar devices exhibit greater
noise currents.
VO
+
(b) INVERTING AMPLIFIER
VI
VI
VI
VO
VO
output characteristics
The output stage of the TLC27L2 and TLC27L7 is designed to sink and source relatively high amounts of current
(see typical characteristics). If the output is subjected to a short-circuit condition, this high current capability can
cause device damage under certain conditions. Output current capability increases with supply voltage.
All operating characteristics of the TLC27L2 and TLC27L7 were measured using a 20-pF load. The devices
drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole
occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many
cases, adding a small amount of resistance in series with the load capacitance alleviates the problem.
27
APPLICATION INFORMATION
output characteristics (continued)
2.5 V
VO
+
VI
TA = 25C
f = 1 kHz
VI(PP) = 1 V
CL
2.5 V
(d) TEST CIRCUIT
28
APPLICATION INFORMATION
output characteristics (continued)
VDD
VI
RP
IP
VO
IF
R2
RL
IL
R1
VO
+
V V
DD O
) I ) I
F
L
P
feedback
Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for
oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads
(discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with
the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC27L2 and
TLC27L7 inputs and outputs were designed to withstand 100-mA surge currents without sustaining latch-up;
however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection
diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply
voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators.
Supply transients should be shunted by the use of decoupling capacitors (0.1 F typical) located across the
supply rails as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
29
APPLICATION INFORMATION
1/2
TLC27L2
VO1
500 k
5V
500 k
+
VO2
1/2
TLC27L2
0.1 F
500 k
500 k
VDD
100 k
Set
Reset
100 k
1/2
TLC27L2
33 k
NOTE: VDD = 5 V to 16 V
30
APPLICATION INFORMATION
VDD
VI
1/2
TLC27L7
VO
90 k
VDD
C
S1
SELECT:
AV
S1
10
X1
TLC4066
S2
100
1
9 k
S2
X2
Analog
Switch
2
1 k
NOTE: VDD = 5 V to 12 V
VI
VO
1/2
TLC27L2
100 k
+
NOTE: VDD = 5 V to 16 V
31
APPLICATION INFORMATION
0.016 F
5V
VI
10 k
10 k
+
VO
0.016 F
1/2
TLC27L2
VDD
R1
10 k
VIA
R1
10 k
VIB
VO
+
1/2
TLC27L7
R2
100 k
NOTE: VDD = 5 V to 16 V
V
+ R2 V V
IA
O
R1 IB
32
26-Mar-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Lead/Ball Finish
5962-89494032A
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
5962-8949403PA
OBSOLETE
CDIP
JG
TBD
Call TI
Call TI
5962-89494042A
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
5962-8949404PA
OBSOLETE
CDIP
JG
TBD
Call TI
Call TI
TLC27L2ACD
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2ACDG4
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2ACDR
ACTIVE
SOIC
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2ACDRG4
ACTIVE
SOIC
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2ACP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC27L2ACPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC27L2ACPSLE
OBSOLETE
SO
PS
TBD
Call TI
TLC27L2AID
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2AIDG4
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2AIDR
ACTIVE
SOIC
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2AIDRG4
ACTIVE
SOIC
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2AIP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC27L2AIPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC27L2AMFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
TLC27L2AMJG
OBSOLETE
CDIP
JG
TBD
Call TI
Call TI
TLC27L2AMJGB
OBSOLETE
CDIP
JG
TBD
Call TI
Call TI
TLC27L2BCD
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2BCDG4
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2BCDR
ACTIVE
SOIC
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2BCDRG4
ACTIVE
SOIC
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2BCP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC27L2BCPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC27L2BID
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2BIDG4
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 1
Call TI
26-Mar-2010
Orderable Device
Status (1)
Package
Type
Package
Drawing
TLC27L2BIDR
ACTIVE
SOIC
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2BIDRG4
ACTIVE
SOIC
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2BIP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC27L2BIPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC27L2CD
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2CDG4
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2CDR
ACTIVE
SOIC
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2CDRG4
ACTIVE
SOIC
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2CP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC27L2CPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC27L2CPSR
ACTIVE
SO
PS
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2CPSRG4
ACTIVE
SO
PS
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2CPW
ACTIVE
TSSOP
PW
150
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2CPWG4
ACTIVE
TSSOP
PW
150
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2CPWLE
OBSOLETE
TSSOP
PW
TLC27L2CPWR
ACTIVE
TSSOP
PW
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2CPWRG4
ACTIVE
TSSOP
PW
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2ID
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2IDG4
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2IDR
ACTIVE
SOIC
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2IDRG4
ACTIVE
SOIC
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2IP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC27L2IPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC27L2IPW
ACTIVE
TSSOP
PW
150
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2IPWG4
ACTIVE
TSSOP
PW
150
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2IPWLE
OBSOLETE
TSSOP
PW
TLC27L2IPWR
ACTIVE
TSSOP
PW
TBD
TBD
2000 Green (RoHS &
Addendum-Page 2
Lead/Ball Finish
Call TI
Call TI
CU NIPDAU
Call TI
Call TI
Level-1-260C-UNLIM
26-Mar-2010
Orderable Device
Status (1)
Package
Type
Package
Drawing
TLC27L2IPWRG4
ACTIVE
TSSOP
PW
Lead/Ball Finish
no Sb/Br)
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2MD
ACTIVE
SOIC
75
TBD
CU NIPDAU
Level-1-220C-UNLIM
TLC27L2MDG4
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
TBD
CU NIPDAU
Level-1-220C-UNLIM
CU NIPDAU
Level-1-260C-UNLIM
TLC27L2MDR
ACTIVE
SOIC
2500
TLC27L2MDRG4
ACTIVE
SOIC
TLC27L2MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
TLC27L2MJG
OBSOLETE
CDIP
JG
TBD
Call TI
Call TI
TLC27L2MJGB
OBSOLETE
CDIP
JG
TBD
Call TI
Call TI
TLC27L7CD
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
TLC27L7CDG4
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
TLC27L7CDR
ACTIVE
SOIC
CU NIPDAU
Level-1-260C-UNLIM
TLC27L7CDRG4
ACTIVE
SOIC
CU NIPDAU
Level-1-260C-UNLIM
TLC27L7CP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC27L7CPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC27L7CPSR
ACTIVE
SO
PS
CU NIPDAU
Level-1-260C-UNLIM
TLC27L7CPSRG4
ACTIVE
SO
PS
CU NIPDAU
Level-1-260C-UNLIM
TLC27L7ID
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
TLC27L7IDG4
ACTIVE
SOIC
75
CU NIPDAU
Level-1-260C-UNLIM
TLC27L7IDR
ACTIVE
SOIC
CU NIPDAU
Level-1-260C-UNLIM
TLC27L7IDRG4
ACTIVE
SOIC
CU NIPDAU
Level-1-260C-UNLIM
TLC27L7IP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC27L7IPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
TLC27L7MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
TLC27L7MJG
OBSOLETE
CDIP
JG
TBD
Call TI
Call TI
TLC27L7MJGB
OBSOLETE
CDIP
JG
TBD
Call TI
Call TI
(1)
Addendum-Page 3
26-Mar-2010
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 4
9-Dec-2010
Device
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLC27L2ACDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L2AIDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L2BCDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L2BIDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L2CDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L2CPSR
SO
PS
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
TLC27L2CPWR
TSSOP
PW
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
TLC27L2IDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L2IPWR
TSSOP
PW
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
TLC27L2MDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L7CDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L7CPSR
SO
PS
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
TLC27L7IDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
9-Dec-2010
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC27L2ACDR
SOIC
2500
340.5
338.1
20.6
TLC27L2AIDR
SOIC
2500
340.5
338.1
20.6
TLC27L2BCDR
SOIC
2500
340.5
338.1
20.6
TLC27L2BIDR
SOIC
2500
340.5
338.1
20.6
TLC27L2CDR
SOIC
2500
340.5
338.1
20.6
TLC27L2CPSR
SO
PS
2000
346.0
346.0
33.0
TLC27L2CPWR
TSSOP
PW
2000
346.0
346.0
29.0
TLC27L2IDR
SOIC
2500
340.5
338.1
20.6
TLC27L2IPWR
TSSOP
PW
2000
346.0
346.0
29.0
TLC27L2MDR
SOIC
2500
346.0
346.0
29.0
TLC27L7CDR
SOIC
2500
340.5
338.1
20.6
TLC27L7CPSR
SO
PS
2000
346.0
346.0
33.0
TLC27L7IDR
SOIC
2500
340.5
338.1
20.6
Pack Materials-Page 2
MECHANICAL DATA
MCER001A JANUARY 1995 REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
0.280 (7,11)
0.245 (6,22)
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.023 (0,58)
0.015 (0,38)
015
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
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