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Prepared By:

Engr. Bhai Nhuraisha Ibrahim Delomo















What is the meaning of SAP?




SAP

Simple-As-Possible (SAP)
The main purpose of SAP is to introduce all the crucial
ideas behind computer operation











What are the three different

generations of SAP?











There are three different generations of SAP.(SAP-1
SAP-2 SAP-3)




SAP - 1

Is the first stage in the evolution
toward modern computers.
Can only perform addition and
subtraction and no logical operation
SAP1 has six T-states (three fetch and
three execute cycles) reserved for each
instruction











SAP-1 Architecture













Define architecture




Architecture

Architecture is the conceptual design and
fundamental operational structure of a computer
system.




SAP-1 Architecture

Has a 16 x 8 memory (16 memory
locations with 8 bits in each
location.
SAP cannot store program having
more than 16 locations.












































SAP-1 Architecture




SAP 1 Architecture

1. Program Counter (PC)
- Counts from 0000-1111 and it signals the memory
address of the next instruction to be fetched and
executed.
- used for proper execution of functions of
computer by providing address of next
instruction to microprocessor.




SAP-1 Architecture

2. Input and MAR
- Memory address register
- store memory addresses
- include the address and the switch register.









3. RAM
SAP-1 Architecture

- Program code to be executed and data for SAP-1
computer is stored.
- Receives 4-bit addresses from MAR and a read
operation is performed.




SAP-1 Architecture

4. Instruction Register (IR)
- contains the instruction, composed of
OPCODE + ADDRESS.
- The contents of the IR is split into two nibbles;
upper nibble that goes directly to the controller,
sequencer and the lower nibble that is directed
into the WBUS.




SAP-1 Architecture

5. Controller sequencer
- Generates the signal for each block so that
action occur in desired sequence.
- Produces a 12- bit word that determines how the
register will react to the next positive CLK edge.




SAP-1 Architecture

6. Accumulator
- AN 8- bit buffer register that stores intermediate
results during a computer run.
- one of the operands of ADD, SUB and OUT
instructions.




SAP-1 Architecture

7. Adder / Subtractor
- A 2s complement adder-subtractor.
- Its content can change as soon as the input word
changes (asynchronous).




SAP-1 Architecture

8. B Register (Buffer Register)
- 8-bit, primarily used to hold
the other operand of
mathematical operation.




SAP-1 Architecture

9. Output register
- holds the output of the out instruction.




10. Binary display
- Row of eight LEDs to show the contents of the
output register.




FETCH CYCLE

ADDRESS STATE T1
INCREMENT STATE T2
MEMORY STATE T3




































SAP-1 clock has a frequency of 1
kHz, equivalent to a period of 1 ms.
Therefore, it takes 6 ms for a SAP-1
machine cycle
CON






Cp Ep m 1 1
A
E
A
S
u
E
u

O
Active
Address State
0 1 0 1
1 1 1 0 0 0 1 1

(T1) Ep m

Increment
1 o 1 1
1 1 1 0
0 0 1 1
Cp

State (T2)

Memory
0 0 1 0 0 1 1 0 0 0 1 1
1

State (T3)










FETCH CYCLE
CON






Cp Ep m 1 1
A
E
A
S
u
E
u

O
Active
Address State
0 1 0 1
1 1 1 0 0 0 1 1

(T1) Ep m

Increment
1 o 1 1
1 1 1 0
0 0 1 1
Cp

State (T2)

Memory
0 0 1 0 0 1 1 0 0 0 1 1
1

State (T3)










FETCH CYCLE
Example 1



If the system clock has a frequency of 2.5 MHz, how
long is an instruction cycle?



The Period of the clock is
T = 1/f = .5 MHz = 400ns
Therefore, each T state last 400ns. Since it takes 13
T states to fetch and execute the LDA instruction,
the instruction cycle lasts for
13 x 400 ns =5,200 ns = 5.2s











Counter-cp
Ep-execute
CE - Chip Enable




EXECUTION CYCLE

LDA ROUTINE
ADD ROUTINE
SUB ROUTINE
OUT ROUTINE
CON




LDA Cp Ep m 1 1
A
E
A
S
u
E
u

O
Active
LDA T4
m, 1
LDA T5 ,
A

LDA T6 NONE








EXECUTION CYCLE
SAP-1 Architecture Summary

SAP-1 control unit consists of
program counter (PC)
Instruction Register (IR)
Controller sequencer
SAP-1 ALU consists of
Accumulator
Adder-subracter
B register
SAP-1 Memory
MAR
16x8 RAM
I/O unit
Input programming switches
Output port
Binary Display




SAP-1 INSTRUCTION

LDA
ADD
SUB
OUT
HLT












PROGRAMING SAP-1




SAP-1 Instruction

LDA Load addressed memory contents into the
accumulator.
ADD content of the accumulator will be added to the
content of the memory in the address placing the sum
back to the accumulator.
SUB Subtract addressed memory contents from
accumulator.
OUT Load accumulator data into the output register.
HLT Stop Processing.
SAP-1 OP CODE (Operation Code)






Mnemonics



Opcode
LDA


0000
ADD

0001


SUB


0010


OUT


1110



HLT



1111






What is the difference between

the Assembly Language &

Machine Language?




Assembly Language

Involves working with mnemonics when writing a program
Source program




Machine Language



Involves working with strings of 0s and 1s
Object program
EXAMPLE 1

Translate this program into SAP-1 machine language



Address Instruction
0H LDA 9H
1H ADD AH
2H ADD BH
3H SUB CH
4H OUT
5H HLT
0001 0001 1010

0010 0001 1011

0011 0010 1100

0100 1110 xxxx

0101 1111 xxxx
Address Instruction
0H LDA 9H
1H ADD AH
2H ADD BH
3H SUB CH
4H OUT
5H HLT


Solution

(OPCODE

+

ADDRESS)


Address

Instruction

0000

0000 1001











Mnemonics Opcode

LDA

0000
ADD

0001
SUB 0010
OUT 1110
HLT 1111
Assignment

How would you program SAP-1 to solve this Arithmetic
problem?

16 + 20 + 24 -32

LDA
ADD
ADD
SUB
OUT
HLT
Note : Table the Address and its Contents (9H is the address, the
content of 9H is 10H ).
Use addresses 9H to CH for the data


Address Contents

0H LDA 9H
Address Contents
0000 0000 1001
0001 0001 1010
0010 0001 1011
0111 0010 1100
0100 1110 XXXX
0101 1111 XXXX
0110 XXXX XXXX
0111 XXXX XXXX
1000 XXXX XXXX
1001 0001 0000
1010 0001 0100
1011 0001 1000
1100 0010 0000

How would you program SAP-1 to solve this Arithmetic problem?

16 + 20 + 24 -32


Assembly Language
Machine Language

Address Contents
oH LDA 9H
1H ADD AH
2H ADD BH
3H SUB CH
4H OUT
5H HLT
6H XX
7H XX
8H XX
9H 10H
AH 14H
BH 18H
CH 20H

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