Version 5.

2
Lab Manual February 3, 2006
Encounter

RTL Compiler
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Table of Contents Encounter RTL Compiler
February 3, 2006 Cadence Design Systems, Inc. iii
Table of Contents
Encounter RTL Compiler
Module 1 Introduction to the Encounter RTL Compiler
Lab 1-1 Exploring the Design Hierarchy ...................................................................................... 1-1
Setting Up the Environment....................................................................................... 1-2
Navigating the Hierarchy........................................................................................... 1-4
Reading Constraints and Running Synthesis ............................................................. 1-6
Using the Graphical Interface .................................................................................... 1-7
Module 2 Design Constraints
Lab 2-1 Applying Design Constraints........................................................................................... 2-1
Setting Up the Environment....................................................................................... 2-1
Setting Load and Design Rule Checks....................................................................... 2-2
Setting Clocks ............................................................................................................ 2-3
Applying External Delays.......................................................................................... 2-4
Applying Path Exceptions.......................................................................................... 2-5
Module 3 Synthesis Flow
Lab 3-1 Exploring the Synthesis Flow.......................................................................................... 3-1
Setting Up the Environment....................................................................................... 3-1
Defining Cost Groups ................................................................................................ 3-2
Estimating Physical Wire Delays............................................................................... 3-2
Running a Generic Synthesis..................................................................................... 3-3
Mapping to a Target Library...................................................................................... 3-3
Running Incremental Synthesis ................................................................................. 3-3
Analyzing Reports ..................................................................................................... 3-5
Module 4 Low Power Synthesis
Lab 4-1 Running Low Power Synthesis........................................................................................ 4-1
Using Clock Gating.................................................................................................... 4-1
Setting Up the Environment....................................................................................... 4-2
Setting Up for Low Power Synthesis......................................................................... 4-2
Annotating RTL-Switching Activity ......................................................................... 4-3
Running Low Power Synthesis.................................................................................. 4-5
Annotating Gate-Switching Activity (Optional)........................................................ 4-6
Reporting Power ........................................................................................................ 4-7
Encounter RTL Compiler Table of Contents
iv Cadence Design Systems, Inc. February 3, 2006
Module 5 Design for Testability
Lab 5-1 Running Low Power and Scan Synthesis ........................................................................ 5-1
Setting Up the Environment....................................................................................... 5-1
Estimating Physical Wire Delays............................................................................... 5-2
Setting Up for Scan Synthesis.................................................................................... 5-2
Inserting Shadow DFT............................................................................................... 5-3
Fixing DFT Violations............................................................................................... 5-4
Running Scan Synthesis............................................................................................. 5-4
Annotating Switching Activity .................................................................................. 5-5
Configuring the Scan Chains ..................................................................................... 5-5
Running Incremental Synthesis ................................................................................. 5-5
Connecting Scan Chains ............................................................................................ 5-6
Generating Reports .................................................................................................... 5-6
Saving the Design ...................................................................................................... 5-7
Module 6 Interface to Other Tools
Lab 6-1 Interfacing with Other Tools............................................................................................ 6-1
Changing Names of Design Objects.......................................................................... 6-1
Removing Assign Statements from the Netlist.......................................................... 6-2
Adding Isolation Buffers on Input and Output .......................................................... 6-2
Controlling the Bit-Blasting of Bus Ports.................................................................. 6-3
Ungrouping the Hierarchy ......................................................................................... 6-3
Terminology Conventions
2/3/06 Cadence Design Systems, Inc. v
Mouse Use and Terminology
The basic uses of mouse buttons are shown in this graphic.
Term Action Icon Example
click Quickly press and release the specied mouse button.
On menus and forms, you use the left mouse button
most of the time.
double click Rapidly press the specied mouse button twice.
Shift-click
Control-click
Shift-Control-click
Hold down the appropriate key or keys and click a
specied mouse button.
draw through Dene a box by clicking the mouse at one corner of the
box, moving to the diagonally opposite corner with the
mouse button held down, and releasing the button.
pop up Press the middle mouse button.
pull down Move the mouse cursor to the menu name on the menu
banner, press and hold the left mouse button, move the
cursor down to highlight the menu selection, release the
mouse button to execute the selection.
Enter Type a command in a window and press Return to
execute the command.
Select Position the cursor over a command and press the left
mouse button. Choose or pick are synonyms for select.
Click left
Double
click
2
Shift
Shift- click right
Draw
through

Click
middle
To repeat last command
To undo points in a graphic
Click or select button
To choose commands
To select options on forms
Pop-up menu button
To pop up menus
To pop up options windows by double clicking
To draw objects
To select menu command on pop-up menus
Conventions Terminology
vi Cadence Design Systems, Inc. 2/3/06
Labs for Module 1
Introduction to the Encounter RTL Compiler
2/3/06 Encounter RTL Compiler 1-1
Lab 1-1 Exploring the Design Hierarchy
Lab 1-1 Exploring the Design Hierarchy
Objective: To run synthesis, to explore the design hierarchy,
and to analyze reports.
The example design provided with this module is a Verilog

description of a
Dual Tone Multi-Frequency (DTMF) receiver. In a telephone network,
DTMF is a common in-band signaling technique used for transmitting
information between network entities. DTMF signals are commonly
generated by touch-tone telephones.
Figure 1-1. DTMF Chip
1-2 Encounter RTL Compiler 2/3/06
Exploring the Design Hierarchy Lab 1-1
You need the following files to run the synthesis:
I Synthesis library
I Verilog or VHDL netlist, preferably at RTL level.
I Constraints
This is the lab directory structure.
Figure 1-2. Lab Directory Structure
Setting Up the Environment
1. Change to the work directory by entering this command:
cd rc52lab/work
2. Start the tool by entering this command:
rc -gui -logfile dtmf_chip1.log
This command opens up the graphical interface.
You can type any command interactively at the rc:/> shell prompt.
Important
You must view files in a separate xterm window, and not in the rc shell.
library
rc52lab
rtl
tcl
Verilog files
Tcl scripts
Library files
Lab run directory
work
Simulation files
sim
Additional files
etc
2/3/06 Encounter RTL Compiler 1-3
Lab 1-1 Exploring the Design Hierarchy
3. Using the rc:/> shell prompt, hide the graphical interface by
entering:
gui_hide
Tip: When you enter gui* at the rc shell, you see a list of graphical
interface (GUI) commands.
4. View the setup.g file under the tcl directory.
5. Set the environment by entering:
include ../tcl/setup.g
6. Read the libraries and specify the cells to avoid by entering:
set_attr library $LIBRARY /
set_attr avoid true SDFF*
You do not have to specify the path. The library search path was set
using the setup.g script.
7. Read the Verilog

HDL by entering:
read_hdl ${FILE_LIST}
8. Elaborate the design by entering:
elaborate dtmf_chip
The log displays a message related to creating a control flow graph
of your design. In a real design scenario, you typically attend to the
messages in detail. In this lab, you will look for any unresolved
instances.
Most typical messages, you see are CWD-#, DW-# or CDFG-#.
The CWD and DW messages are implementations of ChipWare or
DesignWare.
You can find these messages later in the /messages directory of the
rc:> shell.
The elaboration must finish with the message Done elaborating....
9. In the log file, find any unresolved instances.
Answer: ___________________________________
1-4 Encounter RTL Compiler 2/3/06
Exploring the Design Hierarchy Lab 1-1
Navigating the Hierarchy
Use the navigational commands to explore the hierarchy and to view the
attributes of design objects.
This figure illustrates the hierarchy of the design objects.
Figure 1-3. Design Hierarchy
Important
The directory structure within the compiler shell is similar to the UNIX
directory structure. Make sure you are entering your compiler commands in
the rc shell.
1. List all the attributes possible on a design object in the design
hierarchy by entering:
ls -l -a [find / -design dtmf_chip]
Notice that this ls command works just like the UNIX command.
2. As in the previous step, find the attributes of the following design
objects:
subdesign tdsp_core
instance EXECUTE_INST
port refclk
port reset (top-level port)
pin reset in the EXECUTE_INST instance
3. Change to the dtmf_chip directory under the designs directory.
cd /designs/dtmf_chip
libraries
/ (ROOT)
HDL Information (GTECH, DW...)
Design Information
Library Information (cells, wire loads...)
Printed Message Information
hdl_libraries
designs
messages
2/3/06 Encounter RTL Compiler 1-5
Lab 1-1 Exploring the Design Hierarchy
4. Navigate through the design hierarchy and the subdirectories and list
the attributes of some of the design objects.
5. Open a separate window and examine the list_subdes.tcl file under
the tcl directory.
The Tcl-based script finds all the subdesigns in the top-level design.
6. In the compiler shell, change back to the root directory:
cd /
7. Load the list_subdes.tcl script into the compiler by entering:
include list_subdes.tcl
You do not have to specify the path. The Tcl search path was set
using the setup.g script.
8. Enter the following command:
list_subdes
This command returns a list of all the instances with their directory
paths in the design hierarchy. Many such commands are in the
load_etc.tcl file under the software installation directory.
9. Some instances in this output are datapath components inferred by
the Encounter

RTL Compiler for an arithmetic operation in the

RTL.
Why does it get the prefix G2C_DP?
Answer: ___________________________________
10. Find blackboxes or unresolved instances by entering:
filter timing_model true [find / -instance *]
filter unresolved true [find / -instance *]
proc list_subdes { } {
foreach des [find / subdes *] {
foreach inst [get_attr instances $des] {
echo $des
}
}
}
1-6 Encounter RTL Compiler 2/3/06
Exploring the Design Hierarchy Lab 1-1
Reading Constraints and Running Synthesis
The next steps in a basic flow are to read your constraints and run synthesis
on your design.
1. Source the constraint file.
read_sdc dtmf_chip.sdc
The SDC file has many errors. The log file reports the errors and the
reasons. For now, ignore this error.
2. You can write out these errors into a file by entering this command:
echo $::dc::sdc_failed_commands > failed.sdc
3. Check for any missing constraints by entering:
report timing -lint
What are the errors reported?
Answer: ______________________
For now, ignore this error. You will learn about the affect of the error
after mapping the design.
4. Synthesize your design by entering:
synthesize -to_mapped -no_incr
This step takes about 12 minutes on Solaris machines and about 5
minutes on Linux machines.
5. You can check the run time using the runtime attribute.
get_attr runtime /
2/3/06 Encounter RTL Compiler 1-7
Lab 1-1 Exploring the Design Hierarchy
Using the Graphical Interface
The graphical interface of Encounter RTL Compiler is a very useful tool to
debug your design.
1. View or unhide the graphical interface.
gui_show
The interface displays three main windows:
Logical hierarchy window
HDL window
Schematic window
These windows are dynamically refreshed to identify the logical
hierarchy you currently are in.
2. Left-click DTMF_INST to select it.
Tip: Aim the mouse pointer at the top of the instance to view its
attributes, to select it, or to double click the instance name.
3. Right-click DTMF_INST.
Apop-up menu appears. You can viewthe HDL or the schematic of
the instance in a separate window.
4. Choose ToolsVdir Browser.
a. Browse through each category by clicking the + symbol.
This option expands each category to show the design objects
under that category. If the category listed is a design object, the
tool also shows the set of attributes that are set or computed for
that design object.
b. You can control what to display in this browser by choosing
PreferencesGeneralVdir Browser ls Options.
5. Choose PreferencesGeneral.
a. In the Vdir Browser ls Options section, select all the options.
1-8 Encounter RTL Compiler 2/3/06
Exploring the Design Hierarchy Lab 1-1
6. Choose PreferencesSchematic.
The Schematics Preferences form appears.
a. On the General tab, in the Display Modes section, select all the
options.
b. Click OK.
7. Choose PreferencesLogical.
The Logical Preferences form appears.
a. Select all the options.
b. Click OK.
8. In the Schematic window, move your mouse over the top of
DTMF_INST.
The internal and leakage power are displayed.
9. In the Logical browser, expand the + of the DTMF_INST module.
Right-click the DTMF_INST module and select Attributes.
Is this instance a black box or a timing module?
Answer: ____________________________
2/3/06 Encounter RTL Compiler 1-9
Lab 1-1 Exploring the Design Hierarchy
10. Double click the DTMF_INST.
The hierarchical instances under DTMF_INST are shown in the
schematic window.
The logical window highlights DTMF_INST and the HDL browser
shows the line in the HDL where the instance was instantiated.
11. Click left and drag towards the bottom-right in the design.
This action zooms into the area.
a. Click left and drag your mouse towards the top-right to zoomout
of the area.
b. Click left and drag your mouse towards bottom-left to fit the
design in the area.
12. Click left and drag towards the top-left in the design.
This action take you to a higher level of hierarchy.
13. Pan across the schematic window with your cursor keys.
14. Choose ReportsTimingWorst Path.
A window displays the worst path and the schematic of the worst
path with all the instances in the critical path.
15. Choose ReportsTimingEndpoint Histogram.
A window pops up. Set the Maximum Count to 50 and click
Apply.
What happens and why? _______________________
Read in the dtmf_chip.orig.sdc, which is more accurate. The clocks
were not properly constrained in the previously loaded timing
constraints file.
2
1-10 Encounter RTL Compiler 2/3/06
Exploring the Design Hierarchy Lab 1-1
16. To remove all the old timing constraints, use:
cd /designs/dtmf_chip/timing
rm */*
This command removes all the previous timing data from the
compiler memory.
Important
Removing all the timing data after synthesizing your design is not a
recommended step, because Encounter RTL Compiler works best with
proper constraints applied to it fromthe start. Otherwise, the design will not
be properly optimized. Because this is a practice session, you can remove
the data anyway.
17. Read the new constraints.
read_sdc dtmf_chip.orig.sdc
You do not have to synthesize again in this session.
18. Choose ReportsTimingEndpoint Histogram.
Awindowpops up. Set the Maximum Count to 50 and click Apply.
a. Double click one of the histograms.
Another window pops up with all the paths. You can view the
most critical path for that slack group and the corresponding
schematic view.
b. Click the worst path to select it. To change to another endpoint,
use your cursor keys to go up or down.
19. Explore the rest of the menus.
Summary
The navigation helps you in redirecting your efforts to the most important
aspects of your design.
End of Lab
2
Labs for Module 2
Design Constraints
2/3/06 Encounter RTL Compiler 2-1
Lab 2-1 Applying Design Constraints
Lab 2-1 Applying Design Constraints
Objective: To set the constraints, such as clocks, external
delays, false paths, and multicycle paths, after
elaboration and before synthesis.
Setting Up the Environment
In this section, you set the environment of the synthesis session, load the RTL
files, and elaborate the top level.
1. Change to the work directory.
cd rc52lab/work
2. Start the tool by entering the command:
rc -logfile dtmf_chip2.log
3. Set the environment by entering:
include ../tcl/setup.g
4. Read the libraries and specify the cells to avoid by entering:
set_attr library $LIBRARY /
set_attr avoid true SDFF*
5. Load the RTL by entering:
read_hdl ${FILE_LIST}
The variable FILE_LIST is a list of all the Verilog

RTL defined in
the setup.g file.
6. Elaborate the design.
dtmf_chip is the top-level module.
2-2 Encounter RTL Compiler 2/3/06
Applying Design Constraints Lab 2-1
7. Check the design for any problems.
check_design
What type of problems are reported?
Answer: _________________________________________
In a normal design scenario, you identify and fix the design
problems. None of the problems in this design are worth attending
to.
Therefore, go to the next step.
Setting Load and Design Rule Checks
1. Set the capacitance loading on all output ports at the top level to 2
times the load capacitance on the PAD pin of the PDIDGZ library
cell.
A nested set of find commands locates the load attribute of the pin
and assigns it to a variable called cap.
The Tcl expression [expr x * y] specifies the capacitance load on the
external_pin_cap attribute of the output ports.
2. Use ls -l -a and/or get_attribute on the tdigit_flag output port and get
the value of the external pin capacitance.
Answer: _____________________________________
What is the unit for capacitance?
Answer: _____________________________________
3. The external driver attribute on all input ports point to the
PDO04CDG library cell.
set cap [get_attr load [find [find /lib* -libcell PDIDGZ] -libpin PAD]]
set_attr external_pin_cap [expr 2*$cap] [all_outputs]
set_attr external_driver [find [find /lib* -libcell PDO04CDG] \
-libpin PAD] [all_inputs]
2/3/06 Encounter RTL Compiler 2-3
Lab 2-1 Applying Design Constraints
4. Remove the driver settings from the reset and the refclk pins.
This is usually done to prevent the buffering of the large nets during
design rule fixing. You might want to add clock trees for these nets
later in the design cycle.
5. Set max_fanout of 15 on all input pins by entering:
set_attr max_fanout 15 [all_inputs]
6. Remove the max_fanout setting from refclk and reset pins by
entering:
The max_fanout setting is a design rule check that will create a
violation for nets that exceed a specified fanout limit.
Setting Clocks
1. Set up the top-level clock.
2. Define the internal clocks of the design.
The system clock refclk goes to a PLL that produces the generated
clocks clk1x at the same frequency and clk2x at half the frequency
of the port clock refclk.
These clocks feed the TEST_CONTROL_INST, which selects
between the scan and regular clock for each of the modules in the
design.
set_attr external_driver "" [find /des* -port ports_in/reset]
set_attr external_driver "" [find /des* -port ports_in/refclk]
set_attr max_fanout "" [find /des* -port ports_in/reset]
set_attr max_fanout "" [find /des* -port ports_in/refclk]
set refclk [define_clock -p 6000 -n refclk [find /des* -port \
ports_in/refclk]]
set m_clk [define_clock -name m_clk -period 6000 \
[find [find / -instance TEST_CONTROL_INST] -pin m_clk]]
foreach CLOCK {m_rcc_clk m_spi_clk m_dsram_clk m_ram_clk m_digit_clk} {
set clock [define_clock -name ${CLOCK} -period 12000 \
[find [find / -instance TEST_CONTROL_INST] -pin ${CLOCK}]] }
2-4 Encounter RTL Compiler 2/3/06
Applying Design Constraints Lab 2-1
3. Create a latency of 2000 ps on the internal clocks by entering:
4. Model an uncertainty of 250 ps on all clocks by entering:
5. Model a fall transition and rise transition on the refclk of 20 ps on
the rise and fall edges by entering:
set_attr slew_fall 20 $refclk
set_attr slew_rise 20 $refclk
Applying External Delays
1. Set the input delay of 500 ps on all input ports and an output delay
of 500 ps on all output ports with respect to refclk.
2. Find the external output delay on the port tdigit[0] from a suitable
report of timing.
Answer: _____________________________________
Tip: Use report timing -to [find / -port port_name].
3. Set the refclk to ideal driver to avoid applying design rule constraints
to it.
In the Encounter

RTLCompiler, the clock ports will not accept any

delay setting. Therefore, the delay setting does not need to be
specifically deleted.
set_attr clock_source_late_latency 2000 [find / -clock m*clk]
set_attr clock_network_late_latency 2000 [find / -clock m*clk]
set_attr clock_setup_uncertainty 250 [find / -clock *]
external_delay -input 500 -clock refclk [all_inputs]
external_delay -output 500 -clock refclk [all_outputs]
set_attr ideal_driver true [find /des* -port ports_in/refclk]
2/3/06 Encounter RTL Compiler 2-5
Lab 2-1 Applying Design Constraints
4. Set the reset to ideal driver to avoid applying design rule constraints
to it:
Applying Path Exceptions
In this section, you set path exceptions, such as false and multicycle paths.
1. Set the false paths in the design so that the tool does not waste any
optimization cycles on these paths by entering:
2. Set up the multicycle paths in the design to the corresponding cycles
of the data.
The launch shift and the capture shift define the amount of cycles for
the slow logic path. A launch shift of 0 and a capture shift of 2 adds
one additional cycle.
3. Verify if the exception to the instance ov_flag_reg* is applied and
name the clock that drives the flip-flop from a suitable report of
timing.
Answer: ____________________________________
external_delay -input 0 -clock $refclk [find /des* -port reset]
set_attr ideal_driver true [find /des* -port ports_in/reset]
path_disable -from [find / -port reset]
path_disable -from [find / -port test_mode]
path_disable -from [find / -port scan_en]
path_disable -from [find / -port spi_data]
path_disable -from [find / -port spi_fs]
multi_cycle -to [find [find / -inst EXECUTE_INST] -inst acc_reg* ] \
-launch_shift 0 -capture_shift 2 -name ACC_REG_SLOW
multi_cycle -to [find [find / -inst EXECUTE_INST] -inst p_reg* ] \
-launch_shift 0 -capture_shift 2 -name P_REG_SLOW
multi_cycle -to [find [find / -inst EXECUTE_INST] -inst ov_flag_reg*] \
-launch_shift 0 -capture_shift 2 -n OVFLAG_REG_SLOW
2-6 Encounter RTL Compiler 2/3/06
Applying Design Constraints Lab 2-1
4. Check for any missing constraints by entering:
report timing -lint
Identify the missing constraints. Does this problem need fixing? If
so, how would you fix the problem?
Answer: __________________________________________
5. Close the software:
quit
End of Lab
Labs for Module 3
Synthesis Flow
2/3/06 Encounter RTL Compiler 3-1
Lab 3-1 Exploring the Synthesis Flow
Lab 3-1 Exploring the Synthesis Flow
Objective: To synthesize and optimize the design. To analyze
the synthesis.
Setting Up the Environment
In this section, you set the environment of the synthesis session, load the RTL
files, and elaborate the top-level design.
1. Change to the work directory:
cd rc52lab/work
2. Start the tool by entering:
rc -logfile dtmf_chip3.log
3. Set the environment by entering:
include ../tcl/setup.g
4. Read the libraries and specify the cells to avoid by entering:
set_attr library $LIBRARY /
set_attr avoid true SDFF*
5. Set the synthesis engine to work for total negative slack (TNS)
optimization.
set_attr endpoint_slack_opto true /
6. Read the design and elaborate by entering:
read_hdl $FILE_LIST
elaborate
7. Set the constraints by entering:
include constraints.g
8. After loading the constraints, run the timing lint report.
It is always a good idea to run this check.
3-2 Encounter RTL Compiler 2/3/06
Exploring the Synthesis Flow Lab 3-1
Defining Cost Groups
1. Create a cost group called INOUT in the top-level design and set a
weight of 6 on the INOUT paths by entering:
2. Create a cost group called CLK_GROUP in the top-level design and
set a weight of 10 by entering:
3. Report the timing of the cost groups.
report timing -cost_group INOUT
report timing -cost_group CLK_GROUP
What is the worst timing slack reported?
Answer: ______________________________
Estimating Physical Wire Delays
The physical layout estimator gives you an initial estimation of how the
placement and routing will affect your wire delays. This methodology also
reduces your effort in trying to obtain wire-load models suitable for your
design.
1. Load the physical library for layout estimation by entering:
set_attribute lef_library $LEF_LIBRARY /
2. Load the capacitance table by entering:
set_attribute cap_table_file $CAP_TABLE /
3. Set the interconnect mode to ple for interconnect modeling.
set_attribute interconnect_mode ple /
define_cost_group -name INOUT -design dtmf_chip -weight 8
path_group -from [all_inputs] -group INOUT -name IN_PATHS
path_group -to [all_outputs] -group INOUT -name OUT_PATHS
define_cost_group -name CLK_GROUP -design dtmf_chip -weight 10
path_group -fr [all::all_seqs] -to [all::all_seqs] -g CLK_GROUP -n REG2REG
2/3/06 Encounter RTL Compiler 3-3
Lab 3-1 Exploring the Synthesis Flow
Running a Generic Synthesis
1. Prevent the deletion of unloaded flops by entering:
set_attr delete_unloaded_seqs 0 /
2. Run generic optimization of the design by entering:
synthesize -to_generic -eff ${SYN_EFFORT}
Find out the total area of the design after synthesize -to_generic
from a suitable report of area. Does this area mean anything?
Answer: ______________________________
Mapping to a Target Library
1. Map the design and optimize the mapped design by entering the
following command:
synthesize -to_mapped -eff ${MAP_EFFORT}
This step takes about 18 minutes on Solaris machines and about 8
minutes on Linux machines.
View the several stages in the synthesis process as it runs.
What is the total area of the design after synthesize -to_mapped?
Answer: _____________________________
Running Incremental Synthesis
1. Run incremental synthesis by entering:
synthesize -incremental
This step takes about 10 minutes on Solaris machines and about 5
minutes on Linux machines.
3-4 Encounter RTL Compiler 2/3/06
Exploring the Synthesis Flow Lab 3-1
2. Report the timing of the cost groups.
report timing -cost_group INOUT
report timing -cost_group CLK_GROUP
What is the worst timing slack reported?
Answer: ______________________________
Important
You must view files in a separate xterm window, and not in the rc shell.
3. Fromthe log file, find out the total area of the design after synthesize
-to_mapped -incremental.
Answer: _____________________________
2/3/06 Encounter RTL Compiler 3-5
Lab 3-1 Exploring the Synthesis Flow
Analyzing Reports
1. From the timing report find out the following:
a. The timing slack for the design.
Answer: _____________________________________
b. Values of skew and latency. Record their values.
Answer: _____________________________________
c. Compare the values in b above with the skewand latency settings
in the constraints.g file.
Answer: _____________________________________
2. Report the timing of the EXECUTE_INST/p_reg_reg[31]/D pin:
What is the timing slack on this report?
Answer: ________________________
3. Report the area of the design:
report area >> dtmf_chip.report
What is the total area of the design?
Answer: ____________________
4. Report the design rule violations by entering:
report design_rules >> dtmf_chip.report
Are there any design rule violations?
Answer: ______________________
5. Report the gate count:
report gates >> dtmf_chip.report
What is the total instance count?
Answer: __________________
6. Save the mapped netlist.
write_hdl > dtmf_chip_mapped.netlist
3-6 Encounter RTL Compiler 2/3/06
Exploring the Synthesis Flow Lab 3-1
7. Report the quality of results by entering:
report qor > qor.synth.report
8. Write the compiler data files.
9. Close the software by entering:
quit
End of Lab
write_encounter design -base dtmf_chip_synth/dtmf_chip
Labs for Module 4
Low Power Synthesis
2/3/06 Encounter RTL Compiler 4-1
Lab 4-1 Running Low Power Synthesis
Lab 4-1 Running Low Power Synthesis
Objective: To insert clock gating for power optimization. To
optimize the leakage and dynamic power.
Using Clock Gating
The clocking strategy ensures that the flip-flop updates every clock cycle
even though the eval_data signal is valid when the enable line goes high.
Figure 4-1. Gating Circuit Using MUX for Data
You can optimize the circuit above for power consumption, ensuring that the
flip-flop is clocked only when the eval_data line is validated with the enable
signal if the clock is gated like the Clock-Gating Circuit in figure 4-2.
Figure 4-2. Clock-Gating Circuit
eval_data
enable
D_in
clk_in
Q_out
DFF
eval_data
enable
D_in
clk_g
Q_out
DFF
clk_in
4-2 Encounter RTL Compiler 2/3/06
Running Low Power Synthesis Lab 4-1
The variable lp_insert_clock_gating, if set to 1, enables clock gating during
elaboration. The tool automatically chooses the library cell for the clock
gating if no clock-gating cell is specified.
Using the clock-gating feature requires a different approach at the elaboration
stage. Before the additional clock-gating code is brought into the design, the
Encounter

RTL Compiler environment has to be modified to enable clock

gating.
Setting Up the Environment
In this section, you set the environment of the synthesis session, load the RTL
files, and elaborate the top-level design.
1. Change to the work directory:
cd rc52lab/work
2. Start the tool by entering:
rc -logfile dtmf_chip_lps.log
3. Set the environment by entering:
include ../tcl/setup.g
4. Read the libraries and specify the cells to avoid by entering:
set_attr library $LIBRARY /
set_attr avoid true SDFF*
5. Set the synthesis engine to work for total negative slack (TNS)
optimization.
set_attr endpoint_slack_opto true /
Setting Up for Low Power Synthesis
In this section, you set the variables to enable low power synthesis and tell
the compiler the style of clock gating to use before elaboration.
1. Enable clock-gating features by entering:
set_attr lp_insert_clock_gating true /
2/3/06 Encounter RTL Compiler 4-3
Lab 4-1 Running Low Power Synthesis
2. Read the design and elaborate by entering:
read_hdl $FILE_LIST
elaborate
3. After elaborating the design, run a check of the design.
It is always a good idea to run this check.
4. Set the clock-gating style by entering:
The lp_clock_gating_style variable tells the tool to use a clock-
gating cell with a latch.
5. Set the constraints by entering:
include constraints.g
include cost_groups.g
6. After loading the constraints, run the timing lint report.
It is always a good idea to run this check.
Annotating RTL-Switching Activity
At this stage, you run the simulation of the design and generate the toggle
count format (TCF) file using a simulation tool. The TCF file determines the
exact power consumption of the design.
1. View the ../tcl/sim.opt and the ../rtl/dtmf_recvr_core_test.v files.
2. Normally at this stage, you run a simulation with the Verilog

-XL
simulator in a separate terminal window.
However, in this case, the TCF file is generated for you.
3. View the ../sim/top.hier.rtl.tcf file.
The generated TCF contains two sets of numbers. One represents the
probability of the signal, and the other represents the number of
times the signal has toggled. The net and instance probabilities are
given separately.
set_attr lp_clock_gating_style latch /designs/dtmf_chip
4-4 Encounter RTL Compiler 2/3/06
Running Low Power Synthesis Lab 4-1
4. Read the RTL TCF file into the compiler.
read_tcf ../sim/top.hier.rtl.tcf
5. From the log file, gather the following information:
What is the number of pins in the TCF file?
Answer: _________
What is the coverage of this TCF?
Answer: _________
What is the total number of nets in the design?
Answer: _________
6. Report the power consumption of the design by entering:
report power -depth 1
What is the total leakage power consumption of the design?
Answer: ___________________________
What is the total switching power consumption of the design?
Answer: ___________________________
What is the total internal power consumption of the design?
Answer: ___________________________
What is the total net power consumption of the design?
Answer: ___________________________
What is the relationship between Net power, Internal power and
Switching power?
Answer: ___________________________
What is the total power consumption of the design?
Answer: ___________________________
What are the top-level blocks of the design?
Answer: ___________________________
2/3/06 Encounter RTL Compiler 4-5
Lab 4-1 Running Low Power Synthesis
7. Change the unit of power by entering:
set_attr lp_power_unit uW /
Do a report power and verify the units and data.
Note: The power annotation during mapping is not affected by the
lp_power_unit attribute.
Running Low Power Synthesis
Low power synthesis is included as part of the synthesis process.
1. Set the maximum leakage power attribute.
2. Set the maximum dynamic power attribute.
3. Synthesize the design:
synthesize -to_mapped -effort medium
Multi-VT optimization and leakage power optimization are run at
this stage.
This step takes about 5 minutes in Linux and 15 minutes in Solaris.
To get the CPU run time use the runtime root attribute.
4. Save the mapped netlist by entering:
write_hdl > dtmf_chip.lps.v
5. Report the power consumption of the gates by entering:
report gate -power
How many instances are from the slow_highvt library?
Answer: _____________________
How many instances are from the slow_normal library?
Answer: _____________________
set_attr max_leakage_power 100 /designs/dtmf_chip
set_attr max_dynamic_power 100 /designs/dtmf_chip
set_attr lp_power_optimization_weight 0.5 /designs/*
4-6 Encounter RTL Compiler 2/3/06
Running Low Power Synthesis Lab 4-1
6. Report the power consumption of the design by entering:
report power -depth 1
7. Report the datapath information by entering:
report datapath
The compiler automatically runs datapath operations unless you turn
them off using the dp_perform_* root attributes.
Are there any datapath modules? If so what type?
Answer: __________________________
8. Run incremental optimization.
synthesize -incr -effort high
Incremental optimization maps the logic added prior to this stage
and runs some additional delay and area transformations.
9. Write out the mapped netlist.
write_hdl > dtmf_chip.lps1.v
Annotating Gate-Switching Activity (Optional)
At this stage, you run the gate-level simulation of the design. You use
gate-level switching activity to better analyze and estimate the power.
1. View the ../sim/sim_gate.opt file.
2. Normally at this stage, you run a simulation with the Verilog-XL
simulator in a separate terminal window.
However, in this case, the TCF file is generated for you.
3. View the ../sim/top.hier.gates.tcf file.
4. Read the gate-level TCF file into the compiler.
From the log file, gather the following information:
What is the coverage of this TCF?
Answer: _________
2/3/06 Encounter RTL Compiler 4-7
Lab 4-1 Running Low Power Synthesis
Reporting Power
1. Report the clock gating.
report clock_gating
2. Report the power.
report power -depth 2
3. Close the software.
End of Lab
4-8 Encounter RTL Compiler 2/3/06
Running Low Power Synthesis Lab 4-1
Labs for Module 5
Design for Testability
2/3/06 Encounter RTL Compiler 5-1
Lab 5-1 Running Low Power and Scan Synthesis
Lab 5-1 Running Low Power and Scan Synthesis
Objective: To insert clock gating for power optimization. To
insert scan chains to improve the testability. To
optimize the leakage power.
Setting Up the Environment
In this section, you set the environment of the synthesis session, load the RTL
files, and elaborate the top-level design.
1. Change to the work directory:
cd rc52lab/work
2. Start the tool by entering and set the environment by entering:
rc -f -gui ../tcl/setup.g -logfile
dtmf_chip.dft.log
3. Enable clock-gating features before elaboration by entering the
following commands:
set_attr lp_insert_clock_gating true /
4. Read the libraries and specify the cells to avoid by entering:
set_attr library $LIBRARY /
The SDFF* cells avoided in previous sessions will now be required
for scan insertion.
5. Load the Verilog

files for the design and elaborate the top-level

module.
read_hdl $FILE_LIST
elaborate dtmf_chip
6. Set the clock-gating style by entering:
The lp_clock_gating_style variable tells the compiler to use a
clock-gating cell with a latch.
set_attr lp_clock_gating_style latch /designs/dtmf_chip
5-2 Encounter RTL Compiler 2/3/06
Running Low Power and Scan Synthesis Lab 5-1
7. After elaborating the design, run a check of the design.
It is always a good idea to run this check.
8. Set the constraints by entering:
include constraints.g
include cost_groups.g
9. After loading the constraints, run the timing lint report.
It is always a good idea to run this check.
Estimating Physical Wire Delays
The physical layout estimator gives you an initial estimation of how the
placement and routing will affect your wire delays. This methodology also
reduces your effort in trying to obtain wire-load models suitable for your
design.
1. Load the physical library for layout estimation by entering:
set_attribute lef_library $LEF_LIBRARY /
2. Load the capacitance table by entering:
set_attribute cap_table_file $CAP_TABLE /
3. Set the interconnect mode to ple for interconnect modeling.
set_attribute interconnect_mode ple /
Setting Up for Scan Synthesis
At this stage, you define the DFT constraints, incrementally synthesize the
design, and connect the scan chains.
1. Set the scan style to MUX scan.
set_attribute dft_scan_style muxed_scan /
2/3/06 Encounter RTL Compiler 5-3
Lab 5-1 Running Low Power and Scan Synthesis
2. Set the DFT constraints for the design.
The shift_enable and the test_mode options are necessary if you are
defining the test constraints.
Inserting Shadow DFT
1. Report the number of sequential elements in the design by entering:
report gates
2. The RAM block used in this module is untestable logic. Use the
shadow DFT logic to build testability around the logic connected to
the RAM, by entering:
3. Find and insert the shadow logic for the RAM_256x16* and the
ROM* instances.
4. Report the number of sequential elements in the design.
Has the number of sequential elements changed? Why?
Answer: ____________________________________
5. Synthesize the design to generic gates:
synthesize -to_generic
It is a good idea to run generic optimization before checking the
DFT rules.
This step takes about 5 minutes.
define_dft shift_enable -active high -create_port scan_enable
define_dft test_mode -active high test_mode
insert_shadow -around [find / -instance RAM_128x16_INST]
-mode share
-test_mode test_mode
-test_clock_pin scan_clk
-balance
5-4 Encounter RTL Compiler 2/3/06
Running Low Power and Scan Synthesis Lab 5-1
Fixing DFT Violations
1. Check the DFT rules by entering:
check_dft_rules >> dft_rules.report
Verify that all the registers have passed the DFT rules.
Identify the violations. What are the types of the violations?
Answer: __________________________________________
2. Fix any DFT violations in your design.
Tip: Use the fix_dft_violations command.
3. Check the DFT rules again to verify if there are any violations left.
Running Scan Synthesis
Low power synthesis is included as part of the synthesis process.
1. Set the scan map mode to convert the flops to scan flops.
set_attr dft_scan_map_mode tdrc_pass /design*/*
When you set the scan map mode to tdrc_pass, you convert the
flip-flops (DFF*) that pass the DFT rule checker to scan flip-flops
(SDFF*).
2. Synthesize the design:
synthesize -to_mapped
This step takes about 5 minutes.
3. Set the attribute for power analysis to high.
set_attr lp_power_analysis_effort high /
4. Report the power, clock gating and the timing of the design:
report power
report timing
report clock_gating
2/3/06 Encounter RTL Compiler 5-5
Lab 5-1 Running Low Power and Scan Synthesis
Annotating Switching Activity
At this stage, you run the simulation of the design and generate the TCF
(Toggle Count Format) file using a simulation tool. The TCF file determines
the exact power consumption of the design.
1. View the sim/top.hier.gates.tcf file.
2. Read the toggle count file by entering:
read_tcf ../sim/top.hier.gates.tcf
3. Report the power consumed by the design.
Configuring the Scan Chains
1. Set the scan input and output ports by entering:
The -create_ports option creates new ports for the scan chains.
2. Set the minimum number of scan chains required by entering:
3. Allow mixing clock edges in the scan connections.
Running Incremental Synthesis
1. Check the DFT rules to make sure the rest of the flops are scannable
by entering:
check_dft_rules >> dft_rules.report2
What is the type of violation for the unscannable flops?
Answer: __________________________________
define_dft scan_chain -create_ports -sdi tdi -sdo tdo
set_attr dft_min_number_of_scan_chains 2 /designs/*
set_attr dft_mix_clock_edges_in_scan_chains true /des*/*
5-6 Encounter RTL Compiler 2/3/06
Running Low Power and Scan Synthesis Lab 5-1
2. If there are any violations, fix the DFT violations for the remaining
unscannable flops.
Tip: Use the fix_dft_violations command.
3. Run incremental synthesis by entering:
synthesize -incremental
Incremental optimization maps all the unpreserved flip-flops that
pass the DFT rule checker with the scan equivalent cells (SDFF*).
4. Report the gates of the design and see the Dflip-flops replaced with
the scan equivalent cells (SDFF*) that were in the library.
report dft_registers
Connecting Scan Chains
1. Preview your scan chains to make sure they are correct.
2. Connect the scan chains with this command:
connect_scan_chains -auto_create_chains
Generating Reports
1. Report the scan chains, clock gating and the power.
report dft_chains
report clock_gating
report power
2. Report the scan registers and check the scan connections.
report dft_registers
3. Report the timing and the quality of results.
report timing
report qor > qor.lpsdft.report
Compare the results without low power and without scan
(qor.synth.report) to a run including them (qor.lpsdft.report).
connect_scan_chains -auto_create_chains -preview
2/3/06 Encounter RTL Compiler 5-7
Lab 5-1 Running Low Power and Scan Synthesis
Saving the Design
1. Save the constraints.
write_sdc > dtmf_chip.sdc
2. Save the netlist to disk.
write_hdl > dtmf_chip.lpsdft.v
3. Create the ATPG files for your design.
write_atpg -cadence > dtmf_chip.cadence.atpg
write_atpg -stil > dtmf_chip.stil.atpg
4. Save the scan DEF file.
write_scandef > dtmf_chip.scan.def
Important
Do not close the software. You will continue this session in the next lab.
End of Lab
5-8 Encounter RTL Compiler 2/3/06
Running Low Power and Scan Synthesis Lab 5-1
Labs for Module 6
Interface to Other Tools
2/3/06 Encounter RTL Compiler 6-1
Lab 6-1 Interfacing with Other Tools
Lab 6-1 Interfacing with Other Tools
Objective: To write a netlist that interfaces with place and route
tools by changing the names of design objects,
eliminating assign statements, and blasting the bits
of bus ports.
Continue from the previous lab session and complete the postsynthesis
processing of the netlist.
Changing Names of Design Objects
In this section, you change names of all subdesigns using LAB_ as a prefix to
match with the names of the place and route tools.
1. Check the names of all the subdesigns in the design by entering:
find /des* -subdesign *
2. Change the names of all the subdesigns to add the LAB_ prefix:
change_names -subdesign -prefix LAB_
3. Verify the changed names of all subdesigns:
find /des* -subdesign *
4. Save the mapped netlist with the changed names:
write_hdl > LAB_mod_names_netlist.v
6-2 Encounter RTL Compiler 2/3/06
Interfacing with Other Tools Lab 6-1
Removing Assign Statements from the Netlist
In this section, you remove assign statements that are not recognized by the
place and route tools.
1. Open the LAB_mod_names_netlist.v and confirm that the assign
statements are present.
2. Remove the assign statements:
insert_io_buffers -remove_assigns
The insert_io_buffers procedure is defined in the load_etc.tcl file.
You can also use the remove_assigns command to remove the assign
statements. The commands also remove assigns like a=b apart from
constant assignments.
3. Save the netlist by entering:
write_hdl > LAB_mod_noassign_netlist.v
4. Open the LAB_mod_noassign_netlist.v and confirm that the assign
statements have been removed.
Adding Isolation Buffers on Input and Output
Add isolation buffers to separate the input and output from the pads so that
the drive strength is constant.
1. Insert isolation buffers for the inputs and outputs by entering:
2. Save the new netlist:
3. Open the LAB_mod_buffered_netlist.v file and find out how many
buffers have been included in the top level to buffer input and output
ports.
Does the list match the ports of the design?
Answer: _______________
insert_io_buffers -isolate_top inouts -buffer BUFX20
write_hdl > LAB_mod_buffered_netlist.v
2/3/06 Encounter RTL Compiler 6-3
Lab 6-1 Interfacing with Other Tools
Controlling the Bit-Blasting of Bus Ports
A review of the netlist shows that multibit signals are shown only as vectors
in the module port definitions.
1. Open the bit map of the port and show each bit individually rather
than as vectors:
Some place-and-route tools require the ports to be bit-blasted, and
these are automatically generated through the write_hdl command.
2. Save the netlist and the SDC file by entering:
3. Open the LAB_mod_buffered_bb_netlist.v and confirm that the
ports in the module definitions have been broken into bits.
Ungrouping the Hierarchy
1. Create a report summary to view the hierarchy.
report hierarchy -module dtmf_chip
2. Prevent the tdsp_core and results_conv modules from being
optimized by entering:
set_attr bit_blasted_port_style %s_\{%d\}
set_attr write_vlog_bit_blast_constants true /
set_attr write_vlog_bit_blast_mapped_ports true /
write_hdl > LAB_mod_buffered_bb_netlist.v
write_sdc > lab.sdc
set_attr preserve_module 1 [find / -subdesign *results_conv*]
set_attr preserve_module 1 [find / -subdesign *tdsp_core*]
6-4 Encounter RTL Compiler 2/3/06
Interfacing with Other Tools Lab 6-1
3. Ungroup the dtmf_chip design and report the hierarchy to confirm
the ungroup results by entering:
How many instances now exist in the design hierarchy of the
session?
Answer: ___________
What is the timing slack and the area of the design?
Answer: ___________ ___________
You might need to resynthesize the design if it does not meet your
requirements.
4. Save the design files:
write_hdl > dtmf_chip.final.v
write_sdc > dtmf_chip.final.v
5. Write the compiler data files.
6. Close the software:
quit
End of Lab
ungroup -all -flatten
report hierarchy -module dtmf_chip
write_encounter design -base dtmf_chip_final/dtmf_chip