Institute / School Name School of Electronics and Electrical Engineering

Program Name B.E. (ECE)

Course Code ECL4303
Course Name Microelectronics Circuit Design
Lecture (per week) 5 Course Credits 4
Course Coordinator Name Dr. Sheifali Gupta

1. Scope and Objectives of the Course
Digital and Analog Circuit implementation with CMOS logic.
To understand the Ideal and Non Ideal effects of MOS.
Learning the MOS Fabrication basics.
To understand the concept power dissipation in MOS.

2. Textbooks
TB1: Sung-Mo Kang and Yusuf Leblebici, CMOS Digital Integrated Circuits Analysis and Design, Tata
McGraw Hill, 3
rd
Edition, 2005.
TB2: Richard C. Jaeger, Travis N. Blalock, MICROELECTRONIC CIRCUIT DESIGN, McGraw-Hill, 4
th

edition, 2011.


3. Reference Books
RB1: Neil H. E. Weste and Kamran Eshraghian ,Principles of CMOS VLSI design , Pearson, 3
rd
edition,
2005.
RB2: Jacob Millman, Arvin Grabel, MICROELECTRONICS, Tata McGraw-Hill, 2
nd
edition, 1987.

4. Other readings and relevant websites

S. No. Link of Journals, Magazines, websites and Research Papers
1 http://users.wfu.edu/matthews/courses/p230/lectures/CMOS/CMOSLogic.html
2 http://www.vlsi.wpi.edu/cds/index.htm
3. http://www.wiziq.com/tutorial/460146-CMOS-VLSI-Design-Tutorial-1
4. http://cmosedu.com/cmos1/electric/electric.htm
5. https://www.youtube.com/watch?v=35jWSQXku74
6. https://www.youtube.com/watch?v=JDROPMoNZpk



5. Course Plan


Lect. No.
(1 Hr)
Topics Text Book Section No., Page No.
UNIT 1:MOS Theory
1-2 Evolution of MOS, Historical Perspectives, A circuit
Design Example
TB1

sec 1.1 (pp.1-5)
sec 1.3 (pp.8-11)

3

VLSI Design Flow, VLSI Design Styles, Design Quality TB1 sec 1.5 (pp.21-23)
sec 1.8 (pp.28-38)
sec 1.9 (pp.38-41)


4-5 The metal Oxide Semiconductor (MOS) structure,

TB1 sec 3.1 (pp.83 -87)

6 The MOS system under External Bias,


TB1

sec 3.2 (pp.87 -90)

7-8 Structure and Operation of MOS Transistor TB1 sec 3.3 (pp.90-100)

9 Gradual channel approximation, channel length
modulation
TB1 sec 3.4 (pp.101, pp.107-
111)

10 MOSFET Capacitances

sec 3.6 (pp. 129-134)

UNIT-2: Circuit Designing and Simulation
11 Introduction to circuit designing

TB1 sec 5.1 (pp.169-174)
12-14

CMOS Logic inverter: Representation, CMOS working
DC-characteristics,
TB1

sec 5.4 (pp.197-210)

15-16 Logic gates designing with CMOS Logic, Pseudo-nMOS. TB1 sec 7.3 (pp.287-288),
pp. 291
Sec 7.4 (pp. 300-302),
(pp. 304-305)

ST 1
17 Pass transistor logic TB1 sec 7.5 (pp. 315)
18-20

D-flip-flop, SR flip-flop designing TB1

sec 8.4 (pp.336-338)
sec 8.5 (pp. 343-346)
UNIT3: MOS Memory Design and Power Estimation
21-22 Introduction to Memory Design, 1T-DRAM cell working,
Read/Write Operation
TB1

sec 10.1(pp.405-407)
sec 10.2 (pp. 419-420)

23-24 6T-SRAM Cell Working, Read/Write Operation TB1 sec 10.3 (pp.440, 443-
444)
25 Overview of Power Consumption TB1

sec 11.2 (pp.482-484,
486, 490-491)
UNIT 4: Layout designing
26-27 Introduction, Fabrication Process Flow TB1

Sec 2.1 (48)
sec 2.2 (pp.49-55)


28-30 Layout design rules (Lambda and Micron rules), Full
Custom Mask Layout Design
TB1 sec 2.4 (pp.66)
sec 2.5 (pp. 66-73)
UNIT 5: Analog Integrated Circuit Design Techniques
31-32 Small signal model for the MOS Transistor, TB2 sec 13.8.1 (pp.815-816)

33-35 Common source, Common drain and Common Gate
Amplifiers
TB2

sec 14.1.3- 14.1.5
(pp. 858-864)
36 Introduction to Current mirror circuit , DC Analysis Of
MOS Transistor Current Mirror, Changing MOS
MIRROR Ratio

TB2 sec 16.1(pp.1047-1049)
sec 16.2.1 (pp.1049-
1051)
sec 16.2.2 (pp. 1051-
1052)
ST-2
ST-3
6. Evaluation Scheme:
Component 1 Two Subjective Test 40%
Component 2 End Term Examination 60%

Total 100

Details of Component-1: There will be three sessional tests (STs) for all the theory papers as per
below stated guidelines:
(i) 1
st
sessional test will be from 0- 50% syllabus of the subject
(ii) 2
nd
sessional test will be from 51-100% syllabus of the subject.
(iii) 3
rd
sessional test will be from 0-100% syllabus of the subject.
(iv) The best two sessional tests will be considered for finalizing the internal of the subject.

Details of Component-2: The End Term Examination will be held at the end of semester. As per
academic guidelines minimum 75% attendance is required to become eligible for appearing in the
end term examination. The syllabus for end term will be from 0-100%.
This Document is approved by:
Designation Name Signature
Course Coordinator Dr. Sheifali Gupta

H.O.D Ms. Shivani Malhotra

Dean (Academics)

Date





S.
No.
Syllabus
No. of
Lectures
Weight
age
1. Unit 1 MOS Theory
Evolution of MOS, Historical Perspectives, VLSI Design Flow, VLSI
Design Styles, Design Quality, The metal Oxide Semiconductor (MOS)
structure, The MOS system under External Bias, Structure and
Operation of MOS Transistor, Gradual channel approximation, channel
length modulation, MOSFET Capacitances
10 25%
2. Unit 2- Circuit Designing and simulation
CMOS Inverter: representation, working, DC-characteristics, CMOS
Logic Circuits, Complex Logic Circuits, Clocked SR Latch, CMOS D Latch
10
25%

3. Unit 3 MOS Memory and Power Estimation
Overview of semiconductor memory types, Operation of one Transistor
DRAM Cell, Full CMOS SRAM 6T Cell Design, Read/Write Operation of
SRAM, Dynamic and static power estimation
05 15%
4. Unit 4- Layout Designing
Fabrication Process Flow, CMOS n-Well Process, Layout Design Rules

05 15%
5. Unit 5 Analog Integrated Circuit Design Techniques
Small signal model for the MOS Transistor, Common source, Common
drain and Common Gate Amplifiers, Introduction to Current mirror
circuit , DC Analysis Of MOS Transistor Current Mirror, Changing MOS
MIRROR Ratio
06 20%